1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Tim1ch",
7 extends: Some(
8 "TIM_CORE",
9 ),
10 description: Some(
11 "1-channel timers",
12 ),
13 items: &[
14 BlockItem {
15 name: "cr1",
16 description: Some(
17 "control register 1",
18 ),
19 array: None,
20 byte_offset: 0x0,
21 inner: BlockItemInner::Register(
22 Register {
23 access: Access::ReadWrite,
24 bit_size: 16,
25 fieldset: Some(
26 "Cr11ch",
27 ),
28 },
29 ),
30 },
31 BlockItem {
32 name: "dier",
33 description: Some(
34 "DMA/Interrupt enable register",
35 ),
36 array: None,
37 byte_offset: 0xc,
38 inner: BlockItemInner::Register(
39 Register {
40 access: Access::ReadWrite,
41 bit_size: 32,
42 fieldset: Some(
43 "Dier1ch",
44 ),
45 },
46 ),
47 },
48 BlockItem {
49 name: "sr",
50 description: Some(
51 "status register",
52 ),
53 array: None,
54 byte_offset: 0x10,
55 inner: BlockItemInner::Register(
56 Register {
57 access: Access::ReadWrite,
58 bit_size: 32,
59 fieldset: Some(
60 "Sr1ch",
61 ),
62 },
63 ),
64 },
65 BlockItem {
66 name: "egr",
67 description: Some(
68 "event generation register",
69 ),
70 array: None,
71 byte_offset: 0x14,
72 inner: BlockItemInner::Register(
73 Register {
74 access: Access::Write,
75 bit_size: 16,
76 fieldset: Some(
77 "Egr1ch",
78 ),
79 },
80 ),
81 },
82 BlockItem {
83 name: "ccmr_input",
84 description: Some(
85 "capture/compare mode register 1 (input mode)",
86 ),
87 array: Some(
88 Array::Regular(
89 RegularArray {
90 len: 1,
91 stride: 4,
92 },
93 ),
94 ),
95 byte_offset: 0x18,
96 inner: BlockItemInner::Register(
97 Register {
98 access: Access::ReadWrite,
99 bit_size: 32,
100 fieldset: Some(
101 "CcmrInput1ch",
102 ),
103 },
104 ),
105 },
106 BlockItem {
107 name: "ccmr_output",
108 description: Some(
109 "capture/compare mode register 1 (output mode)",
110 ),
111 array: Some(
112 Array::Regular(
113 RegularArray {
114 len: 1,
115 stride: 4,
116 },
117 ),
118 ),
119 byte_offset: 0x18,
120 inner: BlockItemInner::Register(
121 Register {
122 access: Access::ReadWrite,
123 bit_size: 32,
124 fieldset: Some(
125 "CcmrOutput1ch",
126 ),
127 },
128 ),
129 },
130 BlockItem {
131 name: "ccer",
132 description: Some(
133 "capture/compare enable register",
134 ),
135 array: None,
136 byte_offset: 0x20,
137 inner: BlockItemInner::Register(
138 Register {
139 access: Access::ReadWrite,
140 bit_size: 32,
141 fieldset: Some(
142 "Ccer1ch",
143 ),
144 },
145 ),
146 },
147 BlockItem {
148 name: "cnt",
149 description: Some(
150 "counter",
151 ),
152 array: None,
153 byte_offset: 0x24,
154 inner: BlockItemInner::Register(
155 Register {
156 access: Access::ReadWrite,
157 bit_size: 32,
158 fieldset: Some(
159 "CntCore",
160 ),
161 },
162 ),
163 },
164 BlockItem {
165 name: "psc",
166 description: Some(
167 "prescaler",
168 ),
169 array: None,
170 byte_offset: 0x28,
171 inner: BlockItemInner::Register(
172 Register {
173 access: Access::ReadWrite,
174 bit_size: 16,
175 fieldset: None,
176 },
177 ),
178 },
179 BlockItem {
180 name: "arr",
181 description: Some(
182 "auto-reload register (Dither mode disabled)",
183 ),
184 array: None,
185 byte_offset: 0x2c,
186 inner: BlockItemInner::Register(
187 Register {
188 access: Access::ReadWrite,
189 bit_size: 32,
190 fieldset: Some(
191 "ArrCore",
192 ),
193 },
194 ),
195 },
196 BlockItem {
197 name: "arr_dither",
198 description: Some(
199 "auto-reload register (Dither mode enabled)",
200 ),
201 array: None,
202 byte_offset: 0x2c,
203 inner: BlockItemInner::Register(
204 Register {
205 access: Access::ReadWrite,
206 bit_size: 32,
207 fieldset: Some(
208 "ArrDitherCore",
209 ),
210 },
211 ),
212 },
213 BlockItem {
214 name: "ccr",
215 description: Some(
216 "capture/compare register x (x=1) (Dither mode disabled)",
217 ),
218 array: Some(
219 Array::Regular(
220 RegularArray {
221 len: 1,
222 stride: 4,
223 },
224 ),
225 ),
226 byte_offset: 0x34,
227 inner: BlockItemInner::Register(
228 Register {
229 access: Access::ReadWrite,
230 bit_size: 32,
231 fieldset: Some(
232 "Ccr1ch",
233 ),
234 },
235 ),
236 },
237 BlockItem {
238 name: "ccr_dither",
239 description: Some(
240 "capture/compare register x (x=1) (Dither mode enabled)",
241 ),
242 array: Some(
243 Array::Regular(
244 RegularArray {
245 len: 1,
246 stride: 4,
247 },
248 ),
249 ),
250 byte_offset: 0x34,
251 inner: BlockItemInner::Register(
252 Register {
253 access: Access::ReadWrite,
254 bit_size: 32,
255 fieldset: Some(
256 "CcrDither1ch",
257 ),
258 },
259 ),
260 },
261 BlockItem {
262 name: "tisel",
263 description: Some(
264 "input selection register",
265 ),
266 array: None,
267 byte_offset: 0x5c,
268 inner: BlockItemInner::Register(
269 Register {
270 access: Access::ReadWrite,
271 bit_size: 32,
272 fieldset: Some(
273 "Tisel1ch",
274 ),
275 },
276 ),
277 },
278 BlockItem {
279 name: "or",
280 description: Some(
281 "Option register 1\nNote: Check Reference Manual to parse this register content",
282 ),
283 array: None,
284 byte_offset: 0x68,
285 inner: BlockItemInner::Register(
286 Register {
287 access: Access::ReadWrite,
288 bit_size: 32,
289 fieldset: None,
290 },
291 ),
292 },
293 ],
294 },
295 Block {
296 name: "Tim1chCmp",
297 extends: Some(
298 "TIM_1CH",
299 ),
300 description: Some(
301 "1-channel with one complementary output timers",
302 ),
303 items: &[
304 BlockItem {
305 name: "cr1",
306 description: Some(
307 "control register 1",
308 ),
309 array: None,
310 byte_offset: 0x0,
311 inner: BlockItemInner::Register(
312 Register {
313 access: Access::ReadWrite,
314 bit_size: 16,
315 fieldset: Some(
316 "Cr11ch",
317 ),
318 },
319 ),
320 },
321 BlockItem {
322 name: "cr2",
323 description: Some(
324 "control register 2",
325 ),
326 array: None,
327 byte_offset: 0x4,
328 inner: BlockItemInner::Register(
329 Register {
330 access: Access::ReadWrite,
331 bit_size: 32,
332 fieldset: Some(
333 "Cr21chCmp",
334 ),
335 },
336 ),
337 },
338 BlockItem {
339 name: "dier",
340 description: Some(
341 "DMA/Interrupt enable register",
342 ),
343 array: None,
344 byte_offset: 0xc,
345 inner: BlockItemInner::Register(
346 Register {
347 access: Access::ReadWrite,
348 bit_size: 32,
349 fieldset: Some(
350 "Dier1chCmp",
351 ),
352 },
353 ),
354 },
355 BlockItem {
356 name: "sr",
357 description: Some(
358 "status register",
359 ),
360 array: None,
361 byte_offset: 0x10,
362 inner: BlockItemInner::Register(
363 Register {
364 access: Access::ReadWrite,
365 bit_size: 32,
366 fieldset: Some(
367 "Sr1chCmp",
368 ),
369 },
370 ),
371 },
372 BlockItem {
373 name: "egr",
374 description: Some(
375 "event generation register",
376 ),
377 array: None,
378 byte_offset: 0x14,
379 inner: BlockItemInner::Register(
380 Register {
381 access: Access::Write,
382 bit_size: 16,
383 fieldset: Some(
384 "Egr1chCmp",
385 ),
386 },
387 ),
388 },
389 BlockItem {
390 name: "ccmr_input",
391 description: Some(
392 "capture/compare mode register 1 (input mode)",
393 ),
394 array: Some(
395 Array::Regular(
396 RegularArray {
397 len: 1,
398 stride: 4,
399 },
400 ),
401 ),
402 byte_offset: 0x18,
403 inner: BlockItemInner::Register(
404 Register {
405 access: Access::ReadWrite,
406 bit_size: 32,
407 fieldset: Some(
408 "CcmrInput1ch",
409 ),
410 },
411 ),
412 },
413 BlockItem {
414 name: "ccmr_output",
415 description: Some(
416 "capture/compare mode register 1 (output mode)",
417 ),
418 array: Some(
419 Array::Regular(
420 RegularArray {
421 len: 1,
422 stride: 4,
423 },
424 ),
425 ),
426 byte_offset: 0x18,
427 inner: BlockItemInner::Register(
428 Register {
429 access: Access::ReadWrite,
430 bit_size: 32,
431 fieldset: Some(
432 "CcmrOutput1ch",
433 ),
434 },
435 ),
436 },
437 BlockItem {
438 name: "ccer",
439 description: Some(
440 "capture/compare enable register",
441 ),
442 array: None,
443 byte_offset: 0x20,
444 inner: BlockItemInner::Register(
445 Register {
446 access: Access::ReadWrite,
447 bit_size: 32,
448 fieldset: Some(
449 "Ccer1chCmp",
450 ),
451 },
452 ),
453 },
454 BlockItem {
455 name: "cnt",
456 description: Some(
457 "counter",
458 ),
459 array: None,
460 byte_offset: 0x24,
461 inner: BlockItemInner::Register(
462 Register {
463 access: Access::ReadWrite,
464 bit_size: 32,
465 fieldset: Some(
466 "CntCore",
467 ),
468 },
469 ),
470 },
471 BlockItem {
472 name: "psc",
473 description: Some(
474 "prescaler",
475 ),
476 array: None,
477 byte_offset: 0x28,
478 inner: BlockItemInner::Register(
479 Register {
480 access: Access::ReadWrite,
481 bit_size: 16,
482 fieldset: None,
483 },
484 ),
485 },
486 BlockItem {
487 name: "arr",
488 description: Some(
489 "auto-reload register (Dither mode disabled)",
490 ),
491 array: None,
492 byte_offset: 0x2c,
493 inner: BlockItemInner::Register(
494 Register {
495 access: Access::ReadWrite,
496 bit_size: 32,
497 fieldset: Some(
498 "ArrCore",
499 ),
500 },
501 ),
502 },
503 BlockItem {
504 name: "arr_dither",
505 description: Some(
506 "auto-reload register (Dither mode enabled)",
507 ),
508 array: None,
509 byte_offset: 0x2c,
510 inner: BlockItemInner::Register(
511 Register {
512 access: Access::ReadWrite,
513 bit_size: 32,
514 fieldset: Some(
515 "ArrDitherCore",
516 ),
517 },
518 ),
519 },
520 BlockItem {
521 name: "rcr",
522 description: Some(
523 "repetition counter register",
524 ),
525 array: None,
526 byte_offset: 0x30,
527 inner: BlockItemInner::Register(
528 Register {
529 access: Access::ReadWrite,
530 bit_size: 16,
531 fieldset: Some(
532 "Rcr1chCmp",
533 ),
534 },
535 ),
536 },
537 BlockItem {
538 name: "ccr",
539 description: Some(
540 "capture/compare register x (x=1) (Dither mode disabled)",
541 ),
542 array: Some(
543 Array::Regular(
544 RegularArray {
545 len: 1,
546 stride: 4,
547 },
548 ),
549 ),
550 byte_offset: 0x34,
551 inner: BlockItemInner::Register(
552 Register {
553 access: Access::ReadWrite,
554 bit_size: 32,
555 fieldset: Some(
556 "Ccr1ch",
557 ),
558 },
559 ),
560 },
561 BlockItem {
562 name: "ccr_dither",
563 description: Some(
564 "capture/compare register x (x=1) (Dither mode enabled)",
565 ),
566 array: Some(
567 Array::Regular(
568 RegularArray {
569 len: 1,
570 stride: 4,
571 },
572 ),
573 ),
574 byte_offset: 0x34,
575 inner: BlockItemInner::Register(
576 Register {
577 access: Access::ReadWrite,
578 bit_size: 32,
579 fieldset: Some(
580 "CcrDither1ch",
581 ),
582 },
583 ),
584 },
585 BlockItem {
586 name: "bdtr",
587 description: Some(
588 "break and dead-time register",
589 ),
590 array: None,
591 byte_offset: 0x44,
592 inner: BlockItemInner::Register(
593 Register {
594 access: Access::ReadWrite,
595 bit_size: 32,
596 fieldset: Some(
597 "Bdtr1chCmp",
598 ),
599 },
600 ),
601 },
602 BlockItem {
603 name: "dtr2",
604 description: Some(
605 "break and dead-time register",
606 ),
607 array: None,
608 byte_offset: 0x54,
609 inner: BlockItemInner::Register(
610 Register {
611 access: Access::ReadWrite,
612 bit_size: 32,
613 fieldset: Some(
614 "Dtr21chCmp",
615 ),
616 },
617 ),
618 },
619 BlockItem {
620 name: "tisel",
621 description: Some(
622 "input selection register",
623 ),
624 array: None,
625 byte_offset: 0x5c,
626 inner: BlockItemInner::Register(
627 Register {
628 access: Access::ReadWrite,
629 bit_size: 32,
630 fieldset: Some(
631 "Tisel1ch",
632 ),
633 },
634 ),
635 },
636 BlockItem {
637 name: "af1",
638 description: Some(
639 "alternate function register 1",
640 ),
641 array: None,
642 byte_offset: 0x60,
643 inner: BlockItemInner::Register(
644 Register {
645 access: Access::ReadWrite,
646 bit_size: 32,
647 fieldset: Some(
648 "Af11chCmp",
649 ),
650 },
651 ),
652 },
653 BlockItem {
654 name: "af2",
655 description: Some(
656 "alternate function register 2",
657 ),
658 array: None,
659 byte_offset: 0x64,
660 inner: BlockItemInner::Register(
661 Register {
662 access: Access::ReadWrite,
663 bit_size: 32,
664 fieldset: Some(
665 "Af21chCmp",
666 ),
667 },
668 ),
669 },
670 BlockItem {
671 name: "or",
672 description: Some(
673 "Option register 1\nNote: Check Reference Manual to parse this register content",
674 ),
675 array: None,
676 byte_offset: 0x68,
677 inner: BlockItemInner::Register(
678 Register {
679 access: Access::ReadWrite,
680 bit_size: 32,
681 fieldset: None,
682 },
683 ),
684 },
685 BlockItem {
686 name: "dcr",
687 description: Some(
688 "DMA control register",
689 ),
690 array: None,
691 byte_offset: 0x3dc,
692 inner: BlockItemInner::Register(
693 Register {
694 access: Access::ReadWrite,
695 bit_size: 32,
696 fieldset: Some(
697 "Dcr1chCmp",
698 ),
699 },
700 ),
701 },
702 BlockItem {
703 name: "dmar",
704 description: Some(
705 "DMA address for full transfer",
706 ),
707 array: None,
708 byte_offset: 0x3e0,
709 inner: BlockItemInner::Register(
710 Register {
711 access: Access::ReadWrite,
712 bit_size: 32,
713 fieldset: None,
714 },
715 ),
716 },
717 ],
718 },
719 Block {
720 name: "Tim2ch",
721 extends: Some(
722 "TIM_1CH",
723 ),
724 description: Some(
725 "2-channel timers",
726 ),
727 items: &[
728 BlockItem {
729 name: "cr1",
730 description: Some(
731 "control register 1",
732 ),
733 array: None,
734 byte_offset: 0x0,
735 inner: BlockItemInner::Register(
736 Register {
737 access: Access::ReadWrite,
738 bit_size: 16,
739 fieldset: Some(
740 "Cr11ch",
741 ),
742 },
743 ),
744 },
745 BlockItem {
746 name: "cr2",
747 description: Some(
748 "control register 2",
749 ),
750 array: None,
751 byte_offset: 0x4,
752 inner: BlockItemInner::Register(
753 Register {
754 access: Access::ReadWrite,
755 bit_size: 32,
756 fieldset: Some(
757 "Cr22ch",
758 ),
759 },
760 ),
761 },
762 BlockItem {
763 name: "smcr",
764 description: Some(
765 "slave mode control register",
766 ),
767 array: None,
768 byte_offset: 0x8,
769 inner: BlockItemInner::Register(
770 Register {
771 access: Access::ReadWrite,
772 bit_size: 32,
773 fieldset: Some(
774 "Smcr2ch",
775 ),
776 },
777 ),
778 },
779 BlockItem {
780 name: "dier",
781 description: Some(
782 "DMA/Interrupt enable register",
783 ),
784 array: None,
785 byte_offset: 0xc,
786 inner: BlockItemInner::Register(
787 Register {
788 access: Access::ReadWrite,
789 bit_size: 32,
790 fieldset: Some(
791 "Dier2ch",
792 ),
793 },
794 ),
795 },
796 BlockItem {
797 name: "sr",
798 description: Some(
799 "status register",
800 ),
801 array: None,
802 byte_offset: 0x10,
803 inner: BlockItemInner::Register(
804 Register {
805 access: Access::ReadWrite,
806 bit_size: 32,
807 fieldset: Some(
808 "Sr2ch",
809 ),
810 },
811 ),
812 },
813 BlockItem {
814 name: "egr",
815 description: Some(
816 "event generation register",
817 ),
818 array: None,
819 byte_offset: 0x14,
820 inner: BlockItemInner::Register(
821 Register {
822 access: Access::Write,
823 bit_size: 16,
824 fieldset: Some(
825 "Egr2ch",
826 ),
827 },
828 ),
829 },
830 BlockItem {
831 name: "ccmr_input",
832 description: Some(
833 "capture/compare mode register 1 (input mode)",
834 ),
835 array: Some(
836 Array::Regular(
837 RegularArray {
838 len: 1,
839 stride: 4,
840 },
841 ),
842 ),
843 byte_offset: 0x18,
844 inner: BlockItemInner::Register(
845 Register {
846 access: Access::ReadWrite,
847 bit_size: 32,
848 fieldset: Some(
849 "CcmrInput2ch",
850 ),
851 },
852 ),
853 },
854 BlockItem {
855 name: "ccmr_output",
856 description: Some(
857 "capture/compare mode register 1 (output mode)",
858 ),
859 array: Some(
860 Array::Regular(
861 RegularArray {
862 len: 1,
863 stride: 4,
864 },
865 ),
866 ),
867 byte_offset: 0x18,
868 inner: BlockItemInner::Register(
869 Register {
870 access: Access::ReadWrite,
871 bit_size: 32,
872 fieldset: Some(
873 "CcmrOutput2ch",
874 ),
875 },
876 ),
877 },
878 BlockItem {
879 name: "ccer",
880 description: Some(
881 "capture/compare enable register",
882 ),
883 array: None,
884 byte_offset: 0x20,
885 inner: BlockItemInner::Register(
886 Register {
887 access: Access::ReadWrite,
888 bit_size: 32,
889 fieldset: Some(
890 "Ccer2ch",
891 ),
892 },
893 ),
894 },
895 BlockItem {
896 name: "cnt",
897 description: Some(
898 "counter",
899 ),
900 array: None,
901 byte_offset: 0x24,
902 inner: BlockItemInner::Register(
903 Register {
904 access: Access::ReadWrite,
905 bit_size: 32,
906 fieldset: Some(
907 "CntCore",
908 ),
909 },
910 ),
911 },
912 BlockItem {
913 name: "psc",
914 description: Some(
915 "prescaler",
916 ),
917 array: None,
918 byte_offset: 0x28,
919 inner: BlockItemInner::Register(
920 Register {
921 access: Access::ReadWrite,
922 bit_size: 16,
923 fieldset: None,
924 },
925 ),
926 },
927 BlockItem {
928 name: "arr",
929 description: Some(
930 "auto-reload register (Dither mode disabled)",
931 ),
932 array: None,
933 byte_offset: 0x2c,
934 inner: BlockItemInner::Register(
935 Register {
936 access: Access::ReadWrite,
937 bit_size: 32,
938 fieldset: Some(
939 "ArrCore",
940 ),
941 },
942 ),
943 },
944 BlockItem {
945 name: "arr_dither",
946 description: Some(
947 "auto-reload register (Dither mode enabled)",
948 ),
949 array: None,
950 byte_offset: 0x2c,
951 inner: BlockItemInner::Register(
952 Register {
953 access: Access::ReadWrite,
954 bit_size: 32,
955 fieldset: Some(
956 "ArrDitherCore",
957 ),
958 },
959 ),
960 },
961 BlockItem {
962 name: "ccr",
963 description: Some(
964 "capture/compare register x (x=1-2) (Dither mode disabled)",
965 ),
966 array: Some(
967 Array::Regular(
968 RegularArray {
969 len: 2,
970 stride: 4,
971 },
972 ),
973 ),
974 byte_offset: 0x34,
975 inner: BlockItemInner::Register(
976 Register {
977 access: Access::ReadWrite,
978 bit_size: 32,
979 fieldset: Some(
980 "Ccr1ch",
981 ),
982 },
983 ),
984 },
985 BlockItem {
986 name: "ccr_dither",
987 description: Some(
988 "capture/compare register x (x=1-2) (Dither mode enabled)",
989 ),
990 array: Some(
991 Array::Regular(
992 RegularArray {
993 len: 2,
994 stride: 4,
995 },
996 ),
997 ),
998 byte_offset: 0x34,
999 inner: BlockItemInner::Register(
1000 Register {
1001 access: Access::ReadWrite,
1002 bit_size: 32,
1003 fieldset: Some(
1004 "CcrDither1ch",
1005 ),
1006 },
1007 ),
1008 },
1009 BlockItem {
1010 name: "tisel",
1011 description: Some(
1012 "input selection register",
1013 ),
1014 array: None,
1015 byte_offset: 0x5c,
1016 inner: BlockItemInner::Register(
1017 Register {
1018 access: Access::ReadWrite,
1019 bit_size: 32,
1020 fieldset: Some(
1021 "Tisel2ch",
1022 ),
1023 },
1024 ),
1025 },
1026 BlockItem {
1027 name: "or",
1028 description: Some(
1029 "Option register 1\nNote: Check Reference Manual to parse this register content",
1030 ),
1031 array: None,
1032 byte_offset: 0x68,
1033 inner: BlockItemInner::Register(
1034 Register {
1035 access: Access::ReadWrite,
1036 bit_size: 32,
1037 fieldset: None,
1038 },
1039 ),
1040 },
1041 ],
1042 },
1043 Block {
1044 name: "Tim2chCmp",
1045 extends: Some(
1046 "TIM_1CH_CMP",
1047 ),
1048 description: Some(
1049 "2-channel with one complementary output timers",
1050 ),
1051 items: &[
1052 BlockItem {
1053 name: "cr1",
1054 description: Some(
1055 "control register 1",
1056 ),
1057 array: None,
1058 byte_offset: 0x0,
1059 inner: BlockItemInner::Register(
1060 Register {
1061 access: Access::ReadWrite,
1062 bit_size: 16,
1063 fieldset: Some(
1064 "Cr11ch",
1065 ),
1066 },
1067 ),
1068 },
1069 BlockItem {
1070 name: "cr2",
1071 description: Some(
1072 "control register 2",
1073 ),
1074 array: None,
1075 byte_offset: 0x4,
1076 inner: BlockItemInner::Register(
1077 Register {
1078 access: Access::ReadWrite,
1079 bit_size: 32,
1080 fieldset: Some(
1081 "Cr22chCmp",
1082 ),
1083 },
1084 ),
1085 },
1086 BlockItem {
1087 name: "smcr",
1088 description: Some(
1089 "slave mode control register",
1090 ),
1091 array: None,
1092 byte_offset: 0x8,
1093 inner: BlockItemInner::Register(
1094 Register {
1095 access: Access::ReadWrite,
1096 bit_size: 32,
1097 fieldset: Some(
1098 "Smcr2chCmp",
1099 ),
1100 },
1101 ),
1102 },
1103 BlockItem {
1104 name: "dier",
1105 description: Some(
1106 "DMA/Interrupt enable register",
1107 ),
1108 array: None,
1109 byte_offset: 0xc,
1110 inner: BlockItemInner::Register(
1111 Register {
1112 access: Access::ReadWrite,
1113 bit_size: 32,
1114 fieldset: Some(
1115 "Dier2chCmp",
1116 ),
1117 },
1118 ),
1119 },
1120 BlockItem {
1121 name: "sr",
1122 description: Some(
1123 "status register",
1124 ),
1125 array: None,
1126 byte_offset: 0x10,
1127 inner: BlockItemInner::Register(
1128 Register {
1129 access: Access::ReadWrite,
1130 bit_size: 32,
1131 fieldset: Some(
1132 "Sr2chCmp",
1133 ),
1134 },
1135 ),
1136 },
1137 BlockItem {
1138 name: "egr",
1139 description: Some(
1140 "event generation register",
1141 ),
1142 array: None,
1143 byte_offset: 0x14,
1144 inner: BlockItemInner::Register(
1145 Register {
1146 access: Access::Write,
1147 bit_size: 16,
1148 fieldset: Some(
1149 "Egr2chCmp",
1150 ),
1151 },
1152 ),
1153 },
1154 BlockItem {
1155 name: "ccmr_input",
1156 description: Some(
1157 "capture/compare mode register 1 (input mode)",
1158 ),
1159 array: Some(
1160 Array::Regular(
1161 RegularArray {
1162 len: 2,
1163 stride: 4,
1164 },
1165 ),
1166 ),
1167 byte_offset: 0x18,
1168 inner: BlockItemInner::Register(
1169 Register {
1170 access: Access::ReadWrite,
1171 bit_size: 32,
1172 fieldset: Some(
1173 "CcmrInput1ch",
1174 ),
1175 },
1176 ),
1177 },
1178 BlockItem {
1179 name: "ccmr_output",
1180 description: Some(
1181 "capture/compare mode register 1 (output mode)",
1182 ),
1183 array: Some(
1184 Array::Regular(
1185 RegularArray {
1186 len: 2,
1187 stride: 4,
1188 },
1189 ),
1190 ),
1191 byte_offset: 0x18,
1192 inner: BlockItemInner::Register(
1193 Register {
1194 access: Access::ReadWrite,
1195 bit_size: 32,
1196 fieldset: Some(
1197 "CcmrOutput1ch",
1198 ),
1199 },
1200 ),
1201 },
1202 BlockItem {
1203 name: "ccer",
1204 description: Some(
1205 "capture/compare enable register",
1206 ),
1207 array: None,
1208 byte_offset: 0x20,
1209 inner: BlockItemInner::Register(
1210 Register {
1211 access: Access::ReadWrite,
1212 bit_size: 32,
1213 fieldset: Some(
1214 "Ccer2chCmp",
1215 ),
1216 },
1217 ),
1218 },
1219 BlockItem {
1220 name: "cnt",
1221 description: Some(
1222 "counter",
1223 ),
1224 array: None,
1225 byte_offset: 0x24,
1226 inner: BlockItemInner::Register(
1227 Register {
1228 access: Access::ReadWrite,
1229 bit_size: 32,
1230 fieldset: Some(
1231 "CntCore",
1232 ),
1233 },
1234 ),
1235 },
1236 BlockItem {
1237 name: "psc",
1238 description: Some(
1239 "prescaler",
1240 ),
1241 array: None,
1242 byte_offset: 0x28,
1243 inner: BlockItemInner::Register(
1244 Register {
1245 access: Access::ReadWrite,
1246 bit_size: 16,
1247 fieldset: None,
1248 },
1249 ),
1250 },
1251 BlockItem {
1252 name: "arr",
1253 description: Some(
1254 "auto-reload register (Dither mode disabled)",
1255 ),
1256 array: None,
1257 byte_offset: 0x2c,
1258 inner: BlockItemInner::Register(
1259 Register {
1260 access: Access::ReadWrite,
1261 bit_size: 32,
1262 fieldset: Some(
1263 "ArrCore",
1264 ),
1265 },
1266 ),
1267 },
1268 BlockItem {
1269 name: "arr_dither",
1270 description: Some(
1271 "auto-reload register (Dither mode enabled)",
1272 ),
1273 array: None,
1274 byte_offset: 0x2c,
1275 inner: BlockItemInner::Register(
1276 Register {
1277 access: Access::ReadWrite,
1278 bit_size: 32,
1279 fieldset: Some(
1280 "ArrDitherCore",
1281 ),
1282 },
1283 ),
1284 },
1285 BlockItem {
1286 name: "rcr",
1287 description: Some(
1288 "repetition counter register",
1289 ),
1290 array: None,
1291 byte_offset: 0x30,
1292 inner: BlockItemInner::Register(
1293 Register {
1294 access: Access::ReadWrite,
1295 bit_size: 16,
1296 fieldset: Some(
1297 "Rcr1chCmp",
1298 ),
1299 },
1300 ),
1301 },
1302 BlockItem {
1303 name: "ccr",
1304 description: Some(
1305 "capture/compare register x (x=1-2)",
1306 ),
1307 array: Some(
1308 Array::Regular(
1309 RegularArray {
1310 len: 2,
1311 stride: 4,
1312 },
1313 ),
1314 ),
1315 byte_offset: 0x34,
1316 inner: BlockItemInner::Register(
1317 Register {
1318 access: Access::ReadWrite,
1319 bit_size: 32,
1320 fieldset: Some(
1321 "Ccr1ch",
1322 ),
1323 },
1324 ),
1325 },
1326 BlockItem {
1327 name: "ccr_dither",
1328 description: Some(
1329 "capture/compare register x (x=1-2) (Dither mode enabled)",
1330 ),
1331 array: Some(
1332 Array::Regular(
1333 RegularArray {
1334 len: 2,
1335 stride: 4,
1336 },
1337 ),
1338 ),
1339 byte_offset: 0x34,
1340 inner: BlockItemInner::Register(
1341 Register {
1342 access: Access::ReadWrite,
1343 bit_size: 32,
1344 fieldset: Some(
1345 "CcrDither1ch",
1346 ),
1347 },
1348 ),
1349 },
1350 BlockItem {
1351 name: "bdtr",
1352 description: Some(
1353 "break and dead-time register",
1354 ),
1355 array: None,
1356 byte_offset: 0x44,
1357 inner: BlockItemInner::Register(
1358 Register {
1359 access: Access::ReadWrite,
1360 bit_size: 32,
1361 fieldset: Some(
1362 "Bdtr1chCmp",
1363 ),
1364 },
1365 ),
1366 },
1367 BlockItem {
1368 name: "dtr2",
1369 description: Some(
1370 "break and dead-time register",
1371 ),
1372 array: None,
1373 byte_offset: 0x54,
1374 inner: BlockItemInner::Register(
1375 Register {
1376 access: Access::ReadWrite,
1377 bit_size: 32,
1378 fieldset: Some(
1379 "Dtr21chCmp",
1380 ),
1381 },
1382 ),
1383 },
1384 BlockItem {
1385 name: "tisel",
1386 description: Some(
1387 "input selection register",
1388 ),
1389 array: None,
1390 byte_offset: 0x5c,
1391 inner: BlockItemInner::Register(
1392 Register {
1393 access: Access::ReadWrite,
1394 bit_size: 32,
1395 fieldset: Some(
1396 "Tisel2ch",
1397 ),
1398 },
1399 ),
1400 },
1401 BlockItem {
1402 name: "af1",
1403 description: Some(
1404 "alternate function register 1",
1405 ),
1406 array: None,
1407 byte_offset: 0x60,
1408 inner: BlockItemInner::Register(
1409 Register {
1410 access: Access::ReadWrite,
1411 bit_size: 32,
1412 fieldset: Some(
1413 "Af11chCmp",
1414 ),
1415 },
1416 ),
1417 },
1418 BlockItem {
1419 name: "af2",
1420 description: Some(
1421 "alternate function register 2",
1422 ),
1423 array: None,
1424 byte_offset: 0x64,
1425 inner: BlockItemInner::Register(
1426 Register {
1427 access: Access::ReadWrite,
1428 bit_size: 32,
1429 fieldset: Some(
1430 "Af21chCmp",
1431 ),
1432 },
1433 ),
1434 },
1435 BlockItem {
1436 name: "or",
1437 description: Some(
1438 "Option register 1\nNote: Check Reference Manual to parse this register content",
1439 ),
1440 array: None,
1441 byte_offset: 0x68,
1442 inner: BlockItemInner::Register(
1443 Register {
1444 access: Access::ReadWrite,
1445 bit_size: 32,
1446 fieldset: None,
1447 },
1448 ),
1449 },
1450 BlockItem {
1451 name: "dcr",
1452 description: Some(
1453 "DMA control register",
1454 ),
1455 array: None,
1456 byte_offset: 0x3dc,
1457 inner: BlockItemInner::Register(
1458 Register {
1459 access: Access::ReadWrite,
1460 bit_size: 32,
1461 fieldset: Some(
1462 "Dcr1chCmp",
1463 ),
1464 },
1465 ),
1466 },
1467 BlockItem {
1468 name: "dmar",
1469 description: Some(
1470 "DMA address for full transfer",
1471 ),
1472 array: None,
1473 byte_offset: 0x3e0,
1474 inner: BlockItemInner::Register(
1475 Register {
1476 access: Access::ReadWrite,
1477 bit_size: 32,
1478 fieldset: None,
1479 },
1480 ),
1481 },
1482 ],
1483 },
1484 Block {
1485 name: "TimAdv",
1486 extends: Some(
1487 "TIM_2CH_CMP",
1488 ),
1489 description: Some(
1490 "Advanced Control timers",
1491 ),
1492 items: &[
1493 BlockItem {
1494 name: "cr1",
1495 description: Some(
1496 "control register 1",
1497 ),
1498 array: None,
1499 byte_offset: 0x0,
1500 inner: BlockItemInner::Register(
1501 Register {
1502 access: Access::ReadWrite,
1503 bit_size: 16,
1504 fieldset: Some(
1505 "Cr1Gp16",
1506 ),
1507 },
1508 ),
1509 },
1510 BlockItem {
1511 name: "cr2",
1512 description: Some(
1513 "control register 2",
1514 ),
1515 array: None,
1516 byte_offset: 0x4,
1517 inner: BlockItemInner::Register(
1518 Register {
1519 access: Access::ReadWrite,
1520 bit_size: 32,
1521 fieldset: Some(
1522 "Cr2Adv",
1523 ),
1524 },
1525 ),
1526 },
1527 BlockItem {
1528 name: "smcr",
1529 description: Some(
1530 "slave mode control register",
1531 ),
1532 array: None,
1533 byte_offset: 0x8,
1534 inner: BlockItemInner::Register(
1535 Register {
1536 access: Access::ReadWrite,
1537 bit_size: 32,
1538 fieldset: Some(
1539 "SmcrAdv",
1540 ),
1541 },
1542 ),
1543 },
1544 BlockItem {
1545 name: "dier",
1546 description: Some(
1547 "DMA/Interrupt enable register",
1548 ),
1549 array: None,
1550 byte_offset: 0xc,
1551 inner: BlockItemInner::Register(
1552 Register {
1553 access: Access::ReadWrite,
1554 bit_size: 32,
1555 fieldset: Some(
1556 "DierAdv",
1557 ),
1558 },
1559 ),
1560 },
1561 BlockItem {
1562 name: "sr",
1563 description: Some(
1564 "status register",
1565 ),
1566 array: None,
1567 byte_offset: 0x10,
1568 inner: BlockItemInner::Register(
1569 Register {
1570 access: Access::ReadWrite,
1571 bit_size: 32,
1572 fieldset: Some(
1573 "SrAdv",
1574 ),
1575 },
1576 ),
1577 },
1578 BlockItem {
1579 name: "egr",
1580 description: Some(
1581 "event generation register",
1582 ),
1583 array: None,
1584 byte_offset: 0x14,
1585 inner: BlockItemInner::Register(
1586 Register {
1587 access: Access::Write,
1588 bit_size: 16,
1589 fieldset: Some(
1590 "EgrAdv",
1591 ),
1592 },
1593 ),
1594 },
1595 BlockItem {
1596 name: "ccmr_input",
1597 description: Some(
1598 "capture/compare mode register 1-2 (input mode)",
1599 ),
1600 array: Some(
1601 Array::Regular(
1602 RegularArray {
1603 len: 2,
1604 stride: 4,
1605 },
1606 ),
1607 ),
1608 byte_offset: 0x18,
1609 inner: BlockItemInner::Register(
1610 Register {
1611 access: Access::ReadWrite,
1612 bit_size: 32,
1613 fieldset: Some(
1614 "CcmrInput2ch",
1615 ),
1616 },
1617 ),
1618 },
1619 BlockItem {
1620 name: "ccmr_output",
1621 description: Some(
1622 "capture/compare mode register 1-2 (output mode)",
1623 ),
1624 array: Some(
1625 Array::Regular(
1626 RegularArray {
1627 len: 2,
1628 stride: 4,
1629 },
1630 ),
1631 ),
1632 byte_offset: 0x18,
1633 inner: BlockItemInner::Register(
1634 Register {
1635 access: Access::ReadWrite,
1636 bit_size: 32,
1637 fieldset: Some(
1638 "CcmrOutputGp16",
1639 ),
1640 },
1641 ),
1642 },
1643 BlockItem {
1644 name: "ccer",
1645 description: Some(
1646 "capture/compare enable register",
1647 ),
1648 array: None,
1649 byte_offset: 0x20,
1650 inner: BlockItemInner::Register(
1651 Register {
1652 access: Access::ReadWrite,
1653 bit_size: 32,
1654 fieldset: Some(
1655 "CcerAdv",
1656 ),
1657 },
1658 ),
1659 },
1660 BlockItem {
1661 name: "cnt",
1662 description: Some(
1663 "counter",
1664 ),
1665 array: None,
1666 byte_offset: 0x24,
1667 inner: BlockItemInner::Register(
1668 Register {
1669 access: Access::ReadWrite,
1670 bit_size: 32,
1671 fieldset: Some(
1672 "CntCore",
1673 ),
1674 },
1675 ),
1676 },
1677 BlockItem {
1678 name: "psc",
1679 description: Some(
1680 "prescaler",
1681 ),
1682 array: None,
1683 byte_offset: 0x28,
1684 inner: BlockItemInner::Register(
1685 Register {
1686 access: Access::ReadWrite,
1687 bit_size: 16,
1688 fieldset: None,
1689 },
1690 ),
1691 },
1692 BlockItem {
1693 name: "arr",
1694 description: Some(
1695 "auto-reload register (Dither mode disabled)",
1696 ),
1697 array: None,
1698 byte_offset: 0x2c,
1699 inner: BlockItemInner::Register(
1700 Register {
1701 access: Access::ReadWrite,
1702 bit_size: 32,
1703 fieldset: Some(
1704 "ArrCore",
1705 ),
1706 },
1707 ),
1708 },
1709 BlockItem {
1710 name: "arr_dither",
1711 description: Some(
1712 "auto-reload register (Dither mode enabled)",
1713 ),
1714 array: None,
1715 byte_offset: 0x2c,
1716 inner: BlockItemInner::Register(
1717 Register {
1718 access: Access::ReadWrite,
1719 bit_size: 32,
1720 fieldset: Some(
1721 "ArrDitherCore",
1722 ),
1723 },
1724 ),
1725 },
1726 BlockItem {
1727 name: "rcr",
1728 description: Some(
1729 "repetition counter register",
1730 ),
1731 array: None,
1732 byte_offset: 0x30,
1733 inner: BlockItemInner::Register(
1734 Register {
1735 access: Access::ReadWrite,
1736 bit_size: 16,
1737 fieldset: Some(
1738 "RcrAdv",
1739 ),
1740 },
1741 ),
1742 },
1743 BlockItem {
1744 name: "ccr",
1745 description: Some(
1746 "capture/compare register x (x=1-4)",
1747 ),
1748 array: Some(
1749 Array::Regular(
1750 RegularArray {
1751 len: 4,
1752 stride: 4,
1753 },
1754 ),
1755 ),
1756 byte_offset: 0x34,
1757 inner: BlockItemInner::Register(
1758 Register {
1759 access: Access::ReadWrite,
1760 bit_size: 32,
1761 fieldset: Some(
1762 "Ccr1ch",
1763 ),
1764 },
1765 ),
1766 },
1767 BlockItem {
1768 name: "ccr_dither",
1769 description: Some(
1770 "capture/compare register x (x=1-2) (Dither mode enabled)",
1771 ),
1772 array: Some(
1773 Array::Regular(
1774 RegularArray {
1775 len: 2,
1776 stride: 4,
1777 },
1778 ),
1779 ),
1780 byte_offset: 0x34,
1781 inner: BlockItemInner::Register(
1782 Register {
1783 access: Access::ReadWrite,
1784 bit_size: 32,
1785 fieldset: Some(
1786 "CcrDither1ch",
1787 ),
1788 },
1789 ),
1790 },
1791 BlockItem {
1792 name: "bdtr",
1793 description: Some(
1794 "break and dead-time register",
1795 ),
1796 array: None,
1797 byte_offset: 0x44,
1798 inner: BlockItemInner::Register(
1799 Register {
1800 access: Access::ReadWrite,
1801 bit_size: 32,
1802 fieldset: Some(
1803 "BdtrAdv",
1804 ),
1805 },
1806 ),
1807 },
1808 BlockItem {
1809 name: "ccr5",
1810 description: Some(
1811 "capture/compare register 5 (Dither mode disabled)",
1812 ),
1813 array: None,
1814 byte_offset: 0x48,
1815 inner: BlockItemInner::Register(
1816 Register {
1817 access: Access::ReadWrite,
1818 bit_size: 32,
1819 fieldset: Some(
1820 "Ccr5Adv",
1821 ),
1822 },
1823 ),
1824 },
1825 BlockItem {
1826 name: "ccr5_dither",
1827 description: Some(
1828 "capture/compare register 5 (Dither mode enabled)",
1829 ),
1830 array: None,
1831 byte_offset: 0x48,
1832 inner: BlockItemInner::Register(
1833 Register {
1834 access: Access::ReadWrite,
1835 bit_size: 32,
1836 fieldset: Some(
1837 "Ccr5DitherAdv",
1838 ),
1839 },
1840 ),
1841 },
1842 BlockItem {
1843 name: "ccr6",
1844 description: Some(
1845 "capture/compare register 6 (Dither mode disabled)",
1846 ),
1847 array: None,
1848 byte_offset: 0x4c,
1849 inner: BlockItemInner::Register(
1850 Register {
1851 access: Access::ReadWrite,
1852 bit_size: 32,
1853 fieldset: Some(
1854 "Ccr1ch",
1855 ),
1856 },
1857 ),
1858 },
1859 BlockItem {
1860 name: "ccr6_dither",
1861 description: Some(
1862 "capture/compare register 6 (Dither mode enabled)",
1863 ),
1864 array: None,
1865 byte_offset: 0x4c,
1866 inner: BlockItemInner::Register(
1867 Register {
1868 access: Access::ReadWrite,
1869 bit_size: 32,
1870 fieldset: Some(
1871 "CcrDither1ch",
1872 ),
1873 },
1874 ),
1875 },
1876 BlockItem {
1877 name: "ccmr3",
1878 description: Some(
1879 "capture/compare mode register 3",
1880 ),
1881 array: None,
1882 byte_offset: 0x50,
1883 inner: BlockItemInner::Register(
1884 Register {
1885 access: Access::ReadWrite,
1886 bit_size: 32,
1887 fieldset: Some(
1888 "Ccmr3Adv",
1889 ),
1890 },
1891 ),
1892 },
1893 BlockItem {
1894 name: "dtr2",
1895 description: Some(
1896 "break and dead-time register",
1897 ),
1898 array: None,
1899 byte_offset: 0x54,
1900 inner: BlockItemInner::Register(
1901 Register {
1902 access: Access::ReadWrite,
1903 bit_size: 32,
1904 fieldset: Some(
1905 "Dtr21chCmp",
1906 ),
1907 },
1908 ),
1909 },
1910 BlockItem {
1911 name: "ecr",
1912 description: Some(
1913 "encoder control register",
1914 ),
1915 array: None,
1916 byte_offset: 0x58,
1917 inner: BlockItemInner::Register(
1918 Register {
1919 access: Access::ReadWrite,
1920 bit_size: 32,
1921 fieldset: Some(
1922 "EcrGp16",
1923 ),
1924 },
1925 ),
1926 },
1927 BlockItem {
1928 name: "tisel",
1929 description: Some(
1930 "input selection register",
1931 ),
1932 array: None,
1933 byte_offset: 0x5c,
1934 inner: BlockItemInner::Register(
1935 Register {
1936 access: Access::ReadWrite,
1937 bit_size: 32,
1938 fieldset: Some(
1939 "TiselGp16",
1940 ),
1941 },
1942 ),
1943 },
1944 BlockItem {
1945 name: "af1",
1946 description: Some(
1947 "alternate function register 1",
1948 ),
1949 array: None,
1950 byte_offset: 0x60,
1951 inner: BlockItemInner::Register(
1952 Register {
1953 access: Access::ReadWrite,
1954 bit_size: 32,
1955 fieldset: Some(
1956 "Af1Adv",
1957 ),
1958 },
1959 ),
1960 },
1961 BlockItem {
1962 name: "af2",
1963 description: Some(
1964 "alternate function register 2",
1965 ),
1966 array: None,
1967 byte_offset: 0x64,
1968 inner: BlockItemInner::Register(
1969 Register {
1970 access: Access::ReadWrite,
1971 bit_size: 32,
1972 fieldset: Some(
1973 "Af2Adv",
1974 ),
1975 },
1976 ),
1977 },
1978 BlockItem {
1979 name: "or",
1980 description: Some(
1981 "Option register 1\nNote: Check Reference Manual to parse this register content",
1982 ),
1983 array: None,
1984 byte_offset: 0x68,
1985 inner: BlockItemInner::Register(
1986 Register {
1987 access: Access::ReadWrite,
1988 bit_size: 32,
1989 fieldset: None,
1990 },
1991 ),
1992 },
1993 BlockItem {
1994 name: "dcr",
1995 description: Some(
1996 "DMA control register",
1997 ),
1998 array: None,
1999 byte_offset: 0x3dc,
2000 inner: BlockItemInner::Register(
2001 Register {
2002 access: Access::ReadWrite,
2003 bit_size: 32,
2004 fieldset: Some(
2005 "Dcr1chCmp",
2006 ),
2007 },
2008 ),
2009 },
2010 BlockItem {
2011 name: "dmar",
2012 description: Some(
2013 "DMA address for full transfer",
2014 ),
2015 array: None,
2016 byte_offset: 0x3e0,
2017 inner: BlockItemInner::Register(
2018 Register {
2019 access: Access::ReadWrite,
2020 bit_size: 32,
2021 fieldset: None,
2022 },
2023 ),
2024 },
2025 ],
2026 },
2027 Block {
2028 name: "TimBasic",
2029 extends: Some(
2030 "TIM_BASIC_NO_CR2",
2031 ),
2032 description: Some(
2033 "Basic timers",
2034 ),
2035 items: &[
2036 BlockItem {
2037 name: "cr1",
2038 description: Some(
2039 "control register 1",
2040 ),
2041 array: None,
2042 byte_offset: 0x0,
2043 inner: BlockItemInner::Register(
2044 Register {
2045 access: Access::ReadWrite,
2046 bit_size: 16,
2047 fieldset: Some(
2048 "Cr1Core",
2049 ),
2050 },
2051 ),
2052 },
2053 BlockItem {
2054 name: "cr2",
2055 description: Some(
2056 "control register 2",
2057 ),
2058 array: None,
2059 byte_offset: 0x4,
2060 inner: BlockItemInner::Register(
2061 Register {
2062 access: Access::ReadWrite,
2063 bit_size: 32,
2064 fieldset: Some(
2065 "Cr2Basic",
2066 ),
2067 },
2068 ),
2069 },
2070 BlockItem {
2071 name: "dier",
2072 description: Some(
2073 "DMA/Interrupt enable register",
2074 ),
2075 array: None,
2076 byte_offset: 0xc,
2077 inner: BlockItemInner::Register(
2078 Register {
2079 access: Access::ReadWrite,
2080 bit_size: 32,
2081 fieldset: Some(
2082 "DierBasicNoCr2",
2083 ),
2084 },
2085 ),
2086 },
2087 BlockItem {
2088 name: "sr",
2089 description: Some(
2090 "status register",
2091 ),
2092 array: None,
2093 byte_offset: 0x10,
2094 inner: BlockItemInner::Register(
2095 Register {
2096 access: Access::ReadWrite,
2097 bit_size: 32,
2098 fieldset: Some(
2099 "SrCore",
2100 ),
2101 },
2102 ),
2103 },
2104 BlockItem {
2105 name: "egr",
2106 description: Some(
2107 "event generation register",
2108 ),
2109 array: None,
2110 byte_offset: 0x14,
2111 inner: BlockItemInner::Register(
2112 Register {
2113 access: Access::Write,
2114 bit_size: 16,
2115 fieldset: Some(
2116 "EgrCore",
2117 ),
2118 },
2119 ),
2120 },
2121 BlockItem {
2122 name: "cnt",
2123 description: Some(
2124 "counter",
2125 ),
2126 array: None,
2127 byte_offset: 0x24,
2128 inner: BlockItemInner::Register(
2129 Register {
2130 access: Access::ReadWrite,
2131 bit_size: 32,
2132 fieldset: Some(
2133 "CntCore",
2134 ),
2135 },
2136 ),
2137 },
2138 BlockItem {
2139 name: "psc",
2140 description: Some(
2141 "prescaler",
2142 ),
2143 array: None,
2144 byte_offset: 0x28,
2145 inner: BlockItemInner::Register(
2146 Register {
2147 access: Access::ReadWrite,
2148 bit_size: 16,
2149 fieldset: None,
2150 },
2151 ),
2152 },
2153 BlockItem {
2154 name: "arr",
2155 description: Some(
2156 "auto-reload register (Dither mode disabled)",
2157 ),
2158 array: None,
2159 byte_offset: 0x2c,
2160 inner: BlockItemInner::Register(
2161 Register {
2162 access: Access::ReadWrite,
2163 bit_size: 32,
2164 fieldset: Some(
2165 "ArrCore",
2166 ),
2167 },
2168 ),
2169 },
2170 BlockItem {
2171 name: "arr_dither",
2172 description: Some(
2173 "auto-reload register (Dither mode enabled)",
2174 ),
2175 array: None,
2176 byte_offset: 0x2c,
2177 inner: BlockItemInner::Register(
2178 Register {
2179 access: Access::ReadWrite,
2180 bit_size: 32,
2181 fieldset: Some(
2182 "ArrDitherCore",
2183 ),
2184 },
2185 ),
2186 },
2187 ],
2188 },
2189 Block {
2190 name: "TimBasicNoCr2",
2191 extends: Some(
2192 "TIM_CORE",
2193 ),
2194 description: Some(
2195 "Virtual Basic timers without CR2 register for common part of TIM_BASIC and TIM_1CH_CMP",
2196 ),
2197 items: &[
2198 BlockItem {
2199 name: "cr1",
2200 description: Some(
2201 "control register 1",
2202 ),
2203 array: None,
2204 byte_offset: 0x0,
2205 inner: BlockItemInner::Register(
2206 Register {
2207 access: Access::ReadWrite,
2208 bit_size: 16,
2209 fieldset: Some(
2210 "Cr1Core",
2211 ),
2212 },
2213 ),
2214 },
2215 BlockItem {
2216 name: "dier",
2217 description: Some(
2218 "DMA/Interrupt enable register",
2219 ),
2220 array: None,
2221 byte_offset: 0xc,
2222 inner: BlockItemInner::Register(
2223 Register {
2224 access: Access::ReadWrite,
2225 bit_size: 32,
2226 fieldset: Some(
2227 "DierBasicNoCr2",
2228 ),
2229 },
2230 ),
2231 },
2232 BlockItem {
2233 name: "sr",
2234 description: Some(
2235 "status register",
2236 ),
2237 array: None,
2238 byte_offset: 0x10,
2239 inner: BlockItemInner::Register(
2240 Register {
2241 access: Access::ReadWrite,
2242 bit_size: 32,
2243 fieldset: Some(
2244 "SrCore",
2245 ),
2246 },
2247 ),
2248 },
2249 BlockItem {
2250 name: "egr",
2251 description: Some(
2252 "event generation register",
2253 ),
2254 array: None,
2255 byte_offset: 0x14,
2256 inner: BlockItemInner::Register(
2257 Register {
2258 access: Access::Write,
2259 bit_size: 16,
2260 fieldset: Some(
2261 "EgrCore",
2262 ),
2263 },
2264 ),
2265 },
2266 BlockItem {
2267 name: "cnt",
2268 description: Some(
2269 "counter",
2270 ),
2271 array: None,
2272 byte_offset: 0x24,
2273 inner: BlockItemInner::Register(
2274 Register {
2275 access: Access::ReadWrite,
2276 bit_size: 32,
2277 fieldset: Some(
2278 "CntCore",
2279 ),
2280 },
2281 ),
2282 },
2283 BlockItem {
2284 name: "psc",
2285 description: Some(
2286 "prescaler",
2287 ),
2288 array: None,
2289 byte_offset: 0x28,
2290 inner: BlockItemInner::Register(
2291 Register {
2292 access: Access::ReadWrite,
2293 bit_size: 16,
2294 fieldset: None,
2295 },
2296 ),
2297 },
2298 BlockItem {
2299 name: "arr",
2300 description: Some(
2301 "auto-reload register (Dither mode disabled)",
2302 ),
2303 array: None,
2304 byte_offset: 0x2c,
2305 inner: BlockItemInner::Register(
2306 Register {
2307 access: Access::ReadWrite,
2308 bit_size: 32,
2309 fieldset: Some(
2310 "ArrCore",
2311 ),
2312 },
2313 ),
2314 },
2315 BlockItem {
2316 name: "arr_dither",
2317 description: Some(
2318 "auto-reload register (Dither mode enabled)",
2319 ),
2320 array: None,
2321 byte_offset: 0x2c,
2322 inner: BlockItemInner::Register(
2323 Register {
2324 access: Access::ReadWrite,
2325 bit_size: 32,
2326 fieldset: Some(
2327 "ArrDitherCore",
2328 ),
2329 },
2330 ),
2331 },
2332 ],
2333 },
2334 Block {
2335 name: "TimCore",
2336 extends: None,
2337 description: Some(
2338 "Virtual timer for common part of TIM_BASIC and TIM_1CH",
2339 ),
2340 items: &[
2341 BlockItem {
2342 name: "cr1",
2343 description: Some(
2344 "control register 1",
2345 ),
2346 array: None,
2347 byte_offset: 0x0,
2348 inner: BlockItemInner::Register(
2349 Register {
2350 access: Access::ReadWrite,
2351 bit_size: 16,
2352 fieldset: Some(
2353 "Cr1Core",
2354 ),
2355 },
2356 ),
2357 },
2358 BlockItem {
2359 name: "dier",
2360 description: Some(
2361 "DMA/Interrupt enable register",
2362 ),
2363 array: None,
2364 byte_offset: 0xc,
2365 inner: BlockItemInner::Register(
2366 Register {
2367 access: Access::ReadWrite,
2368 bit_size: 32,
2369 fieldset: Some(
2370 "DierCore",
2371 ),
2372 },
2373 ),
2374 },
2375 BlockItem {
2376 name: "sr",
2377 description: Some(
2378 "status register",
2379 ),
2380 array: None,
2381 byte_offset: 0x10,
2382 inner: BlockItemInner::Register(
2383 Register {
2384 access: Access::ReadWrite,
2385 bit_size: 32,
2386 fieldset: Some(
2387 "SrCore",
2388 ),
2389 },
2390 ),
2391 },
2392 BlockItem {
2393 name: "egr",
2394 description: Some(
2395 "event generation register",
2396 ),
2397 array: None,
2398 byte_offset: 0x14,
2399 inner: BlockItemInner::Register(
2400 Register {
2401 access: Access::Write,
2402 bit_size: 16,
2403 fieldset: Some(
2404 "EgrCore",
2405 ),
2406 },
2407 ),
2408 },
2409 BlockItem {
2410 name: "cnt",
2411 description: Some(
2412 "counter",
2413 ),
2414 array: None,
2415 byte_offset: 0x24,
2416 inner: BlockItemInner::Register(
2417 Register {
2418 access: Access::ReadWrite,
2419 bit_size: 32,
2420 fieldset: Some(
2421 "CntCore",
2422 ),
2423 },
2424 ),
2425 },
2426 BlockItem {
2427 name: "psc",
2428 description: Some(
2429 "prescaler",
2430 ),
2431 array: None,
2432 byte_offset: 0x28,
2433 inner: BlockItemInner::Register(
2434 Register {
2435 access: Access::ReadWrite,
2436 bit_size: 16,
2437 fieldset: None,
2438 },
2439 ),
2440 },
2441 BlockItem {
2442 name: "arr",
2443 description: Some(
2444 "auto-reload register (Dither mode disabled)",
2445 ),
2446 array: None,
2447 byte_offset: 0x2c,
2448 inner: BlockItemInner::Register(
2449 Register {
2450 access: Access::ReadWrite,
2451 bit_size: 32,
2452 fieldset: Some(
2453 "ArrCore",
2454 ),
2455 },
2456 ),
2457 },
2458 BlockItem {
2459 name: "arr_dither",
2460 description: Some(
2461 "auto-reload register (Dither mode enabled)",
2462 ),
2463 array: None,
2464 byte_offset: 0x2c,
2465 inner: BlockItemInner::Register(
2466 Register {
2467 access: Access::ReadWrite,
2468 bit_size: 32,
2469 fieldset: Some(
2470 "ArrDitherCore",
2471 ),
2472 },
2473 ),
2474 },
2475 ],
2476 },
2477 Block {
2478 name: "TimGp16",
2479 extends: Some(
2480 "TIM_2CH",
2481 ),
2482 description: Some(
2483 "General purpose 16-bit timers",
2484 ),
2485 items: &[
2486 BlockItem {
2487 name: "cr1",
2488 description: Some(
2489 "control register 1",
2490 ),
2491 array: None,
2492 byte_offset: 0x0,
2493 inner: BlockItemInner::Register(
2494 Register {
2495 access: Access::ReadWrite,
2496 bit_size: 16,
2497 fieldset: Some(
2498 "Cr1Gp16",
2499 ),
2500 },
2501 ),
2502 },
2503 BlockItem {
2504 name: "cr2",
2505 description: Some(
2506 "control register 2",
2507 ),
2508 array: None,
2509 byte_offset: 0x4,
2510 inner: BlockItemInner::Register(
2511 Register {
2512 access: Access::ReadWrite,
2513 bit_size: 32,
2514 fieldset: Some(
2515 "Cr2Gp16",
2516 ),
2517 },
2518 ),
2519 },
2520 BlockItem {
2521 name: "smcr",
2522 description: Some(
2523 "slave mode control register",
2524 ),
2525 array: None,
2526 byte_offset: 0x8,
2527 inner: BlockItemInner::Register(
2528 Register {
2529 access: Access::ReadWrite,
2530 bit_size: 32,
2531 fieldset: Some(
2532 "SmcrGp16",
2533 ),
2534 },
2535 ),
2536 },
2537 BlockItem {
2538 name: "dier",
2539 description: Some(
2540 "DMA/Interrupt enable register",
2541 ),
2542 array: None,
2543 byte_offset: 0xc,
2544 inner: BlockItemInner::Register(
2545 Register {
2546 access: Access::ReadWrite,
2547 bit_size: 32,
2548 fieldset: Some(
2549 "DierGp16",
2550 ),
2551 },
2552 ),
2553 },
2554 BlockItem {
2555 name: "sr",
2556 description: Some(
2557 "status register",
2558 ),
2559 array: None,
2560 byte_offset: 0x10,
2561 inner: BlockItemInner::Register(
2562 Register {
2563 access: Access::ReadWrite,
2564 bit_size: 32,
2565 fieldset: Some(
2566 "SrGp16",
2567 ),
2568 },
2569 ),
2570 },
2571 BlockItem {
2572 name: "egr",
2573 description: Some(
2574 "event generation register",
2575 ),
2576 array: None,
2577 byte_offset: 0x14,
2578 inner: BlockItemInner::Register(
2579 Register {
2580 access: Access::Write,
2581 bit_size: 16,
2582 fieldset: Some(
2583 "EgrGp16",
2584 ),
2585 },
2586 ),
2587 },
2588 BlockItem {
2589 name: "ccmr_input",
2590 description: Some(
2591 "capture/compare mode register 1-2 (input mode)",
2592 ),
2593 array: Some(
2594 Array::Regular(
2595 RegularArray {
2596 len: 2,
2597 stride: 4,
2598 },
2599 ),
2600 ),
2601 byte_offset: 0x18,
2602 inner: BlockItemInner::Register(
2603 Register {
2604 access: Access::ReadWrite,
2605 bit_size: 32,
2606 fieldset: Some(
2607 "CcmrInput2ch",
2608 ),
2609 },
2610 ),
2611 },
2612 BlockItem {
2613 name: "ccmr_output",
2614 description: Some(
2615 "capture/compare mode register 1-2 (output mode)",
2616 ),
2617 array: Some(
2618 Array::Regular(
2619 RegularArray {
2620 len: 2,
2621 stride: 4,
2622 },
2623 ),
2624 ),
2625 byte_offset: 0x18,
2626 inner: BlockItemInner::Register(
2627 Register {
2628 access: Access::ReadWrite,
2629 bit_size: 32,
2630 fieldset: Some(
2631 "CcmrOutputGp16",
2632 ),
2633 },
2634 ),
2635 },
2636 BlockItem {
2637 name: "ccer",
2638 description: Some(
2639 "capture/compare enable register",
2640 ),
2641 array: None,
2642 byte_offset: 0x20,
2643 inner: BlockItemInner::Register(
2644 Register {
2645 access: Access::ReadWrite,
2646 bit_size: 32,
2647 fieldset: Some(
2648 "CcerGp16",
2649 ),
2650 },
2651 ),
2652 },
2653 BlockItem {
2654 name: "cnt",
2655 description: Some(
2656 "counter",
2657 ),
2658 array: None,
2659 byte_offset: 0x24,
2660 inner: BlockItemInner::Register(
2661 Register {
2662 access: Access::ReadWrite,
2663 bit_size: 32,
2664 fieldset: Some(
2665 "CntCore",
2666 ),
2667 },
2668 ),
2669 },
2670 BlockItem {
2671 name: "psc",
2672 description: Some(
2673 "prescaler",
2674 ),
2675 array: None,
2676 byte_offset: 0x28,
2677 inner: BlockItemInner::Register(
2678 Register {
2679 access: Access::ReadWrite,
2680 bit_size: 16,
2681 fieldset: None,
2682 },
2683 ),
2684 },
2685 BlockItem {
2686 name: "arr",
2687 description: Some(
2688 "auto-reload register (Dither mode disabled)",
2689 ),
2690 array: None,
2691 byte_offset: 0x2c,
2692 inner: BlockItemInner::Register(
2693 Register {
2694 access: Access::ReadWrite,
2695 bit_size: 32,
2696 fieldset: Some(
2697 "ArrCore",
2698 ),
2699 },
2700 ),
2701 },
2702 BlockItem {
2703 name: "arr_dither",
2704 description: Some(
2705 "auto-reload register (Dither mode enabled)",
2706 ),
2707 array: None,
2708 byte_offset: 0x2c,
2709 inner: BlockItemInner::Register(
2710 Register {
2711 access: Access::ReadWrite,
2712 bit_size: 32,
2713 fieldset: Some(
2714 "ArrDitherCore",
2715 ),
2716 },
2717 ),
2718 },
2719 BlockItem {
2720 name: "ccr",
2721 description: Some(
2722 "capture/compare register x (x=1-4) (Dither mode disabled)",
2723 ),
2724 array: Some(
2725 Array::Regular(
2726 RegularArray {
2727 len: 4,
2728 stride: 4,
2729 },
2730 ),
2731 ),
2732 byte_offset: 0x34,
2733 inner: BlockItemInner::Register(
2734 Register {
2735 access: Access::ReadWrite,
2736 bit_size: 32,
2737 fieldset: Some(
2738 "Ccr1ch",
2739 ),
2740 },
2741 ),
2742 },
2743 BlockItem {
2744 name: "ccr_dither",
2745 description: Some(
2746 "capture/compare register x (x=1-4) (Dither mode enabled)",
2747 ),
2748 array: Some(
2749 Array::Regular(
2750 RegularArray {
2751 len: 4,
2752 stride: 4,
2753 },
2754 ),
2755 ),
2756 byte_offset: 0x34,
2757 inner: BlockItemInner::Register(
2758 Register {
2759 access: Access::ReadWrite,
2760 bit_size: 32,
2761 fieldset: Some(
2762 "CcrDither1ch",
2763 ),
2764 },
2765 ),
2766 },
2767 BlockItem {
2768 name: "ecr",
2769 description: Some(
2770 "encoder control register",
2771 ),
2772 array: None,
2773 byte_offset: 0x58,
2774 inner: BlockItemInner::Register(
2775 Register {
2776 access: Access::ReadWrite,
2777 bit_size: 32,
2778 fieldset: Some(
2779 "EcrGp16",
2780 ),
2781 },
2782 ),
2783 },
2784 BlockItem {
2785 name: "tisel",
2786 description: Some(
2787 "input selection register",
2788 ),
2789 array: None,
2790 byte_offset: 0x5c,
2791 inner: BlockItemInner::Register(
2792 Register {
2793 access: Access::ReadWrite,
2794 bit_size: 32,
2795 fieldset: Some(
2796 "TiselGp16",
2797 ),
2798 },
2799 ),
2800 },
2801 BlockItem {
2802 name: "af1",
2803 description: Some(
2804 "alternate function register 1",
2805 ),
2806 array: None,
2807 byte_offset: 0x60,
2808 inner: BlockItemInner::Register(
2809 Register {
2810 access: Access::ReadWrite,
2811 bit_size: 32,
2812 fieldset: Some(
2813 "Af1Gp16",
2814 ),
2815 },
2816 ),
2817 },
2818 BlockItem {
2819 name: "af2",
2820 description: Some(
2821 "alternate function register 2",
2822 ),
2823 array: None,
2824 byte_offset: 0x64,
2825 inner: BlockItemInner::Register(
2826 Register {
2827 access: Access::ReadWrite,
2828 bit_size: 32,
2829 fieldset: Some(
2830 "Af21chCmp",
2831 ),
2832 },
2833 ),
2834 },
2835 BlockItem {
2836 name: "or",
2837 description: Some(
2838 "Option register 1\nNote: Check Reference Manual to parse this register content",
2839 ),
2840 array: None,
2841 byte_offset: 0x68,
2842 inner: BlockItemInner::Register(
2843 Register {
2844 access: Access::ReadWrite,
2845 bit_size: 32,
2846 fieldset: None,
2847 },
2848 ),
2849 },
2850 BlockItem {
2851 name: "dcr",
2852 description: Some(
2853 "DMA control register",
2854 ),
2855 array: None,
2856 byte_offset: 0x3dc,
2857 inner: BlockItemInner::Register(
2858 Register {
2859 access: Access::ReadWrite,
2860 bit_size: 32,
2861 fieldset: Some(
2862 "Dcr1chCmp",
2863 ),
2864 },
2865 ),
2866 },
2867 BlockItem {
2868 name: "dmar",
2869 description: Some(
2870 "DMA address for full transfer",
2871 ),
2872 array: None,
2873 byte_offset: 0x3e0,
2874 inner: BlockItemInner::Register(
2875 Register {
2876 access: Access::ReadWrite,
2877 bit_size: 32,
2878 fieldset: None,
2879 },
2880 ),
2881 },
2882 ],
2883 },
2884 Block {
2885 name: "TimGp32",
2886 extends: Some(
2887 "TIM_GP16",
2888 ),
2889 description: Some(
2890 "General purpose 32-bit timers",
2891 ),
2892 items: &[
2893 BlockItem {
2894 name: "cr1",
2895 description: Some(
2896 "control register 1",
2897 ),
2898 array: None,
2899 byte_offset: 0x0,
2900 inner: BlockItemInner::Register(
2901 Register {
2902 access: Access::ReadWrite,
2903 bit_size: 16,
2904 fieldset: Some(
2905 "Cr1Gp16",
2906 ),
2907 },
2908 ),
2909 },
2910 BlockItem {
2911 name: "cr2",
2912 description: Some(
2913 "control register 2",
2914 ),
2915 array: None,
2916 byte_offset: 0x4,
2917 inner: BlockItemInner::Register(
2918 Register {
2919 access: Access::ReadWrite,
2920 bit_size: 32,
2921 fieldset: Some(
2922 "Cr2Gp16",
2923 ),
2924 },
2925 ),
2926 },
2927 BlockItem {
2928 name: "smcr",
2929 description: Some(
2930 "slave mode control register",
2931 ),
2932 array: None,
2933 byte_offset: 0x8,
2934 inner: BlockItemInner::Register(
2935 Register {
2936 access: Access::ReadWrite,
2937 bit_size: 32,
2938 fieldset: Some(
2939 "SmcrGp16",
2940 ),
2941 },
2942 ),
2943 },
2944 BlockItem {
2945 name: "dier",
2946 description: Some(
2947 "DMA/Interrupt enable register",
2948 ),
2949 array: None,
2950 byte_offset: 0xc,
2951 inner: BlockItemInner::Register(
2952 Register {
2953 access: Access::ReadWrite,
2954 bit_size: 32,
2955 fieldset: Some(
2956 "DierGp16",
2957 ),
2958 },
2959 ),
2960 },
2961 BlockItem {
2962 name: "sr",
2963 description: Some(
2964 "status register",
2965 ),
2966 array: None,
2967 byte_offset: 0x10,
2968 inner: BlockItemInner::Register(
2969 Register {
2970 access: Access::ReadWrite,
2971 bit_size: 32,
2972 fieldset: Some(
2973 "SrGp16",
2974 ),
2975 },
2976 ),
2977 },
2978 BlockItem {
2979 name: "egr",
2980 description: Some(
2981 "event generation register",
2982 ),
2983 array: None,
2984 byte_offset: 0x14,
2985 inner: BlockItemInner::Register(
2986 Register {
2987 access: Access::Write,
2988 bit_size: 16,
2989 fieldset: Some(
2990 "EgrGp16",
2991 ),
2992 },
2993 ),
2994 },
2995 BlockItem {
2996 name: "ccmr_input",
2997 description: Some(
2998 "capture/compare mode register 1-2 (input mode)",
2999 ),
3000 array: Some(
3001 Array::Regular(
3002 RegularArray {
3003 len: 2,
3004 stride: 4,
3005 },
3006 ),
3007 ),
3008 byte_offset: 0x18,
3009 inner: BlockItemInner::Register(
3010 Register {
3011 access: Access::ReadWrite,
3012 bit_size: 32,
3013 fieldset: Some(
3014 "CcmrInput2ch",
3015 ),
3016 },
3017 ),
3018 },
3019 BlockItem {
3020 name: "ccmr_output",
3021 description: Some(
3022 "capture/compare mode register 1-2 (output mode)",
3023 ),
3024 array: Some(
3025 Array::Regular(
3026 RegularArray {
3027 len: 2,
3028 stride: 4,
3029 },
3030 ),
3031 ),
3032 byte_offset: 0x18,
3033 inner: BlockItemInner::Register(
3034 Register {
3035 access: Access::ReadWrite,
3036 bit_size: 32,
3037 fieldset: Some(
3038 "CcmrOutputGp16",
3039 ),
3040 },
3041 ),
3042 },
3043 BlockItem {
3044 name: "ccer",
3045 description: Some(
3046 "capture/compare enable register",
3047 ),
3048 array: None,
3049 byte_offset: 0x20,
3050 inner: BlockItemInner::Register(
3051 Register {
3052 access: Access::ReadWrite,
3053 bit_size: 32,
3054 fieldset: Some(
3055 "CcerGp16",
3056 ),
3057 },
3058 ),
3059 },
3060 BlockItem {
3061 name: "cnt",
3062 description: Some(
3063 "counter (Dither mode disabled)",
3064 ),
3065 array: None,
3066 byte_offset: 0x24,
3067 inner: BlockItemInner::Register(
3068 Register {
3069 access: Access::ReadWrite,
3070 bit_size: 32,
3071 fieldset: None,
3072 },
3073 ),
3074 },
3075 BlockItem {
3076 name: "cnt_dither",
3077 description: Some(
3078 "counter (Dither mode enbled)",
3079 ),
3080 array: None,
3081 byte_offset: 0x24,
3082 inner: BlockItemInner::Register(
3083 Register {
3084 access: Access::ReadWrite,
3085 bit_size: 32,
3086 fieldset: Some(
3087 "CntDitherGp32",
3088 ),
3089 },
3090 ),
3091 },
3092 BlockItem {
3093 name: "psc",
3094 description: Some(
3095 "prescaler",
3096 ),
3097 array: None,
3098 byte_offset: 0x28,
3099 inner: BlockItemInner::Register(
3100 Register {
3101 access: Access::ReadWrite,
3102 bit_size: 16,
3103 fieldset: None,
3104 },
3105 ),
3106 },
3107 BlockItem {
3108 name: "arr",
3109 description: Some(
3110 "auto-reload register (Dither mode disabled)",
3111 ),
3112 array: None,
3113 byte_offset: 0x2c,
3114 inner: BlockItemInner::Register(
3115 Register {
3116 access: Access::ReadWrite,
3117 bit_size: 32,
3118 fieldset: None,
3119 },
3120 ),
3121 },
3122 BlockItem {
3123 name: "arr_dither",
3124 description: Some(
3125 "auto-reload register (Dither mode enabled)",
3126 ),
3127 array: None,
3128 byte_offset: 0x2c,
3129 inner: BlockItemInner::Register(
3130 Register {
3131 access: Access::ReadWrite,
3132 bit_size: 32,
3133 fieldset: Some(
3134 "ArrDitherGp32",
3135 ),
3136 },
3137 ),
3138 },
3139 BlockItem {
3140 name: "ccr",
3141 description: Some(
3142 "capture/compare register x (x=1-4) (Dither mode disabled)",
3143 ),
3144 array: Some(
3145 Array::Regular(
3146 RegularArray {
3147 len: 4,
3148 stride: 4,
3149 },
3150 ),
3151 ),
3152 byte_offset: 0x34,
3153 inner: BlockItemInner::Register(
3154 Register {
3155 access: Access::ReadWrite,
3156 bit_size: 32,
3157 fieldset: None,
3158 },
3159 ),
3160 },
3161 BlockItem {
3162 name: "ccr_dither",
3163 description: Some(
3164 "capture/compare register x (x=1-4) (Dither mode enabled)",
3165 ),
3166 array: Some(
3167 Array::Regular(
3168 RegularArray {
3169 len: 4,
3170 stride: 4,
3171 },
3172 ),
3173 ),
3174 byte_offset: 0x34,
3175 inner: BlockItemInner::Register(
3176 Register {
3177 access: Access::ReadWrite,
3178 bit_size: 32,
3179 fieldset: Some(
3180 "CcrDitherGp32",
3181 ),
3182 },
3183 ),
3184 },
3185 BlockItem {
3186 name: "ecr",
3187 description: Some(
3188 "encoder control register",
3189 ),
3190 array: None,
3191 byte_offset: 0x58,
3192 inner: BlockItemInner::Register(
3193 Register {
3194 access: Access::ReadWrite,
3195 bit_size: 32,
3196 fieldset: Some(
3197 "EcrGp16",
3198 ),
3199 },
3200 ),
3201 },
3202 BlockItem {
3203 name: "tisel",
3204 description: Some(
3205 "input selection register",
3206 ),
3207 array: None,
3208 byte_offset: 0x5c,
3209 inner: BlockItemInner::Register(
3210 Register {
3211 access: Access::ReadWrite,
3212 bit_size: 32,
3213 fieldset: Some(
3214 "TiselGp16",
3215 ),
3216 },
3217 ),
3218 },
3219 BlockItem {
3220 name: "af1",
3221 description: Some(
3222 "alternate function register 1",
3223 ),
3224 array: None,
3225 byte_offset: 0x60,
3226 inner: BlockItemInner::Register(
3227 Register {
3228 access: Access::ReadWrite,
3229 bit_size: 32,
3230 fieldset: Some(
3231 "Af1Gp16",
3232 ),
3233 },
3234 ),
3235 },
3236 BlockItem {
3237 name: "af2",
3238 description: Some(
3239 "alternate function register 2",
3240 ),
3241 array: None,
3242 byte_offset: 0x64,
3243 inner: BlockItemInner::Register(
3244 Register {
3245 access: Access::ReadWrite,
3246 bit_size: 32,
3247 fieldset: Some(
3248 "Af21chCmp",
3249 ),
3250 },
3251 ),
3252 },
3253 BlockItem {
3254 name: "or",
3255 description: Some(
3256 "Option register 1\nNote: Check Reference Manual to parse this register content",
3257 ),
3258 array: None,
3259 byte_offset: 0x68,
3260 inner: BlockItemInner::Register(
3261 Register {
3262 access: Access::ReadWrite,
3263 bit_size: 32,
3264 fieldset: None,
3265 },
3266 ),
3267 },
3268 BlockItem {
3269 name: "dcr",
3270 description: Some(
3271 "DMA control register",
3272 ),
3273 array: None,
3274 byte_offset: 0x3dc,
3275 inner: BlockItemInner::Register(
3276 Register {
3277 access: Access::ReadWrite,
3278 bit_size: 32,
3279 fieldset: Some(
3280 "Dcr1chCmp",
3281 ),
3282 },
3283 ),
3284 },
3285 BlockItem {
3286 name: "dmar",
3287 description: Some(
3288 "DMA address for full transfer",
3289 ),
3290 array: None,
3291 byte_offset: 0x3e0,
3292 inner: BlockItemInner::Register(
3293 Register {
3294 access: Access::ReadWrite,
3295 bit_size: 32,
3296 fieldset: None,
3297 },
3298 ),
3299 },
3300 ],
3301 },
3302 ],
3303 fieldsets: &[
3304 FieldSet {
3305 name: "Af11chCmp",
3306 extends: None,
3307 description: Some(
3308 "alternate function register 1",
3309 ),
3310 bit_size: 32,
3311 fields: &[
3312 Field {
3313 name: "bkine",
3314 description: Some(
3315 "TIMx_BKIN input enable",
3316 ),
3317 bit_offset: BitOffset::Regular(
3318 RegularBitOffset {
3319 offset: 0,
3320 },
3321 ),
3322 bit_size: 1,
3323 array: None,
3324 enumm: None,
3325 },
3326 Field {
3327 name: "bkcmpe",
3328 description: Some(
3329 "TIM_BRK_CMPx (x=1-8) enable",
3330 ),
3331 bit_offset: BitOffset::Regular(
3332 RegularBitOffset {
3333 offset: 1,
3334 },
3335 ),
3336 bit_size: 1,
3337 array: Some(
3338 Array::Regular(
3339 RegularArray {
3340 len: 8,
3341 stride: 1,
3342 },
3343 ),
3344 ),
3345 enumm: None,
3346 },
3347 Field {
3348 name: "bkinp",
3349 description: Some(
3350 "TIMx_BKIN input polarity",
3351 ),
3352 bit_offset: BitOffset::Regular(
3353 RegularBitOffset {
3354 offset: 9,
3355 },
3356 ),
3357 bit_size: 1,
3358 array: None,
3359 enumm: Some(
3360 "Bkinp",
3361 ),
3362 },
3363 Field {
3364 name: "bkcmpp",
3365 description: Some(
3366 "TIM_BRK_CMPx (x=1-4) input polarity",
3367 ),
3368 bit_offset: BitOffset::Regular(
3369 RegularBitOffset {
3370 offset: 10,
3371 },
3372 ),
3373 bit_size: 1,
3374 array: Some(
3375 Array::Regular(
3376 RegularArray {
3377 len: 4,
3378 stride: 1,
3379 },
3380 ),
3381 ),
3382 enumm: Some(
3383 "Bkinp",
3384 ),
3385 },
3386 ],
3387 },
3388 FieldSet {
3389 name: "Af1Adv",
3390 extends: Some(
3391 "AF1_1CH_CMP",
3392 ),
3393 description: Some(
3394 "alternate function register 1",
3395 ),
3396 bit_size: 32,
3397 fields: &[
3398 Field {
3399 name: "bkine",
3400 description: Some(
3401 "TIMx_BKIN input enable",
3402 ),
3403 bit_offset: BitOffset::Regular(
3404 RegularBitOffset {
3405 offset: 0,
3406 },
3407 ),
3408 bit_size: 1,
3409 array: None,
3410 enumm: None,
3411 },
3412 Field {
3413 name: "bkcmpe",
3414 description: Some(
3415 "TIM_BRK_CMPx (x=1-8) enable",
3416 ),
3417 bit_offset: BitOffset::Regular(
3418 RegularBitOffset {
3419 offset: 1,
3420 },
3421 ),
3422 bit_size: 1,
3423 array: Some(
3424 Array::Regular(
3425 RegularArray {
3426 len: 8,
3427 stride: 1,
3428 },
3429 ),
3430 ),
3431 enumm: None,
3432 },
3433 Field {
3434 name: "bkinp",
3435 description: Some(
3436 "TIMx_BKIN input polarity",
3437 ),
3438 bit_offset: BitOffset::Regular(
3439 RegularBitOffset {
3440 offset: 9,
3441 },
3442 ),
3443 bit_size: 1,
3444 array: None,
3445 enumm: Some(
3446 "Bkinp",
3447 ),
3448 },
3449 Field {
3450 name: "bkcmpp",
3451 description: Some(
3452 "TIM_BRK_CMPx (x=1-4) input polarity",
3453 ),
3454 bit_offset: BitOffset::Regular(
3455 RegularBitOffset {
3456 offset: 10,
3457 },
3458 ),
3459 bit_size: 1,
3460 array: Some(
3461 Array::Regular(
3462 RegularArray {
3463 len: 4,
3464 stride: 1,
3465 },
3466 ),
3467 ),
3468 enumm: Some(
3469 "Bkinp",
3470 ),
3471 },
3472 Field {
3473 name: "etrsel",
3474 description: Some(
3475 "etr_in source selection",
3476 ),
3477 bit_offset: BitOffset::Regular(
3478 RegularBitOffset {
3479 offset: 14,
3480 },
3481 ),
3482 bit_size: 4,
3483 array: None,
3484 enumm: None,
3485 },
3486 ],
3487 },
3488 FieldSet {
3489 name: "Af1Gp16",
3490 extends: None,
3491 description: Some(
3492 "alternate function register 1",
3493 ),
3494 bit_size: 32,
3495 fields: &[
3496 Field {
3497 name: "etrsel",
3498 description: Some(
3499 "etr_in source selection",
3500 ),
3501 bit_offset: BitOffset::Regular(
3502 RegularBitOffset {
3503 offset: 14,
3504 },
3505 ),
3506 bit_size: 4,
3507 array: None,
3508 enumm: None,
3509 },
3510 ],
3511 },
3512 FieldSet {
3513 name: "Af21chCmp",
3514 extends: None,
3515 description: Some(
3516 "alternate function register 2",
3517 ),
3518 bit_size: 32,
3519 fields: &[
3520 Field {
3521 name: "ocrsel",
3522 description: Some(
3523 "ocref_clr source selection",
3524 ),
3525 bit_offset: BitOffset::Regular(
3526 RegularBitOffset {
3527 offset: 16,
3528 },
3529 ),
3530 bit_size: 3,
3531 array: None,
3532 enumm: None,
3533 },
3534 ],
3535 },
3536 FieldSet {
3537 name: "Af2Adv",
3538 extends: Some(
3539 "AF2_1CH_CMP",
3540 ),
3541 description: Some(
3542 "alternate function register 2",
3543 ),
3544 bit_size: 32,
3545 fields: &[
3546 Field {
3547 name: "bk2ine",
3548 description: Some(
3549 "TIMx_BKIN2 input enable",
3550 ),
3551 bit_offset: BitOffset::Regular(
3552 RegularBitOffset {
3553 offset: 0,
3554 },
3555 ),
3556 bit_size: 1,
3557 array: None,
3558 enumm: None,
3559 },
3560 Field {
3561 name: "bk2cmpe",
3562 description: Some(
3563 "TIM_BRK2_CMPx (x=1-8) enable",
3564 ),
3565 bit_offset: BitOffset::Regular(
3566 RegularBitOffset {
3567 offset: 1,
3568 },
3569 ),
3570 bit_size: 1,
3571 array: Some(
3572 Array::Regular(
3573 RegularArray {
3574 len: 8,
3575 stride: 1,
3576 },
3577 ),
3578 ),
3579 enumm: None,
3580 },
3581 Field {
3582 name: "bk2inp",
3583 description: Some(
3584 "TIMx_BK2IN input polarity",
3585 ),
3586 bit_offset: BitOffset::Regular(
3587 RegularBitOffset {
3588 offset: 9,
3589 },
3590 ),
3591 bit_size: 1,
3592 array: None,
3593 enumm: Some(
3594 "Bkinp",
3595 ),
3596 },
3597 Field {
3598 name: "bk2cmpp",
3599 description: Some(
3600 "TIM_BRK2_CMPx (x=1-4) input polarity",
3601 ),
3602 bit_offset: BitOffset::Regular(
3603 RegularBitOffset {
3604 offset: 10,
3605 },
3606 ),
3607 bit_size: 1,
3608 array: Some(
3609 Array::Regular(
3610 RegularArray {
3611 len: 4,
3612 stride: 1,
3613 },
3614 ),
3615 ),
3616 enumm: Some(
3617 "Bkinp",
3618 ),
3619 },
3620 Field {
3621 name: "ocrsel",
3622 description: Some(
3623 "ocref_clr source selection",
3624 ),
3625 bit_offset: BitOffset::Regular(
3626 RegularBitOffset {
3627 offset: 16,
3628 },
3629 ),
3630 bit_size: 3,
3631 array: None,
3632 enumm: None,
3633 },
3634 ],
3635 },
3636 FieldSet {
3637 name: "ArrCore",
3638 extends: None,
3639 description: Some(
3640 "auto-reload register (Dither mode disabled)",
3641 ),
3642 bit_size: 32,
3643 fields: &[
3644 Field {
3645 name: "arr",
3646 description: Some(
3647 "Auto-reload value",
3648 ),
3649 bit_offset: BitOffset::Regular(
3650 RegularBitOffset {
3651 offset: 0,
3652 },
3653 ),
3654 bit_size: 16,
3655 array: None,
3656 enumm: None,
3657 },
3658 ],
3659 },
3660 FieldSet {
3661 name: "ArrDitherCore",
3662 extends: None,
3663 description: Some(
3664 "auto-reload register (Dither mode enabled)",
3665 ),
3666 bit_size: 32,
3667 fields: &[
3668 Field {
3669 name: "dither",
3670 description: Some(
3671 "Dither value",
3672 ),
3673 bit_offset: BitOffset::Regular(
3674 RegularBitOffset {
3675 offset: 0,
3676 },
3677 ),
3678 bit_size: 4,
3679 array: None,
3680 enumm: None,
3681 },
3682 Field {
3683 name: "arr",
3684 description: Some(
3685 "Auto-reload value",
3686 ),
3687 bit_offset: BitOffset::Regular(
3688 RegularBitOffset {
3689 offset: 4,
3690 },
3691 ),
3692 bit_size: 16,
3693 array: None,
3694 enumm: None,
3695 },
3696 ],
3697 },
3698 FieldSet {
3699 name: "ArrDitherGp32",
3700 extends: None,
3701 description: Some(
3702 "auto-reload register (Dither mode enabled)",
3703 ),
3704 bit_size: 32,
3705 fields: &[
3706 Field {
3707 name: "dither",
3708 description: Some(
3709 "Dither value",
3710 ),
3711 bit_offset: BitOffset::Regular(
3712 RegularBitOffset {
3713 offset: 0,
3714 },
3715 ),
3716 bit_size: 4,
3717 array: None,
3718 enumm: None,
3719 },
3720 Field {
3721 name: "arr",
3722 description: Some(
3723 "Auto-reload value",
3724 ),
3725 bit_offset: BitOffset::Regular(
3726 RegularBitOffset {
3727 offset: 4,
3728 },
3729 ),
3730 bit_size: 28,
3731 array: None,
3732 enumm: None,
3733 },
3734 ],
3735 },
3736 FieldSet {
3737 name: "Bdtr1chCmp",
3738 extends: None,
3739 description: Some(
3740 "break and dead-time register",
3741 ),
3742 bit_size: 32,
3743 fields: &[
3744 Field {
3745 name: "dtg",
3746 description: Some(
3747 "Dead-time generator setup",
3748 ),
3749 bit_offset: BitOffset::Regular(
3750 RegularBitOffset {
3751 offset: 0,
3752 },
3753 ),
3754 bit_size: 8,
3755 array: None,
3756 enumm: None,
3757 },
3758 Field {
3759 name: "lock",
3760 description: Some(
3761 "Lock configuration",
3762 ),
3763 bit_offset: BitOffset::Regular(
3764 RegularBitOffset {
3765 offset: 8,
3766 },
3767 ),
3768 bit_size: 2,
3769 array: None,
3770 enumm: Some(
3771 "Lock",
3772 ),
3773 },
3774 Field {
3775 name: "ossi",
3776 description: Some(
3777 "Off-state selection for Idle mode",
3778 ),
3779 bit_offset: BitOffset::Regular(
3780 RegularBitOffset {
3781 offset: 10,
3782 },
3783 ),
3784 bit_size: 1,
3785 array: None,
3786 enumm: Some(
3787 "Ossi",
3788 ),
3789 },
3790 Field {
3791 name: "ossr",
3792 description: Some(
3793 "Off-state selection for Run mode",
3794 ),
3795 bit_offset: BitOffset::Regular(
3796 RegularBitOffset {
3797 offset: 11,
3798 },
3799 ),
3800 bit_size: 1,
3801 array: None,
3802 enumm: Some(
3803 "Ossr",
3804 ),
3805 },
3806 Field {
3807 name: "bke",
3808 description: Some(
3809 "Break x (x=1) enable",
3810 ),
3811 bit_offset: BitOffset::Regular(
3812 RegularBitOffset {
3813 offset: 12,
3814 },
3815 ),
3816 bit_size: 1,
3817 array: Some(
3818 Array::Regular(
3819 RegularArray {
3820 len: 1,
3821 stride: 12,
3822 },
3823 ),
3824 ),
3825 enumm: None,
3826 },
3827 Field {
3828 name: "bkp",
3829 description: Some(
3830 "Break x (x=1) polarity",
3831 ),
3832 bit_offset: BitOffset::Regular(
3833 RegularBitOffset {
3834 offset: 13,
3835 },
3836 ),
3837 bit_size: 1,
3838 array: Some(
3839 Array::Regular(
3840 RegularArray {
3841 len: 1,
3842 stride: 12,
3843 },
3844 ),
3845 ),
3846 enumm: Some(
3847 "Bkp",
3848 ),
3849 },
3850 Field {
3851 name: "aoe",
3852 description: Some(
3853 "Automatic output enable",
3854 ),
3855 bit_offset: BitOffset::Regular(
3856 RegularBitOffset {
3857 offset: 14,
3858 },
3859 ),
3860 bit_size: 1,
3861 array: None,
3862 enumm: None,
3863 },
3864 Field {
3865 name: "moe",
3866 description: Some(
3867 "Main output enable",
3868 ),
3869 bit_offset: BitOffset::Regular(
3870 RegularBitOffset {
3871 offset: 15,
3872 },
3873 ),
3874 bit_size: 1,
3875 array: None,
3876 enumm: None,
3877 },
3878 Field {
3879 name: "bkf",
3880 description: Some(
3881 "Break x (x=1) filter",
3882 ),
3883 bit_offset: BitOffset::Regular(
3884 RegularBitOffset {
3885 offset: 16,
3886 },
3887 ),
3888 bit_size: 4,
3889 array: Some(
3890 Array::Regular(
3891 RegularArray {
3892 len: 1,
3893 stride: 4,
3894 },
3895 ),
3896 ),
3897 enumm: Some(
3898 "FilterValue",
3899 ),
3900 },
3901 Field {
3902 name: "bkdsrm",
3903 description: Some(
3904 "Break x (x=1) Disarm",
3905 ),
3906 bit_offset: BitOffset::Regular(
3907 RegularBitOffset {
3908 offset: 26,
3909 },
3910 ),
3911 bit_size: 1,
3912 array: Some(
3913 Array::Regular(
3914 RegularArray {
3915 len: 1,
3916 stride: 1,
3917 },
3918 ),
3919 ),
3920 enumm: Some(
3921 "Bkdsrm",
3922 ),
3923 },
3924 Field {
3925 name: "bkbid",
3926 description: Some(
3927 "Break x (x=1) bidirectional",
3928 ),
3929 bit_offset: BitOffset::Regular(
3930 RegularBitOffset {
3931 offset: 28,
3932 },
3933 ),
3934 bit_size: 1,
3935 array: Some(
3936 Array::Regular(
3937 RegularArray {
3938 len: 1,
3939 stride: 1,
3940 },
3941 ),
3942 ),
3943 enumm: Some(
3944 "Bkbid",
3945 ),
3946 },
3947 ],
3948 },
3949 FieldSet {
3950 name: "BdtrAdv",
3951 extends: Some(
3952 "BDTR_1CH_CMP",
3953 ),
3954 description: Some(
3955 "break and dead-time register",
3956 ),
3957 bit_size: 32,
3958 fields: &[
3959 Field {
3960 name: "dtg",
3961 description: Some(
3962 "Dead-time generator setup",
3963 ),
3964 bit_offset: BitOffset::Regular(
3965 RegularBitOffset {
3966 offset: 0,
3967 },
3968 ),
3969 bit_size: 8,
3970 array: None,
3971 enumm: None,
3972 },
3973 Field {
3974 name: "lock",
3975 description: Some(
3976 "Lock configuration",
3977 ),
3978 bit_offset: BitOffset::Regular(
3979 RegularBitOffset {
3980 offset: 8,
3981 },
3982 ),
3983 bit_size: 2,
3984 array: None,
3985 enumm: Some(
3986 "Lock",
3987 ),
3988 },
3989 Field {
3990 name: "ossi",
3991 description: Some(
3992 "Off-state selection for Idle mode",
3993 ),
3994 bit_offset: BitOffset::Regular(
3995 RegularBitOffset {
3996 offset: 10,
3997 },
3998 ),
3999 bit_size: 1,
4000 array: None,
4001 enumm: Some(
4002 "Ossi",
4003 ),
4004 },
4005 Field {
4006 name: "ossr",
4007 description: Some(
4008 "Off-state selection for Run mode",
4009 ),
4010 bit_offset: BitOffset::Regular(
4011 RegularBitOffset {
4012 offset: 11,
4013 },
4014 ),
4015 bit_size: 1,
4016 array: None,
4017 enumm: Some(
4018 "Ossr",
4019 ),
4020 },
4021 Field {
4022 name: "bke",
4023 description: Some(
4024 "Break x (x=1,2) enable",
4025 ),
4026 bit_offset: BitOffset::Regular(
4027 RegularBitOffset {
4028 offset: 12,
4029 },
4030 ),
4031 bit_size: 1,
4032 array: Some(
4033 Array::Regular(
4034 RegularArray {
4035 len: 2,
4036 stride: 12,
4037 },
4038 ),
4039 ),
4040 enumm: None,
4041 },
4042 Field {
4043 name: "bkp",
4044 description: Some(
4045 "Break x (x=1,2) polarity",
4046 ),
4047 bit_offset: BitOffset::Regular(
4048 RegularBitOffset {
4049 offset: 13,
4050 },
4051 ),
4052 bit_size: 1,
4053 array: Some(
4054 Array::Regular(
4055 RegularArray {
4056 len: 2,
4057 stride: 12,
4058 },
4059 ),
4060 ),
4061 enumm: Some(
4062 "Bkp",
4063 ),
4064 },
4065 Field {
4066 name: "aoe",
4067 description: Some(
4068 "Automatic output enable",
4069 ),
4070 bit_offset: BitOffset::Regular(
4071 RegularBitOffset {
4072 offset: 14,
4073 },
4074 ),
4075 bit_size: 1,
4076 array: None,
4077 enumm: None,
4078 },
4079 Field {
4080 name: "moe",
4081 description: Some(
4082 "Main output enable",
4083 ),
4084 bit_offset: BitOffset::Regular(
4085 RegularBitOffset {
4086 offset: 15,
4087 },
4088 ),
4089 bit_size: 1,
4090 array: None,
4091 enumm: None,
4092 },
4093 Field {
4094 name: "bkf",
4095 description: Some(
4096 "Break x (x=1,2) filter",
4097 ),
4098 bit_offset: BitOffset::Regular(
4099 RegularBitOffset {
4100 offset: 16,
4101 },
4102 ),
4103 bit_size: 4,
4104 array: Some(
4105 Array::Regular(
4106 RegularArray {
4107 len: 2,
4108 stride: 4,
4109 },
4110 ),
4111 ),
4112 enumm: Some(
4113 "FilterValue",
4114 ),
4115 },
4116 Field {
4117 name: "bkdsrm",
4118 description: Some(
4119 "Break x (x=1,2) Disarm",
4120 ),
4121 bit_offset: BitOffset::Regular(
4122 RegularBitOffset {
4123 offset: 26,
4124 },
4125 ),
4126 bit_size: 1,
4127 array: Some(
4128 Array::Regular(
4129 RegularArray {
4130 len: 2,
4131 stride: 1,
4132 },
4133 ),
4134 ),
4135 enumm: Some(
4136 "Bkdsrm",
4137 ),
4138 },
4139 Field {
4140 name: "bkbid",
4141 description: Some(
4142 "Break x (x=1,2) bidirectional",
4143 ),
4144 bit_offset: BitOffset::Regular(
4145 RegularBitOffset {
4146 offset: 28,
4147 },
4148 ),
4149 bit_size: 1,
4150 array: Some(
4151 Array::Regular(
4152 RegularArray {
4153 len: 2,
4154 stride: 1,
4155 },
4156 ),
4157 ),
4158 enumm: Some(
4159 "Bkbid",
4160 ),
4161 },
4162 ],
4163 },
4164 FieldSet {
4165 name: "Ccer1ch",
4166 extends: None,
4167 description: Some(
4168 "capture/compare enable register",
4169 ),
4170 bit_size: 32,
4171 fields: &[
4172 Field {
4173 name: "cce",
4174 description: Some(
4175 "Capture/Compare x (x=1) output enable",
4176 ),
4177 bit_offset: BitOffset::Regular(
4178 RegularBitOffset {
4179 offset: 0,
4180 },
4181 ),
4182 bit_size: 1,
4183 array: Some(
4184 Array::Regular(
4185 RegularArray {
4186 len: 1,
4187 stride: 4,
4188 },
4189 ),
4190 ),
4191 enumm: None,
4192 },
4193 Field {
4194 name: "ccp",
4195 description: Some(
4196 "Capture/Compare x (x=1) output Polarity",
4197 ),
4198 bit_offset: BitOffset::Regular(
4199 RegularBitOffset {
4200 offset: 1,
4201 },
4202 ),
4203 bit_size: 1,
4204 array: Some(
4205 Array::Regular(
4206 RegularArray {
4207 len: 1,
4208 stride: 4,
4209 },
4210 ),
4211 ),
4212 enumm: None,
4213 },
4214 Field {
4215 name: "ccnp",
4216 description: Some(
4217 "Capture/Compare x (x=1) output Polarity",
4218 ),
4219 bit_offset: BitOffset::Regular(
4220 RegularBitOffset {
4221 offset: 3,
4222 },
4223 ),
4224 bit_size: 1,
4225 array: Some(
4226 Array::Regular(
4227 RegularArray {
4228 len: 1,
4229 stride: 4,
4230 },
4231 ),
4232 ),
4233 enumm: None,
4234 },
4235 ],
4236 },
4237 FieldSet {
4238 name: "Ccer1chCmp",
4239 extends: Some(
4240 "CCER_1CH",
4241 ),
4242 description: Some(
4243 "capture/compare enable register",
4244 ),
4245 bit_size: 32,
4246 fields: &[
4247 Field {
4248 name: "cce",
4249 description: Some(
4250 "Capture/Compare x (x=1) output enable",
4251 ),
4252 bit_offset: BitOffset::Regular(
4253 RegularBitOffset {
4254 offset: 0,
4255 },
4256 ),
4257 bit_size: 1,
4258 array: Some(
4259 Array::Regular(
4260 RegularArray {
4261 len: 1,
4262 stride: 4,
4263 },
4264 ),
4265 ),
4266 enumm: None,
4267 },
4268 Field {
4269 name: "ccp",
4270 description: Some(
4271 "Capture/Compare x (x=1) output Polarity",
4272 ),
4273 bit_offset: BitOffset::Regular(
4274 RegularBitOffset {
4275 offset: 1,
4276 },
4277 ),
4278 bit_size: 1,
4279 array: Some(
4280 Array::Regular(
4281 RegularArray {
4282 len: 1,
4283 stride: 4,
4284 },
4285 ),
4286 ),
4287 enumm: None,
4288 },
4289 Field {
4290 name: "ccne",
4291 description: Some(
4292 "Capture/Compare x (x=1) complementary output enable",
4293 ),
4294 bit_offset: BitOffset::Regular(
4295 RegularBitOffset {
4296 offset: 2,
4297 },
4298 ),
4299 bit_size: 1,
4300 array: Some(
4301 Array::Regular(
4302 RegularArray {
4303 len: 1,
4304 stride: 4,
4305 },
4306 ),
4307 ),
4308 enumm: None,
4309 },
4310 Field {
4311 name: "ccnp",
4312 description: Some(
4313 "Capture/Compare x (x=1) output Polarity",
4314 ),
4315 bit_offset: BitOffset::Regular(
4316 RegularBitOffset {
4317 offset: 3,
4318 },
4319 ),
4320 bit_size: 1,
4321 array: Some(
4322 Array::Regular(
4323 RegularArray {
4324 len: 1,
4325 stride: 4,
4326 },
4327 ),
4328 ),
4329 enumm: None,
4330 },
4331 ],
4332 },
4333 FieldSet {
4334 name: "Ccer2ch",
4335 extends: Some(
4336 "CCER_1CH",
4337 ),
4338 description: Some(
4339 "capture/compare enable register",
4340 ),
4341 bit_size: 32,
4342 fields: &[
4343 Field {
4344 name: "cce",
4345 description: Some(
4346 "Capture/Compare x (x=1-2) output enable",
4347 ),
4348 bit_offset: BitOffset::Regular(
4349 RegularBitOffset {
4350 offset: 0,
4351 },
4352 ),
4353 bit_size: 1,
4354 array: Some(
4355 Array::Regular(
4356 RegularArray {
4357 len: 2,
4358 stride: 4,
4359 },
4360 ),
4361 ),
4362 enumm: None,
4363 },
4364 Field {
4365 name: "ccp",
4366 description: Some(
4367 "Capture/Compare x (x=1-2) output Polarity",
4368 ),
4369 bit_offset: BitOffset::Regular(
4370 RegularBitOffset {
4371 offset: 1,
4372 },
4373 ),
4374 bit_size: 1,
4375 array: Some(
4376 Array::Regular(
4377 RegularArray {
4378 len: 2,
4379 stride: 4,
4380 },
4381 ),
4382 ),
4383 enumm: None,
4384 },
4385 Field {
4386 name: "ccnp",
4387 description: Some(
4388 "Capture/Compare x (x=1-2) output Polarity",
4389 ),
4390 bit_offset: BitOffset::Regular(
4391 RegularBitOffset {
4392 offset: 3,
4393 },
4394 ),
4395 bit_size: 1,
4396 array: Some(
4397 Array::Regular(
4398 RegularArray {
4399 len: 2,
4400 stride: 4,
4401 },
4402 ),
4403 ),
4404 enumm: None,
4405 },
4406 ],
4407 },
4408 FieldSet {
4409 name: "Ccer2chCmp",
4410 extends: Some(
4411 "CCER_2CH",
4412 ),
4413 description: Some(
4414 "capture/compare enable register",
4415 ),
4416 bit_size: 32,
4417 fields: &[
4418 Field {
4419 name: "cce",
4420 description: Some(
4421 "Capture/Compare x (x=1-2) output enable",
4422 ),
4423 bit_offset: BitOffset::Regular(
4424 RegularBitOffset {
4425 offset: 0,
4426 },
4427 ),
4428 bit_size: 1,
4429 array: Some(
4430 Array::Regular(
4431 RegularArray {
4432 len: 2,
4433 stride: 4,
4434 },
4435 ),
4436 ),
4437 enumm: None,
4438 },
4439 Field {
4440 name: "ccp",
4441 description: Some(
4442 "Capture/Compare x (x=1-2) output Polarity",
4443 ),
4444 bit_offset: BitOffset::Regular(
4445 RegularBitOffset {
4446 offset: 1,
4447 },
4448 ),
4449 bit_size: 1,
4450 array: Some(
4451 Array::Regular(
4452 RegularArray {
4453 len: 2,
4454 stride: 4,
4455 },
4456 ),
4457 ),
4458 enumm: None,
4459 },
4460 Field {
4461 name: "ccne",
4462 description: Some(
4463 "Capture/Compare x (x=1) complementary output enable",
4464 ),
4465 bit_offset: BitOffset::Regular(
4466 RegularBitOffset {
4467 offset: 2,
4468 },
4469 ),
4470 bit_size: 1,
4471 array: Some(
4472 Array::Regular(
4473 RegularArray {
4474 len: 1,
4475 stride: 4,
4476 },
4477 ),
4478 ),
4479 enumm: None,
4480 },
4481 Field {
4482 name: "ccnp",
4483 description: Some(
4484 "Capture/Compare x (x=1-2) output Polarity",
4485 ),
4486 bit_offset: BitOffset::Regular(
4487 RegularBitOffset {
4488 offset: 3,
4489 },
4490 ),
4491 bit_size: 1,
4492 array: Some(
4493 Array::Regular(
4494 RegularArray {
4495 len: 2,
4496 stride: 4,
4497 },
4498 ),
4499 ),
4500 enumm: None,
4501 },
4502 ],
4503 },
4504 FieldSet {
4505 name: "CcerAdv",
4506 extends: Some(
4507 "CCER_2CH_CMP",
4508 ),
4509 description: Some(
4510 "capture/compare enable register",
4511 ),
4512 bit_size: 32,
4513 fields: &[
4514 Field {
4515 name: "cce",
4516 description: Some(
4517 "Capture/Compare x (x=1-6) output enable",
4518 ),
4519 bit_offset: BitOffset::Regular(
4520 RegularBitOffset {
4521 offset: 0,
4522 },
4523 ),
4524 bit_size: 1,
4525 array: Some(
4526 Array::Regular(
4527 RegularArray {
4528 len: 6,
4529 stride: 4,
4530 },
4531 ),
4532 ),
4533 enumm: None,
4534 },
4535 Field {
4536 name: "ccp",
4537 description: Some(
4538 "Capture/Compare x (x=1-6) output Polarity",
4539 ),
4540 bit_offset: BitOffset::Regular(
4541 RegularBitOffset {
4542 offset: 1,
4543 },
4544 ),
4545 bit_size: 1,
4546 array: Some(
4547 Array::Regular(
4548 RegularArray {
4549 len: 6,
4550 stride: 4,
4551 },
4552 ),
4553 ),
4554 enumm: None,
4555 },
4556 Field {
4557 name: "ccne",
4558 description: Some(
4559 "Capture/Compare x (x=1-4) complementary output enable",
4560 ),
4561 bit_offset: BitOffset::Regular(
4562 RegularBitOffset {
4563 offset: 2,
4564 },
4565 ),
4566 bit_size: 1,
4567 array: Some(
4568 Array::Regular(
4569 RegularArray {
4570 len: 4,
4571 stride: 4,
4572 },
4573 ),
4574 ),
4575 enumm: None,
4576 },
4577 Field {
4578 name: "ccnp",
4579 description: Some(
4580 "Capture/Compare x (x=1-4) output Polarity",
4581 ),
4582 bit_offset: BitOffset::Regular(
4583 RegularBitOffset {
4584 offset: 3,
4585 },
4586 ),
4587 bit_size: 1,
4588 array: Some(
4589 Array::Regular(
4590 RegularArray {
4591 len: 4,
4592 stride: 4,
4593 },
4594 ),
4595 ),
4596 enumm: None,
4597 },
4598 ],
4599 },
4600 FieldSet {
4601 name: "CcerGp16",
4602 extends: None,
4603 description: Some(
4604 "capture/compare enable register",
4605 ),
4606 bit_size: 32,
4607 fields: &[
4608 Field {
4609 name: "cce",
4610 description: Some(
4611 "Capture/Compare x (x=1-4) output enable",
4612 ),
4613 bit_offset: BitOffset::Regular(
4614 RegularBitOffset {
4615 offset: 0,
4616 },
4617 ),
4618 bit_size: 1,
4619 array: Some(
4620 Array::Regular(
4621 RegularArray {
4622 len: 4,
4623 stride: 4,
4624 },
4625 ),
4626 ),
4627 enumm: None,
4628 },
4629 Field {
4630 name: "ccp",
4631 description: Some(
4632 "Capture/Compare x (x=1-4) output Polarity",
4633 ),
4634 bit_offset: BitOffset::Regular(
4635 RegularBitOffset {
4636 offset: 1,
4637 },
4638 ),
4639 bit_size: 1,
4640 array: Some(
4641 Array::Regular(
4642 RegularArray {
4643 len: 4,
4644 stride: 4,
4645 },
4646 ),
4647 ),
4648 enumm: None,
4649 },
4650 Field {
4651 name: "ccnp",
4652 description: Some(
4653 "Capture/Compare x (x=1-4) output Polarity",
4654 ),
4655 bit_offset: BitOffset::Regular(
4656 RegularBitOffset {
4657 offset: 3,
4658 },
4659 ),
4660 bit_size: 1,
4661 array: Some(
4662 Array::Regular(
4663 RegularArray {
4664 len: 4,
4665 stride: 4,
4666 },
4667 ),
4668 ),
4669 enumm: None,
4670 },
4671 ],
4672 },
4673 FieldSet {
4674 name: "Ccmr3Adv",
4675 extends: None,
4676 description: Some(
4677 "capture/compare mode register 3",
4678 ),
4679 bit_size: 32,
4680 fields: &[
4681 Field {
4682 name: "ocfe",
4683 description: Some(
4684 "Output compare x (x=5,6) fast enable",
4685 ),
4686 bit_offset: BitOffset::Regular(
4687 RegularBitOffset {
4688 offset: 2,
4689 },
4690 ),
4691 bit_size: 1,
4692 array: Some(
4693 Array::Regular(
4694 RegularArray {
4695 len: 2,
4696 stride: 8,
4697 },
4698 ),
4699 ),
4700 enumm: None,
4701 },
4702 Field {
4703 name: "ocpe",
4704 description: Some(
4705 "Output compare x (x=5,6) preload enable",
4706 ),
4707 bit_offset: BitOffset::Regular(
4708 RegularBitOffset {
4709 offset: 3,
4710 },
4711 ),
4712 bit_size: 1,
4713 array: Some(
4714 Array::Regular(
4715 RegularArray {
4716 len: 2,
4717 stride: 8,
4718 },
4719 ),
4720 ),
4721 enumm: None,
4722 },
4723 Field {
4724 name: "ocm",
4725 description: Some(
4726 "Output compare x (x=5,6) mode",
4727 ),
4728 bit_offset: BitOffset::Cursed(
4729 CursedBitOffset {
4730 ranges: &[
4731 4..=6,
4732 16..=16,
4733 ],
4734 },
4735 ),
4736 bit_size: 4,
4737 array: Some(
4738 Array::Regular(
4739 RegularArray {
4740 len: 2,
4741 stride: 8,
4742 },
4743 ),
4744 ),
4745 enumm: Some(
4746 "Ocm",
4747 ),
4748 },
4749 Field {
4750 name: "occe",
4751 description: Some(
4752 "Output compare x (x=5,6) clear enable",
4753 ),
4754 bit_offset: BitOffset::Regular(
4755 RegularBitOffset {
4756 offset: 7,
4757 },
4758 ),
4759 bit_size: 1,
4760 array: Some(
4761 Array::Regular(
4762 RegularArray {
4763 len: 2,
4764 stride: 8,
4765 },
4766 ),
4767 ),
4768 enumm: None,
4769 },
4770 ],
4771 },
4772 FieldSet {
4773 name: "CcmrInput1ch",
4774 extends: None,
4775 description: Some(
4776 "capture/compare mode register x (x=1) (input mode)",
4777 ),
4778 bit_size: 32,
4779 fields: &[
4780 Field {
4781 name: "ccs",
4782 description: Some(
4783 "Capture/Compare y selection",
4784 ),
4785 bit_offset: BitOffset::Regular(
4786 RegularBitOffset {
4787 offset: 0,
4788 },
4789 ),
4790 bit_size: 2,
4791 array: Some(
4792 Array::Regular(
4793 RegularArray {
4794 len: 1,
4795 stride: 8,
4796 },
4797 ),
4798 ),
4799 enumm: Some(
4800 "CcmrInputCcs",
4801 ),
4802 },
4803 Field {
4804 name: "icpsc",
4805 description: Some(
4806 "Input capture y prescaler",
4807 ),
4808 bit_offset: BitOffset::Regular(
4809 RegularBitOffset {
4810 offset: 2,
4811 },
4812 ),
4813 bit_size: 2,
4814 array: Some(
4815 Array::Regular(
4816 RegularArray {
4817 len: 1,
4818 stride: 8,
4819 },
4820 ),
4821 ),
4822 enumm: None,
4823 },
4824 Field {
4825 name: "icf",
4826 description: Some(
4827 "Input capture y filter",
4828 ),
4829 bit_offset: BitOffset::Regular(
4830 RegularBitOffset {
4831 offset: 4,
4832 },
4833 ),
4834 bit_size: 4,
4835 array: Some(
4836 Array::Regular(
4837 RegularArray {
4838 len: 1,
4839 stride: 8,
4840 },
4841 ),
4842 ),
4843 enumm: Some(
4844 "FilterValue",
4845 ),
4846 },
4847 ],
4848 },
4849 FieldSet {
4850 name: "CcmrInput2ch",
4851 extends: Some(
4852 "CCMR_Input_1CH",
4853 ),
4854 description: Some(
4855 "capture/compare mode register x (x=1) (input mode)",
4856 ),
4857 bit_size: 32,
4858 fields: &[
4859 Field {
4860 name: "ccs",
4861 description: Some(
4862 "Capture/Compare y selection",
4863 ),
4864 bit_offset: BitOffset::Regular(
4865 RegularBitOffset {
4866 offset: 0,
4867 },
4868 ),
4869 bit_size: 2,
4870 array: Some(
4871 Array::Regular(
4872 RegularArray {
4873 len: 2,
4874 stride: 8,
4875 },
4876 ),
4877 ),
4878 enumm: Some(
4879 "CcmrInputCcs",
4880 ),
4881 },
4882 Field {
4883 name: "icpsc",
4884 description: Some(
4885 "Input capture y prescaler",
4886 ),
4887 bit_offset: BitOffset::Regular(
4888 RegularBitOffset {
4889 offset: 2,
4890 },
4891 ),
4892 bit_size: 2,
4893 array: Some(
4894 Array::Regular(
4895 RegularArray {
4896 len: 2,
4897 stride: 8,
4898 },
4899 ),
4900 ),
4901 enumm: None,
4902 },
4903 Field {
4904 name: "icf",
4905 description: Some(
4906 "Input capture y filter",
4907 ),
4908 bit_offset: BitOffset::Regular(
4909 RegularBitOffset {
4910 offset: 4,
4911 },
4912 ),
4913 bit_size: 4,
4914 array: Some(
4915 Array::Regular(
4916 RegularArray {
4917 len: 2,
4918 stride: 8,
4919 },
4920 ),
4921 ),
4922 enumm: Some(
4923 "FilterValue",
4924 ),
4925 },
4926 ],
4927 },
4928 FieldSet {
4929 name: "CcmrOutput1ch",
4930 extends: None,
4931 description: Some(
4932 "capture/compare mode register x (x=1) (output mode)",
4933 ),
4934 bit_size: 32,
4935 fields: &[
4936 Field {
4937 name: "ccs",
4938 description: Some(
4939 "Capture/Compare y selection",
4940 ),
4941 bit_offset: BitOffset::Regular(
4942 RegularBitOffset {
4943 offset: 0,
4944 },
4945 ),
4946 bit_size: 2,
4947 array: Some(
4948 Array::Regular(
4949 RegularArray {
4950 len: 1,
4951 stride: 8,
4952 },
4953 ),
4954 ),
4955 enumm: Some(
4956 "CcmrOutputCcs",
4957 ),
4958 },
4959 Field {
4960 name: "ocfe",
4961 description: Some(
4962 "Output compare y fast enable",
4963 ),
4964 bit_offset: BitOffset::Regular(
4965 RegularBitOffset {
4966 offset: 2,
4967 },
4968 ),
4969 bit_size: 1,
4970 array: Some(
4971 Array::Regular(
4972 RegularArray {
4973 len: 1,
4974 stride: 8,
4975 },
4976 ),
4977 ),
4978 enumm: None,
4979 },
4980 Field {
4981 name: "ocpe",
4982 description: Some(
4983 "Output compare y preload enable",
4984 ),
4985 bit_offset: BitOffset::Regular(
4986 RegularBitOffset {
4987 offset: 3,
4988 },
4989 ),
4990 bit_size: 1,
4991 array: Some(
4992 Array::Regular(
4993 RegularArray {
4994 len: 1,
4995 stride: 8,
4996 },
4997 ),
4998 ),
4999 enumm: None,
5000 },
5001 Field {
5002 name: "ocm",
5003 description: Some(
5004 "Output compare y mode",
5005 ),
5006 bit_offset: BitOffset::Cursed(
5007 CursedBitOffset {
5008 ranges: &[
5009 4..=6,
5010 16..=16,
5011 ],
5012 },
5013 ),
5014 bit_size: 4,
5015 array: Some(
5016 Array::Regular(
5017 RegularArray {
5018 len: 1,
5019 stride: 8,
5020 },
5021 ),
5022 ),
5023 enumm: Some(
5024 "Ocm",
5025 ),
5026 },
5027 ],
5028 },
5029 FieldSet {
5030 name: "CcmrOutput2ch",
5031 extends: Some(
5032 "CCMR_Output_1CH",
5033 ),
5034 description: Some(
5035 "capture/compare mode register x (x=1) (output mode)",
5036 ),
5037 bit_size: 32,
5038 fields: &[
5039 Field {
5040 name: "ccs",
5041 description: Some(
5042 "Capture/Compare y selection",
5043 ),
5044 bit_offset: BitOffset::Regular(
5045 RegularBitOffset {
5046 offset: 0,
5047 },
5048 ),
5049 bit_size: 2,
5050 array: Some(
5051 Array::Regular(
5052 RegularArray {
5053 len: 2,
5054 stride: 8,
5055 },
5056 ),
5057 ),
5058 enumm: Some(
5059 "CcmrOutputCcs",
5060 ),
5061 },
5062 Field {
5063 name: "ocfe",
5064 description: Some(
5065 "Output compare y fast enable",
5066 ),
5067 bit_offset: BitOffset::Regular(
5068 RegularBitOffset {
5069 offset: 2,
5070 },
5071 ),
5072 bit_size: 1,
5073 array: Some(
5074 Array::Regular(
5075 RegularArray {
5076 len: 2,
5077 stride: 8,
5078 },
5079 ),
5080 ),
5081 enumm: None,
5082 },
5083 Field {
5084 name: "ocpe",
5085 description: Some(
5086 "Output compare y preload enable",
5087 ),
5088 bit_offset: BitOffset::Regular(
5089 RegularBitOffset {
5090 offset: 3,
5091 },
5092 ),
5093 bit_size: 1,
5094 array: Some(
5095 Array::Regular(
5096 RegularArray {
5097 len: 2,
5098 stride: 8,
5099 },
5100 ),
5101 ),
5102 enumm: None,
5103 },
5104 Field {
5105 name: "ocm",
5106 description: Some(
5107 "Output compare y mode",
5108 ),
5109 bit_offset: BitOffset::Cursed(
5110 CursedBitOffset {
5111 ranges: &[
5112 4..=6,
5113 16..=16,
5114 ],
5115 },
5116 ),
5117 bit_size: 4,
5118 array: Some(
5119 Array::Regular(
5120 RegularArray {
5121 len: 2,
5122 stride: 8,
5123 },
5124 ),
5125 ),
5126 enumm: Some(
5127 "Ocm",
5128 ),
5129 },
5130 ],
5131 },
5132 FieldSet {
5133 name: "CcmrOutputGp16",
5134 extends: Some(
5135 "CCMR_Output_2CH",
5136 ),
5137 description: Some(
5138 "capture/compare mode register x (x=1-2) (output mode)",
5139 ),
5140 bit_size: 32,
5141 fields: &[
5142 Field {
5143 name: "ccs",
5144 description: Some(
5145 "Capture/Compare y selection",
5146 ),
5147 bit_offset: BitOffset::Regular(
5148 RegularBitOffset {
5149 offset: 0,
5150 },
5151 ),
5152 bit_size: 2,
5153 array: Some(
5154 Array::Regular(
5155 RegularArray {
5156 len: 2,
5157 stride: 8,
5158 },
5159 ),
5160 ),
5161 enumm: Some(
5162 "CcmrOutputCcs",
5163 ),
5164 },
5165 Field {
5166 name: "ocfe",
5167 description: Some(
5168 "Output compare y fast enable",
5169 ),
5170 bit_offset: BitOffset::Regular(
5171 RegularBitOffset {
5172 offset: 2,
5173 },
5174 ),
5175 bit_size: 1,
5176 array: Some(
5177 Array::Regular(
5178 RegularArray {
5179 len: 2,
5180 stride: 8,
5181 },
5182 ),
5183 ),
5184 enumm: None,
5185 },
5186 Field {
5187 name: "ocpe",
5188 description: Some(
5189 "Output compare y preload enable",
5190 ),
5191 bit_offset: BitOffset::Regular(
5192 RegularBitOffset {
5193 offset: 3,
5194 },
5195 ),
5196 bit_size: 1,
5197 array: Some(
5198 Array::Regular(
5199 RegularArray {
5200 len: 2,
5201 stride: 8,
5202 },
5203 ),
5204 ),
5205 enumm: None,
5206 },
5207 Field {
5208 name: "ocm",
5209 description: Some(
5210 "Output compare y mode",
5211 ),
5212 bit_offset: BitOffset::Cursed(
5213 CursedBitOffset {
5214 ranges: &[
5215 4..=6,
5216 16..=16,
5217 ],
5218 },
5219 ),
5220 bit_size: 4,
5221 array: Some(
5222 Array::Regular(
5223 RegularArray {
5224 len: 2,
5225 stride: 8,
5226 },
5227 ),
5228 ),
5229 enumm: Some(
5230 "Ocm",
5231 ),
5232 },
5233 Field {
5234 name: "occe",
5235 description: Some(
5236 "Output compare y clear enable",
5237 ),
5238 bit_offset: BitOffset::Regular(
5239 RegularBitOffset {
5240 offset: 7,
5241 },
5242 ),
5243 bit_size: 1,
5244 array: Some(
5245 Array::Regular(
5246 RegularArray {
5247 len: 2,
5248 stride: 8,
5249 },
5250 ),
5251 ),
5252 enumm: None,
5253 },
5254 ],
5255 },
5256 FieldSet {
5257 name: "Ccr1ch",
5258 extends: None,
5259 description: Some(
5260 "capture/compare register x (x=1-4,6) (Dither mode disabled)",
5261 ),
5262 bit_size: 32,
5263 fields: &[
5264 Field {
5265 name: "ccr",
5266 description: Some(
5267 "capture/compare x (x=1-4,6) value",
5268 ),
5269 bit_offset: BitOffset::Regular(
5270 RegularBitOffset {
5271 offset: 0,
5272 },
5273 ),
5274 bit_size: 16,
5275 array: None,
5276 enumm: None,
5277 },
5278 ],
5279 },
5280 FieldSet {
5281 name: "Ccr5Adv",
5282 extends: Some(
5283 "CCR_1CH",
5284 ),
5285 description: Some(
5286 "capture/compare register 5 (Dither mode disabled)",
5287 ),
5288 bit_size: 32,
5289 fields: &[
5290 Field {
5291 name: "ccr",
5292 description: Some(
5293 "capture/compare x (x=1-4,6) value",
5294 ),
5295 bit_offset: BitOffset::Regular(
5296 RegularBitOffset {
5297 offset: 0,
5298 },
5299 ),
5300 bit_size: 16,
5301 array: None,
5302 enumm: None,
5303 },
5304 Field {
5305 name: "gc5c",
5306 description: Some(
5307 "Group channel 5 and channel x (x=1-3)",
5308 ),
5309 bit_offset: BitOffset::Regular(
5310 RegularBitOffset {
5311 offset: 29,
5312 },
5313 ),
5314 bit_size: 1,
5315 array: Some(
5316 Array::Regular(
5317 RegularArray {
5318 len: 3,
5319 stride: 1,
5320 },
5321 ),
5322 ),
5323 enumm: Some(
5324 "Gc5c",
5325 ),
5326 },
5327 ],
5328 },
5329 FieldSet {
5330 name: "Ccr5DitherAdv",
5331 extends: Some(
5332 "CCR_DITHER_1CH",
5333 ),
5334 description: Some(
5335 "capture/compare register 5 (Dither mode enabled)",
5336 ),
5337 bit_size: 32,
5338 fields: &[
5339 Field {
5340 name: "dither",
5341 description: Some(
5342 "capture/compare x (x=1-4,6) value",
5343 ),
5344 bit_offset: BitOffset::Regular(
5345 RegularBitOffset {
5346 offset: 0,
5347 },
5348 ),
5349 bit_size: 4,
5350 array: None,
5351 enumm: None,
5352 },
5353 Field {
5354 name: "ccr",
5355 description: Some(
5356 "capture/compare x (x=1-4,6) value",
5357 ),
5358 bit_offset: BitOffset::Regular(
5359 RegularBitOffset {
5360 offset: 4,
5361 },
5362 ),
5363 bit_size: 16,
5364 array: None,
5365 enumm: None,
5366 },
5367 Field {
5368 name: "gc5c",
5369 description: Some(
5370 "Group channel 5 and channel x (x=1-3)",
5371 ),
5372 bit_offset: BitOffset::Regular(
5373 RegularBitOffset {
5374 offset: 29,
5375 },
5376 ),
5377 bit_size: 1,
5378 array: Some(
5379 Array::Regular(
5380 RegularArray {
5381 len: 3,
5382 stride: 1,
5383 },
5384 ),
5385 ),
5386 enumm: Some(
5387 "Gc5c",
5388 ),
5389 },
5390 ],
5391 },
5392 FieldSet {
5393 name: "CcrDither1ch",
5394 extends: None,
5395 description: Some(
5396 "capture/compare register x (x=1-4,6) (Dither mode enabled)",
5397 ),
5398 bit_size: 32,
5399 fields: &[
5400 Field {
5401 name: "dither",
5402 description: Some(
5403 "capture/compare x (x=1-4,6) value",
5404 ),
5405 bit_offset: BitOffset::Regular(
5406 RegularBitOffset {
5407 offset: 0,
5408 },
5409 ),
5410 bit_size: 4,
5411 array: None,
5412 enumm: None,
5413 },
5414 Field {
5415 name: "ccr",
5416 description: Some(
5417 "capture/compare x (x=1-4,6) value",
5418 ),
5419 bit_offset: BitOffset::Regular(
5420 RegularBitOffset {
5421 offset: 4,
5422 },
5423 ),
5424 bit_size: 16,
5425 array: None,
5426 enumm: None,
5427 },
5428 ],
5429 },
5430 FieldSet {
5431 name: "CcrDitherGp32",
5432 extends: None,
5433 description: Some(
5434 "capture/compare register x (x=1-4,6) (Dither mode enabled)",
5435 ),
5436 bit_size: 32,
5437 fields: &[
5438 Field {
5439 name: "dither",
5440 description: Some(
5441 "Dither value",
5442 ),
5443 bit_offset: BitOffset::Regular(
5444 RegularBitOffset {
5445 offset: 0,
5446 },
5447 ),
5448 bit_size: 4,
5449 array: None,
5450 enumm: None,
5451 },
5452 Field {
5453 name: "ccr",
5454 description: Some(
5455 "capture/compare x (x=1-4,6) value",
5456 ),
5457 bit_offset: BitOffset::Regular(
5458 RegularBitOffset {
5459 offset: 4,
5460 },
5461 ),
5462 bit_size: 28,
5463 array: None,
5464 enumm: None,
5465 },
5466 ],
5467 },
5468 FieldSet {
5469 name: "CntCore",
5470 extends: None,
5471 description: Some(
5472 "counter",
5473 ),
5474 bit_size: 32,
5475 fields: &[
5476 Field {
5477 name: "cnt",
5478 description: Some(
5479 "counter value",
5480 ),
5481 bit_offset: BitOffset::Regular(
5482 RegularBitOffset {
5483 offset: 0,
5484 },
5485 ),
5486 bit_size: 16,
5487 array: None,
5488 enumm: None,
5489 },
5490 Field {
5491 name: "uifcpy",
5492 description: Some(
5493 "UIF copy",
5494 ),
5495 bit_offset: BitOffset::Regular(
5496 RegularBitOffset {
5497 offset: 31,
5498 },
5499 ),
5500 bit_size: 1,
5501 array: None,
5502 enumm: None,
5503 },
5504 ],
5505 },
5506 FieldSet {
5507 name: "CntDitherGp32",
5508 extends: None,
5509 description: Some(
5510 "counter (Dither mode enabled)",
5511 ),
5512 bit_size: 32,
5513 fields: &[
5514 Field {
5515 name: "cnt",
5516 description: Some(
5517 "counter value",
5518 ),
5519 bit_offset: BitOffset::Regular(
5520 RegularBitOffset {
5521 offset: 0,
5522 },
5523 ),
5524 bit_size: 31,
5525 array: None,
5526 enumm: None,
5527 },
5528 Field {
5529 name: "uifcpy",
5530 description: Some(
5531 "UIF copy",
5532 ),
5533 bit_offset: BitOffset::Regular(
5534 RegularBitOffset {
5535 offset: 31,
5536 },
5537 ),
5538 bit_size: 1,
5539 array: None,
5540 enumm: None,
5541 },
5542 ],
5543 },
5544 FieldSet {
5545 name: "Cr11ch",
5546 extends: Some(
5547 "CR1_CORE",
5548 ),
5549 description: Some(
5550 "control register 1",
5551 ),
5552 bit_size: 32,
5553 fields: &[
5554 Field {
5555 name: "cen",
5556 description: Some(
5557 "Counter enable",
5558 ),
5559 bit_offset: BitOffset::Regular(
5560 RegularBitOffset {
5561 offset: 0,
5562 },
5563 ),
5564 bit_size: 1,
5565 array: None,
5566 enumm: None,
5567 },
5568 Field {
5569 name: "udis",
5570 description: Some(
5571 "Update disable",
5572 ),
5573 bit_offset: BitOffset::Regular(
5574 RegularBitOffset {
5575 offset: 1,
5576 },
5577 ),
5578 bit_size: 1,
5579 array: None,
5580 enumm: None,
5581 },
5582 Field {
5583 name: "urs",
5584 description: Some(
5585 "Update request source",
5586 ),
5587 bit_offset: BitOffset::Regular(
5588 RegularBitOffset {
5589 offset: 2,
5590 },
5591 ),
5592 bit_size: 1,
5593 array: None,
5594 enumm: Some(
5595 "Urs",
5596 ),
5597 },
5598 Field {
5599 name: "opm",
5600 description: Some(
5601 "One-pulse mode enbaled",
5602 ),
5603 bit_offset: BitOffset::Regular(
5604 RegularBitOffset {
5605 offset: 3,
5606 },
5607 ),
5608 bit_size: 1,
5609 array: None,
5610 enumm: None,
5611 },
5612 Field {
5613 name: "arpe",
5614 description: Some(
5615 "Auto-reload preload enable",
5616 ),
5617 bit_offset: BitOffset::Regular(
5618 RegularBitOffset {
5619 offset: 7,
5620 },
5621 ),
5622 bit_size: 1,
5623 array: None,
5624 enumm: None,
5625 },
5626 Field {
5627 name: "ckd",
5628 description: Some(
5629 "Clock division",
5630 ),
5631 bit_offset: BitOffset::Regular(
5632 RegularBitOffset {
5633 offset: 8,
5634 },
5635 ),
5636 bit_size: 2,
5637 array: None,
5638 enumm: Some(
5639 "Ckd",
5640 ),
5641 },
5642 Field {
5643 name: "uifremap",
5644 description: Some(
5645 "UIF status bit remapping enable",
5646 ),
5647 bit_offset: BitOffset::Regular(
5648 RegularBitOffset {
5649 offset: 11,
5650 },
5651 ),
5652 bit_size: 1,
5653 array: None,
5654 enumm: None,
5655 },
5656 Field {
5657 name: "dithen",
5658 description: Some(
5659 "Dithering enable",
5660 ),
5661 bit_offset: BitOffset::Regular(
5662 RegularBitOffset {
5663 offset: 12,
5664 },
5665 ),
5666 bit_size: 1,
5667 array: None,
5668 enumm: None,
5669 },
5670 ],
5671 },
5672 FieldSet {
5673 name: "Cr1Core",
5674 extends: None,
5675 description: Some(
5676 "control register 1",
5677 ),
5678 bit_size: 32,
5679 fields: &[
5680 Field {
5681 name: "cen",
5682 description: Some(
5683 "Counter enable",
5684 ),
5685 bit_offset: BitOffset::Regular(
5686 RegularBitOffset {
5687 offset: 0,
5688 },
5689 ),
5690 bit_size: 1,
5691 array: None,
5692 enumm: None,
5693 },
5694 Field {
5695 name: "udis",
5696 description: Some(
5697 "Update disable",
5698 ),
5699 bit_offset: BitOffset::Regular(
5700 RegularBitOffset {
5701 offset: 1,
5702 },
5703 ),
5704 bit_size: 1,
5705 array: None,
5706 enumm: None,
5707 },
5708 Field {
5709 name: "urs",
5710 description: Some(
5711 "Update request source",
5712 ),
5713 bit_offset: BitOffset::Regular(
5714 RegularBitOffset {
5715 offset: 2,
5716 },
5717 ),
5718 bit_size: 1,
5719 array: None,
5720 enumm: Some(
5721 "Urs",
5722 ),
5723 },
5724 Field {
5725 name: "opm",
5726 description: Some(
5727 "One-pulse mode enbaled",
5728 ),
5729 bit_offset: BitOffset::Regular(
5730 RegularBitOffset {
5731 offset: 3,
5732 },
5733 ),
5734 bit_size: 1,
5735 array: None,
5736 enumm: None,
5737 },
5738 Field {
5739 name: "arpe",
5740 description: Some(
5741 "Auto-reload preload enable",
5742 ),
5743 bit_offset: BitOffset::Regular(
5744 RegularBitOffset {
5745 offset: 7,
5746 },
5747 ),
5748 bit_size: 1,
5749 array: None,
5750 enumm: None,
5751 },
5752 Field {
5753 name: "uifremap",
5754 description: Some(
5755 "UIF status bit remapping enable",
5756 ),
5757 bit_offset: BitOffset::Regular(
5758 RegularBitOffset {
5759 offset: 11,
5760 },
5761 ),
5762 bit_size: 1,
5763 array: None,
5764 enumm: None,
5765 },
5766 Field {
5767 name: "dithen",
5768 description: Some(
5769 "Dithering enable",
5770 ),
5771 bit_offset: BitOffset::Regular(
5772 RegularBitOffset {
5773 offset: 12,
5774 },
5775 ),
5776 bit_size: 1,
5777 array: None,
5778 enumm: None,
5779 },
5780 ],
5781 },
5782 FieldSet {
5783 name: "Cr1Gp16",
5784 extends: Some(
5785 "CR1_CORE",
5786 ),
5787 description: Some(
5788 "control register 1",
5789 ),
5790 bit_size: 32,
5791 fields: &[
5792 Field {
5793 name: "cen",
5794 description: Some(
5795 "Counter enable",
5796 ),
5797 bit_offset: BitOffset::Regular(
5798 RegularBitOffset {
5799 offset: 0,
5800 },
5801 ),
5802 bit_size: 1,
5803 array: None,
5804 enumm: None,
5805 },
5806 Field {
5807 name: "udis",
5808 description: Some(
5809 "Update disable",
5810 ),
5811 bit_offset: BitOffset::Regular(
5812 RegularBitOffset {
5813 offset: 1,
5814 },
5815 ),
5816 bit_size: 1,
5817 array: None,
5818 enumm: None,
5819 },
5820 Field {
5821 name: "urs",
5822 description: Some(
5823 "Update request source",
5824 ),
5825 bit_offset: BitOffset::Regular(
5826 RegularBitOffset {
5827 offset: 2,
5828 },
5829 ),
5830 bit_size: 1,
5831 array: None,
5832 enumm: Some(
5833 "Urs",
5834 ),
5835 },
5836 Field {
5837 name: "opm",
5838 description: Some(
5839 "One-pulse mode enbaled",
5840 ),
5841 bit_offset: BitOffset::Regular(
5842 RegularBitOffset {
5843 offset: 3,
5844 },
5845 ),
5846 bit_size: 1,
5847 array: None,
5848 enumm: None,
5849 },
5850 Field {
5851 name: "dir",
5852 description: Some(
5853 "Direction",
5854 ),
5855 bit_offset: BitOffset::Regular(
5856 RegularBitOffset {
5857 offset: 4,
5858 },
5859 ),
5860 bit_size: 1,
5861 array: None,
5862 enumm: Some(
5863 "Dir",
5864 ),
5865 },
5866 Field {
5867 name: "cms",
5868 description: Some(
5869 "Center-aligned mode selection",
5870 ),
5871 bit_offset: BitOffset::Regular(
5872 RegularBitOffset {
5873 offset: 5,
5874 },
5875 ),
5876 bit_size: 2,
5877 array: None,
5878 enumm: Some(
5879 "Cms",
5880 ),
5881 },
5882 Field {
5883 name: "arpe",
5884 description: Some(
5885 "Auto-reload preload enable",
5886 ),
5887 bit_offset: BitOffset::Regular(
5888 RegularBitOffset {
5889 offset: 7,
5890 },
5891 ),
5892 bit_size: 1,
5893 array: None,
5894 enumm: None,
5895 },
5896 Field {
5897 name: "ckd",
5898 description: Some(
5899 "Clock division",
5900 ),
5901 bit_offset: BitOffset::Regular(
5902 RegularBitOffset {
5903 offset: 8,
5904 },
5905 ),
5906 bit_size: 2,
5907 array: None,
5908 enumm: Some(
5909 "Ckd",
5910 ),
5911 },
5912 Field {
5913 name: "uifremap",
5914 description: Some(
5915 "UIF status bit remapping enable",
5916 ),
5917 bit_offset: BitOffset::Regular(
5918 RegularBitOffset {
5919 offset: 11,
5920 },
5921 ),
5922 bit_size: 1,
5923 array: None,
5924 enumm: None,
5925 },
5926 Field {
5927 name: "dithen",
5928 description: Some(
5929 "Dithering enable",
5930 ),
5931 bit_offset: BitOffset::Regular(
5932 RegularBitOffset {
5933 offset: 12,
5934 },
5935 ),
5936 bit_size: 1,
5937 array: None,
5938 enumm: None,
5939 },
5940 ],
5941 },
5942 FieldSet {
5943 name: "Cr21chCmp",
5944 extends: None,
5945 description: Some(
5946 "control register 2",
5947 ),
5948 bit_size: 32,
5949 fields: &[
5950 Field {
5951 name: "ccpc",
5952 description: Some(
5953 "Capture/compare preloaded control",
5954 ),
5955 bit_offset: BitOffset::Regular(
5956 RegularBitOffset {
5957 offset: 0,
5958 },
5959 ),
5960 bit_size: 1,
5961 array: None,
5962 enumm: None,
5963 },
5964 Field {
5965 name: "ccus",
5966 description: Some(
5967 "Capture/compare control update selection",
5968 ),
5969 bit_offset: BitOffset::Regular(
5970 RegularBitOffset {
5971 offset: 2,
5972 },
5973 ),
5974 bit_size: 1,
5975 array: None,
5976 enumm: None,
5977 },
5978 Field {
5979 name: "ccds",
5980 description: Some(
5981 "Capture/compare DMA selection",
5982 ),
5983 bit_offset: BitOffset::Regular(
5984 RegularBitOffset {
5985 offset: 3,
5986 },
5987 ),
5988 bit_size: 1,
5989 array: None,
5990 enumm: Some(
5991 "Ccds",
5992 ),
5993 },
5994 Field {
5995 name: "ois",
5996 description: Some(
5997 "Output Idle state x (x=1)",
5998 ),
5999 bit_offset: BitOffset::Regular(
6000 RegularBitOffset {
6001 offset: 8,
6002 },
6003 ),
6004 bit_size: 1,
6005 array: Some(
6006 Array::Regular(
6007 RegularArray {
6008 len: 1,
6009 stride: 2,
6010 },
6011 ),
6012 ),
6013 enumm: None,
6014 },
6015 Field {
6016 name: "oisn",
6017 description: Some(
6018 "Output Idle state x (x=1)",
6019 ),
6020 bit_offset: BitOffset::Regular(
6021 RegularBitOffset {
6022 offset: 9,
6023 },
6024 ),
6025 bit_size: 1,
6026 array: Some(
6027 Array::Regular(
6028 RegularArray {
6029 len: 1,
6030 stride: 2,
6031 },
6032 ),
6033 ),
6034 enumm: None,
6035 },
6036 ],
6037 },
6038 FieldSet {
6039 name: "Cr22ch",
6040 extends: None,
6041 description: Some(
6042 "control register 2",
6043 ),
6044 bit_size: 32,
6045 fields: &[
6046 Field {
6047 name: "mms",
6048 description: Some(
6049 "Master mode selection",
6050 ),
6051 bit_offset: BitOffset::Cursed(
6052 CursedBitOffset {
6053 ranges: &[
6054 4..=6,
6055 25..=25,
6056 ],
6057 },
6058 ),
6059 bit_size: 4,
6060 array: None,
6061 enumm: Some(
6062 "Mms",
6063 ),
6064 },
6065 Field {
6066 name: "ti1s",
6067 description: Some(
6068 "TI1 selection",
6069 ),
6070 bit_offset: BitOffset::Regular(
6071 RegularBitOffset {
6072 offset: 7,
6073 },
6074 ),
6075 bit_size: 1,
6076 array: None,
6077 enumm: Some(
6078 "Ti1s",
6079 ),
6080 },
6081 ],
6082 },
6083 FieldSet {
6084 name: "Cr22chCmp",
6085 extends: Some(
6086 "CR2_1CH_CMP",
6087 ),
6088 description: Some(
6089 "control register 2",
6090 ),
6091 bit_size: 32,
6092 fields: &[
6093 Field {
6094 name: "ccpc",
6095 description: Some(
6096 "Capture/compare preloaded control",
6097 ),
6098 bit_offset: BitOffset::Regular(
6099 RegularBitOffset {
6100 offset: 0,
6101 },
6102 ),
6103 bit_size: 1,
6104 array: None,
6105 enumm: None,
6106 },
6107 Field {
6108 name: "ccus",
6109 description: Some(
6110 "Capture/compare control update selection",
6111 ),
6112 bit_offset: BitOffset::Regular(
6113 RegularBitOffset {
6114 offset: 2,
6115 },
6116 ),
6117 bit_size: 1,
6118 array: None,
6119 enumm: None,
6120 },
6121 Field {
6122 name: "ccds",
6123 description: Some(
6124 "Capture/compare DMA selection",
6125 ),
6126 bit_offset: BitOffset::Regular(
6127 RegularBitOffset {
6128 offset: 3,
6129 },
6130 ),
6131 bit_size: 1,
6132 array: None,
6133 enumm: Some(
6134 "Ccds",
6135 ),
6136 },
6137 Field {
6138 name: "mms",
6139 description: Some(
6140 "Master mode selection",
6141 ),
6142 bit_offset: BitOffset::Cursed(
6143 CursedBitOffset {
6144 ranges: &[
6145 4..=6,
6146 25..=25,
6147 ],
6148 },
6149 ),
6150 bit_size: 4,
6151 array: None,
6152 enumm: Some(
6153 "Mms",
6154 ),
6155 },
6156 Field {
6157 name: "ti1s",
6158 description: Some(
6159 "TI1 selection",
6160 ),
6161 bit_offset: BitOffset::Regular(
6162 RegularBitOffset {
6163 offset: 7,
6164 },
6165 ),
6166 bit_size: 1,
6167 array: None,
6168 enumm: Some(
6169 "Ti1s",
6170 ),
6171 },
6172 Field {
6173 name: "ois",
6174 description: Some(
6175 "Output Idle state x (x=1,2)",
6176 ),
6177 bit_offset: BitOffset::Regular(
6178 RegularBitOffset {
6179 offset: 8,
6180 },
6181 ),
6182 bit_size: 1,
6183 array: Some(
6184 Array::Regular(
6185 RegularArray {
6186 len: 2,
6187 stride: 2,
6188 },
6189 ),
6190 ),
6191 enumm: None,
6192 },
6193 Field {
6194 name: "oisn",
6195 description: Some(
6196 "Output Idle state x (x=1)",
6197 ),
6198 bit_offset: BitOffset::Regular(
6199 RegularBitOffset {
6200 offset: 9,
6201 },
6202 ),
6203 bit_size: 1,
6204 array: Some(
6205 Array::Regular(
6206 RegularArray {
6207 len: 1,
6208 stride: 2,
6209 },
6210 ),
6211 ),
6212 enumm: None,
6213 },
6214 ],
6215 },
6216 FieldSet {
6217 name: "Cr2Adv",
6218 extends: Some(
6219 "CR2_2CH_CMP",
6220 ),
6221 description: Some(
6222 "control register 2",
6223 ),
6224 bit_size: 32,
6225 fields: &[
6226 Field {
6227 name: "ccpc",
6228 description: Some(
6229 "Capture/compare preloaded control",
6230 ),
6231 bit_offset: BitOffset::Regular(
6232 RegularBitOffset {
6233 offset: 0,
6234 },
6235 ),
6236 bit_size: 1,
6237 array: None,
6238 enumm: None,
6239 },
6240 Field {
6241 name: "ccus",
6242 description: Some(
6243 "Capture/compare control update selection",
6244 ),
6245 bit_offset: BitOffset::Regular(
6246 RegularBitOffset {
6247 offset: 2,
6248 },
6249 ),
6250 bit_size: 1,
6251 array: None,
6252 enumm: None,
6253 },
6254 Field {
6255 name: "ccds",
6256 description: Some(
6257 "Capture/compare DMA selection",
6258 ),
6259 bit_offset: BitOffset::Regular(
6260 RegularBitOffset {
6261 offset: 3,
6262 },
6263 ),
6264 bit_size: 1,
6265 array: None,
6266 enumm: Some(
6267 "Ccds",
6268 ),
6269 },
6270 Field {
6271 name: "mms",
6272 description: Some(
6273 "Master mode selection",
6274 ),
6275 bit_offset: BitOffset::Cursed(
6276 CursedBitOffset {
6277 ranges: &[
6278 4..=6,
6279 25..=25,
6280 ],
6281 },
6282 ),
6283 bit_size: 4,
6284 array: None,
6285 enumm: Some(
6286 "Mms",
6287 ),
6288 },
6289 Field {
6290 name: "ti1s",
6291 description: Some(
6292 "TI1 selection",
6293 ),
6294 bit_offset: BitOffset::Regular(
6295 RegularBitOffset {
6296 offset: 7,
6297 },
6298 ),
6299 bit_size: 1,
6300 array: None,
6301 enumm: Some(
6302 "Ti1s",
6303 ),
6304 },
6305 Field {
6306 name: "ois",
6307 description: Some(
6308 "Output Idle state x (x=1-6)",
6309 ),
6310 bit_offset: BitOffset::Regular(
6311 RegularBitOffset {
6312 offset: 8,
6313 },
6314 ),
6315 bit_size: 1,
6316 array: Some(
6317 Array::Regular(
6318 RegularArray {
6319 len: 6,
6320 stride: 2,
6321 },
6322 ),
6323 ),
6324 enumm: None,
6325 },
6326 Field {
6327 name: "oisn",
6328 description: Some(
6329 "Output Idle state x N x (x=1-4)",
6330 ),
6331 bit_offset: BitOffset::Regular(
6332 RegularBitOffset {
6333 offset: 9,
6334 },
6335 ),
6336 bit_size: 1,
6337 array: Some(
6338 Array::Regular(
6339 RegularArray {
6340 len: 4,
6341 stride: 2,
6342 },
6343 ),
6344 ),
6345 enumm: None,
6346 },
6347 Field {
6348 name: "mms2",
6349 description: Some(
6350 "Master mode selection 2",
6351 ),
6352 bit_offset: BitOffset::Regular(
6353 RegularBitOffset {
6354 offset: 20,
6355 },
6356 ),
6357 bit_size: 4,
6358 array: None,
6359 enumm: Some(
6360 "Mms2",
6361 ),
6362 },
6363 ],
6364 },
6365 FieldSet {
6366 name: "Cr2Basic",
6367 extends: None,
6368 description: Some(
6369 "control register 2",
6370 ),
6371 bit_size: 32,
6372 fields: &[
6373 Field {
6374 name: "mms",
6375 description: Some(
6376 "Master mode selection",
6377 ),
6378 bit_offset: BitOffset::Cursed(
6379 CursedBitOffset {
6380 ranges: &[
6381 4..=6,
6382 25..=25,
6383 ],
6384 },
6385 ),
6386 bit_size: 4,
6387 array: None,
6388 enumm: Some(
6389 "Mms",
6390 ),
6391 },
6392 ],
6393 },
6394 FieldSet {
6395 name: "Cr2Gp16",
6396 extends: Some(
6397 "CR2_BASIC",
6398 ),
6399 description: Some(
6400 "control register 2",
6401 ),
6402 bit_size: 32,
6403 fields: &[
6404 Field {
6405 name: "ccds",
6406 description: Some(
6407 "Capture/compare DMA selection",
6408 ),
6409 bit_offset: BitOffset::Regular(
6410 RegularBitOffset {
6411 offset: 3,
6412 },
6413 ),
6414 bit_size: 1,
6415 array: None,
6416 enumm: Some(
6417 "Ccds",
6418 ),
6419 },
6420 Field {
6421 name: "mms",
6422 description: Some(
6423 "Master mode selection",
6424 ),
6425 bit_offset: BitOffset::Cursed(
6426 CursedBitOffset {
6427 ranges: &[
6428 4..=6,
6429 25..=25,
6430 ],
6431 },
6432 ),
6433 bit_size: 4,
6434 array: None,
6435 enumm: Some(
6436 "Mms",
6437 ),
6438 },
6439 Field {
6440 name: "ti1s",
6441 description: Some(
6442 "TI1 selection",
6443 ),
6444 bit_offset: BitOffset::Regular(
6445 RegularBitOffset {
6446 offset: 7,
6447 },
6448 ),
6449 bit_size: 1,
6450 array: None,
6451 enumm: Some(
6452 "Ti1s",
6453 ),
6454 },
6455 ],
6456 },
6457 FieldSet {
6458 name: "Dcr1chCmp",
6459 extends: None,
6460 description: Some(
6461 "DMA control register",
6462 ),
6463 bit_size: 32,
6464 fields: &[
6465 Field {
6466 name: "dba",
6467 description: Some(
6468 "DMA base address",
6469 ),
6470 bit_offset: BitOffset::Regular(
6471 RegularBitOffset {
6472 offset: 0,
6473 },
6474 ),
6475 bit_size: 5,
6476 array: None,
6477 enumm: None,
6478 },
6479 Field {
6480 name: "dbl",
6481 description: Some(
6482 "DMA burst length",
6483 ),
6484 bit_offset: BitOffset::Regular(
6485 RegularBitOffset {
6486 offset: 8,
6487 },
6488 ),
6489 bit_size: 5,
6490 array: None,
6491 enumm: None,
6492 },
6493 Field {
6494 name: "dbss",
6495 description: Some(
6496 "DMA burst source selection",
6497 ),
6498 bit_offset: BitOffset::Regular(
6499 RegularBitOffset {
6500 offset: 16,
6501 },
6502 ),
6503 bit_size: 4,
6504 array: None,
6505 enumm: Some(
6506 "Dbss",
6507 ),
6508 },
6509 ],
6510 },
6511 FieldSet {
6512 name: "Dier1ch",
6513 extends: Some(
6514 "DIER_CORE",
6515 ),
6516 description: Some(
6517 "DMA/Interrupt enable register",
6518 ),
6519 bit_size: 32,
6520 fields: &[
6521 Field {
6522 name: "uie",
6523 description: Some(
6524 "Update interrupt enable",
6525 ),
6526 bit_offset: BitOffset::Regular(
6527 RegularBitOffset {
6528 offset: 0,
6529 },
6530 ),
6531 bit_size: 1,
6532 array: None,
6533 enumm: None,
6534 },
6535 Field {
6536 name: "ccie",
6537 description: Some(
6538 "Capture/Compare x (x=1) interrupt enable",
6539 ),
6540 bit_offset: BitOffset::Regular(
6541 RegularBitOffset {
6542 offset: 1,
6543 },
6544 ),
6545 bit_size: 1,
6546 array: Some(
6547 Array::Regular(
6548 RegularArray {
6549 len: 1,
6550 stride: 1,
6551 },
6552 ),
6553 ),
6554 enumm: None,
6555 },
6556 ],
6557 },
6558 FieldSet {
6559 name: "Dier1chCmp",
6560 extends: Some(
6561 "DIER_1CH",
6562 ),
6563 description: Some(
6564 "DMA/Interrupt enable register",
6565 ),
6566 bit_size: 32,
6567 fields: &[
6568 Field {
6569 name: "uie",
6570 description: Some(
6571 "Update interrupt enable",
6572 ),
6573 bit_offset: BitOffset::Regular(
6574 RegularBitOffset {
6575 offset: 0,
6576 },
6577 ),
6578 bit_size: 1,
6579 array: None,
6580 enumm: None,
6581 },
6582 Field {
6583 name: "ccie",
6584 description: Some(
6585 "Capture/Compare x (x=1) interrupt enable",
6586 ),
6587 bit_offset: BitOffset::Regular(
6588 RegularBitOffset {
6589 offset: 1,
6590 },
6591 ),
6592 bit_size: 1,
6593 array: Some(
6594 Array::Regular(
6595 RegularArray {
6596 len: 1,
6597 stride: 1,
6598 },
6599 ),
6600 ),
6601 enumm: None,
6602 },
6603 Field {
6604 name: "comie",
6605 description: Some(
6606 "COM interrupt enable",
6607 ),
6608 bit_offset: BitOffset::Regular(
6609 RegularBitOffset {
6610 offset: 5,
6611 },
6612 ),
6613 bit_size: 1,
6614 array: None,
6615 enumm: None,
6616 },
6617 Field {
6618 name: "bie",
6619 description: Some(
6620 "Break interrupt enable",
6621 ),
6622 bit_offset: BitOffset::Regular(
6623 RegularBitOffset {
6624 offset: 7,
6625 },
6626 ),
6627 bit_size: 1,
6628 array: None,
6629 enumm: None,
6630 },
6631 Field {
6632 name: "ude",
6633 description: Some(
6634 "Update DMA request enable",
6635 ),
6636 bit_offset: BitOffset::Regular(
6637 RegularBitOffset {
6638 offset: 8,
6639 },
6640 ),
6641 bit_size: 1,
6642 array: None,
6643 enumm: None,
6644 },
6645 Field {
6646 name: "ccde",
6647 description: Some(
6648 "Capture/Compare x (x=1) DMA request enable",
6649 ),
6650 bit_offset: BitOffset::Regular(
6651 RegularBitOffset {
6652 offset: 9,
6653 },
6654 ),
6655 bit_size: 1,
6656 array: Some(
6657 Array::Regular(
6658 RegularArray {
6659 len: 1,
6660 stride: 1,
6661 },
6662 ),
6663 ),
6664 enumm: None,
6665 },
6666 ],
6667 },
6668 FieldSet {
6669 name: "Dier2ch",
6670 extends: Some(
6671 "DIER_1CH",
6672 ),
6673 description: Some(
6674 "DMA/Interrupt enable register",
6675 ),
6676 bit_size: 32,
6677 fields: &[
6678 Field {
6679 name: "uie",
6680 description: Some(
6681 "Update interrupt enable",
6682 ),
6683 bit_offset: BitOffset::Regular(
6684 RegularBitOffset {
6685 offset: 0,
6686 },
6687 ),
6688 bit_size: 1,
6689 array: None,
6690 enumm: None,
6691 },
6692 Field {
6693 name: "ccie",
6694 description: Some(
6695 "Capture/Compare x (x=1-2) interrupt enable",
6696 ),
6697 bit_offset: BitOffset::Regular(
6698 RegularBitOffset {
6699 offset: 1,
6700 },
6701 ),
6702 bit_size: 1,
6703 array: Some(
6704 Array::Regular(
6705 RegularArray {
6706 len: 2,
6707 stride: 1,
6708 },
6709 ),
6710 ),
6711 enumm: None,
6712 },
6713 Field {
6714 name: "tie",
6715 description: Some(
6716 "Trigger interrupt enable",
6717 ),
6718 bit_offset: BitOffset::Regular(
6719 RegularBitOffset {
6720 offset: 6,
6721 },
6722 ),
6723 bit_size: 1,
6724 array: None,
6725 enumm: None,
6726 },
6727 ],
6728 },
6729 FieldSet {
6730 name: "Dier2chCmp",
6731 extends: Some(
6732 "DIER_1CH_CMP",
6733 ),
6734 description: Some(
6735 "DMA/Interrupt enable register",
6736 ),
6737 bit_size: 32,
6738 fields: &[
6739 Field {
6740 name: "uie",
6741 description: Some(
6742 "Update interrupt enable",
6743 ),
6744 bit_offset: BitOffset::Regular(
6745 RegularBitOffset {
6746 offset: 0,
6747 },
6748 ),
6749 bit_size: 1,
6750 array: None,
6751 enumm: None,
6752 },
6753 Field {
6754 name: "ccie",
6755 description: Some(
6756 "Capture/Compare x (x=1) interrupt enable",
6757 ),
6758 bit_offset: BitOffset::Regular(
6759 RegularBitOffset {
6760 offset: 1,
6761 },
6762 ),
6763 bit_size: 1,
6764 array: Some(
6765 Array::Regular(
6766 RegularArray {
6767 len: 1,
6768 stride: 1,
6769 },
6770 ),
6771 ),
6772 enumm: None,
6773 },
6774 Field {
6775 name: "comie",
6776 description: Some(
6777 "COM interrupt enable",
6778 ),
6779 bit_offset: BitOffset::Regular(
6780 RegularBitOffset {
6781 offset: 5,
6782 },
6783 ),
6784 bit_size: 1,
6785 array: None,
6786 enumm: None,
6787 },
6788 Field {
6789 name: "tie",
6790 description: Some(
6791 "Trigger interrupt enable",
6792 ),
6793 bit_offset: BitOffset::Regular(
6794 RegularBitOffset {
6795 offset: 6,
6796 },
6797 ),
6798 bit_size: 1,
6799 array: None,
6800 enumm: None,
6801 },
6802 Field {
6803 name: "bie",
6804 description: Some(
6805 "Break interrupt enable",
6806 ),
6807 bit_offset: BitOffset::Regular(
6808 RegularBitOffset {
6809 offset: 7,
6810 },
6811 ),
6812 bit_size: 1,
6813 array: None,
6814 enumm: None,
6815 },
6816 Field {
6817 name: "ude",
6818 description: Some(
6819 "Update DMA request enable",
6820 ),
6821 bit_offset: BitOffset::Regular(
6822 RegularBitOffset {
6823 offset: 8,
6824 },
6825 ),
6826 bit_size: 1,
6827 array: None,
6828 enumm: None,
6829 },
6830 Field {
6831 name: "ccde",
6832 description: Some(
6833 "Capture/Compare x (x=1) DMA request enable",
6834 ),
6835 bit_offset: BitOffset::Regular(
6836 RegularBitOffset {
6837 offset: 9,
6838 },
6839 ),
6840 bit_size: 1,
6841 array: Some(
6842 Array::Regular(
6843 RegularArray {
6844 len: 1,
6845 stride: 1,
6846 },
6847 ),
6848 ),
6849 enumm: None,
6850 },
6851 Field {
6852 name: "comde",
6853 description: Some(
6854 "COM DMA request enable",
6855 ),
6856 bit_offset: BitOffset::Regular(
6857 RegularBitOffset {
6858 offset: 13,
6859 },
6860 ),
6861 bit_size: 1,
6862 array: None,
6863 enumm: None,
6864 },
6865 Field {
6866 name: "tde",
6867 description: Some(
6868 "Trigger DMA request enable",
6869 ),
6870 bit_offset: BitOffset::Regular(
6871 RegularBitOffset {
6872 offset: 14,
6873 },
6874 ),
6875 bit_size: 1,
6876 array: None,
6877 enumm: None,
6878 },
6879 ],
6880 },
6881 FieldSet {
6882 name: "DierAdv",
6883 extends: Some(
6884 "DIER_2CH_CMP",
6885 ),
6886 description: Some(
6887 "DMA/Interrupt enable register",
6888 ),
6889 bit_size: 32,
6890 fields: &[
6891 Field {
6892 name: "uie",
6893 description: Some(
6894 "Update interrupt enable",
6895 ),
6896 bit_offset: BitOffset::Regular(
6897 RegularBitOffset {
6898 offset: 0,
6899 },
6900 ),
6901 bit_size: 1,
6902 array: None,
6903 enumm: None,
6904 },
6905 Field {
6906 name: "ccie",
6907 description: Some(
6908 "Capture/Compare x (x=1-4) interrupt enable",
6909 ),
6910 bit_offset: BitOffset::Regular(
6911 RegularBitOffset {
6912 offset: 1,
6913 },
6914 ),
6915 bit_size: 1,
6916 array: Some(
6917 Array::Regular(
6918 RegularArray {
6919 len: 4,
6920 stride: 1,
6921 },
6922 ),
6923 ),
6924 enumm: None,
6925 },
6926 Field {
6927 name: "comie",
6928 description: Some(
6929 "COM interrupt enable",
6930 ),
6931 bit_offset: BitOffset::Regular(
6932 RegularBitOffset {
6933 offset: 5,
6934 },
6935 ),
6936 bit_size: 1,
6937 array: None,
6938 enumm: None,
6939 },
6940 Field {
6941 name: "tie",
6942 description: Some(
6943 "Trigger interrupt enable",
6944 ),
6945 bit_offset: BitOffset::Regular(
6946 RegularBitOffset {
6947 offset: 6,
6948 },
6949 ),
6950 bit_size: 1,
6951 array: None,
6952 enumm: None,
6953 },
6954 Field {
6955 name: "bie",
6956 description: Some(
6957 "Break interrupt enable",
6958 ),
6959 bit_offset: BitOffset::Regular(
6960 RegularBitOffset {
6961 offset: 7,
6962 },
6963 ),
6964 bit_size: 1,
6965 array: None,
6966 enumm: None,
6967 },
6968 Field {
6969 name: "ude",
6970 description: Some(
6971 "Update DMA request enable",
6972 ),
6973 bit_offset: BitOffset::Regular(
6974 RegularBitOffset {
6975 offset: 8,
6976 },
6977 ),
6978 bit_size: 1,
6979 array: None,
6980 enumm: None,
6981 },
6982 Field {
6983 name: "ccde",
6984 description: Some(
6985 "Capture/Compare x (x=1) DMA request enable",
6986 ),
6987 bit_offset: BitOffset::Regular(
6988 RegularBitOffset {
6989 offset: 9,
6990 },
6991 ),
6992 bit_size: 1,
6993 array: Some(
6994 Array::Regular(
6995 RegularArray {
6996 len: 4,
6997 stride: 1,
6998 },
6999 ),
7000 ),
7001 enumm: None,
7002 },
7003 Field {
7004 name: "comde",
7005 description: Some(
7006 "COM DMA request enable",
7007 ),
7008 bit_offset: BitOffset::Regular(
7009 RegularBitOffset {
7010 offset: 13,
7011 },
7012 ),
7013 bit_size: 1,
7014 array: None,
7015 enumm: None,
7016 },
7017 Field {
7018 name: "tde",
7019 description: Some(
7020 "Trigger DMA request enable",
7021 ),
7022 bit_offset: BitOffset::Regular(
7023 RegularBitOffset {
7024 offset: 14,
7025 },
7026 ),
7027 bit_size: 1,
7028 array: None,
7029 enumm: None,
7030 },
7031 Field {
7032 name: "idxie",
7033 description: Some(
7034 "Index interrupt enable",
7035 ),
7036 bit_offset: BitOffset::Regular(
7037 RegularBitOffset {
7038 offset: 20,
7039 },
7040 ),
7041 bit_size: 1,
7042 array: None,
7043 enumm: None,
7044 },
7045 Field {
7046 name: "dirie",
7047 description: Some(
7048 "Direction change interrupt enable",
7049 ),
7050 bit_offset: BitOffset::Regular(
7051 RegularBitOffset {
7052 offset: 21,
7053 },
7054 ),
7055 bit_size: 1,
7056 array: None,
7057 enumm: None,
7058 },
7059 Field {
7060 name: "ierrie",
7061 description: Some(
7062 "Index error interrupt enable",
7063 ),
7064 bit_offset: BitOffset::Regular(
7065 RegularBitOffset {
7066 offset: 22,
7067 },
7068 ),
7069 bit_size: 1,
7070 array: None,
7071 enumm: None,
7072 },
7073 Field {
7074 name: "terrie",
7075 description: Some(
7076 "Transition error interrupt enable",
7077 ),
7078 bit_offset: BitOffset::Regular(
7079 RegularBitOffset {
7080 offset: 23,
7081 },
7082 ),
7083 bit_size: 1,
7084 array: None,
7085 enumm: None,
7086 },
7087 ],
7088 },
7089 FieldSet {
7090 name: "DierBasicNoCr2",
7091 extends: Some(
7092 "DIER_CORE",
7093 ),
7094 description: Some(
7095 "DMA/Interrupt enable register",
7096 ),
7097 bit_size: 32,
7098 fields: &[
7099 Field {
7100 name: "uie",
7101 description: Some(
7102 "Update interrupt enable",
7103 ),
7104 bit_offset: BitOffset::Regular(
7105 RegularBitOffset {
7106 offset: 0,
7107 },
7108 ),
7109 bit_size: 1,
7110 array: None,
7111 enumm: None,
7112 },
7113 Field {
7114 name: "ude",
7115 description: Some(
7116 "Update DMA request enable",
7117 ),
7118 bit_offset: BitOffset::Regular(
7119 RegularBitOffset {
7120 offset: 8,
7121 },
7122 ),
7123 bit_size: 1,
7124 array: None,
7125 enumm: None,
7126 },
7127 ],
7128 },
7129 FieldSet {
7130 name: "DierCore",
7131 extends: None,
7132 description: Some(
7133 "DMA/Interrupt enable register",
7134 ),
7135 bit_size: 32,
7136 fields: &[
7137 Field {
7138 name: "uie",
7139 description: Some(
7140 "Update interrupt enable",
7141 ),
7142 bit_offset: BitOffset::Regular(
7143 RegularBitOffset {
7144 offset: 0,
7145 },
7146 ),
7147 bit_size: 1,
7148 array: None,
7149 enumm: None,
7150 },
7151 ],
7152 },
7153 FieldSet {
7154 name: "DierGp16",
7155 extends: Some(
7156 "DIER_BASIC_NO_CR2",
7157 ),
7158 description: Some(
7159 "DMA/Interrupt enable register",
7160 ),
7161 bit_size: 32,
7162 fields: &[
7163 Field {
7164 name: "uie",
7165 description: Some(
7166 "Update interrupt enable",
7167 ),
7168 bit_offset: BitOffset::Regular(
7169 RegularBitOffset {
7170 offset: 0,
7171 },
7172 ),
7173 bit_size: 1,
7174 array: None,
7175 enumm: None,
7176 },
7177 Field {
7178 name: "ccie",
7179 description: Some(
7180 "Capture/Compare x (x=1-4) interrupt enable",
7181 ),
7182 bit_offset: BitOffset::Regular(
7183 RegularBitOffset {
7184 offset: 1,
7185 },
7186 ),
7187 bit_size: 1,
7188 array: Some(
7189 Array::Regular(
7190 RegularArray {
7191 len: 4,
7192 stride: 1,
7193 },
7194 ),
7195 ),
7196 enumm: None,
7197 },
7198 Field {
7199 name: "tie",
7200 description: Some(
7201 "Trigger interrupt enable",
7202 ),
7203 bit_offset: BitOffset::Regular(
7204 RegularBitOffset {
7205 offset: 6,
7206 },
7207 ),
7208 bit_size: 1,
7209 array: None,
7210 enumm: None,
7211 },
7212 Field {
7213 name: "ude",
7214 description: Some(
7215 "Update DMA request enable",
7216 ),
7217 bit_offset: BitOffset::Regular(
7218 RegularBitOffset {
7219 offset: 8,
7220 },
7221 ),
7222 bit_size: 1,
7223 array: None,
7224 enumm: None,
7225 },
7226 Field {
7227 name: "ccde",
7228 description: Some(
7229 "Capture/Compare x (x=1-4) DMA request enable",
7230 ),
7231 bit_offset: BitOffset::Regular(
7232 RegularBitOffset {
7233 offset: 9,
7234 },
7235 ),
7236 bit_size: 1,
7237 array: Some(
7238 Array::Regular(
7239 RegularArray {
7240 len: 4,
7241 stride: 1,
7242 },
7243 ),
7244 ),
7245 enumm: None,
7246 },
7247 Field {
7248 name: "tde",
7249 description: Some(
7250 "Trigger DMA request enable",
7251 ),
7252 bit_offset: BitOffset::Regular(
7253 RegularBitOffset {
7254 offset: 14,
7255 },
7256 ),
7257 bit_size: 1,
7258 array: None,
7259 enumm: None,
7260 },
7261 Field {
7262 name: "idxie",
7263 description: Some(
7264 "Index interrupt enable",
7265 ),
7266 bit_offset: BitOffset::Regular(
7267 RegularBitOffset {
7268 offset: 20,
7269 },
7270 ),
7271 bit_size: 1,
7272 array: None,
7273 enumm: None,
7274 },
7275 Field {
7276 name: "dirie",
7277 description: Some(
7278 "Direction change interrupt enable",
7279 ),
7280 bit_offset: BitOffset::Regular(
7281 RegularBitOffset {
7282 offset: 21,
7283 },
7284 ),
7285 bit_size: 1,
7286 array: None,
7287 enumm: None,
7288 },
7289 Field {
7290 name: "ierrie",
7291 description: Some(
7292 "Index error interrupt enable",
7293 ),
7294 bit_offset: BitOffset::Regular(
7295 RegularBitOffset {
7296 offset: 22,
7297 },
7298 ),
7299 bit_size: 1,
7300 array: None,
7301 enumm: None,
7302 },
7303 Field {
7304 name: "terrie",
7305 description: Some(
7306 "Transition error interrupt enable",
7307 ),
7308 bit_offset: BitOffset::Regular(
7309 RegularBitOffset {
7310 offset: 23,
7311 },
7312 ),
7313 bit_size: 1,
7314 array: None,
7315 enumm: None,
7316 },
7317 ],
7318 },
7319 FieldSet {
7320 name: "Dtr21chCmp",
7321 extends: None,
7322 description: Some(
7323 "deadtime register 2",
7324 ),
7325 bit_size: 32,
7326 fields: &[
7327 Field {
7328 name: "dtgf",
7329 description: Some(
7330 "Dead-time falling edge generator setup",
7331 ),
7332 bit_offset: BitOffset::Regular(
7333 RegularBitOffset {
7334 offset: 0,
7335 },
7336 ),
7337 bit_size: 8,
7338 array: None,
7339 enumm: None,
7340 },
7341 Field {
7342 name: "dtae",
7343 description: Some(
7344 "Deadtime asymmetric enable",
7345 ),
7346 bit_offset: BitOffset::Regular(
7347 RegularBitOffset {
7348 offset: 16,
7349 },
7350 ),
7351 bit_size: 1,
7352 array: None,
7353 enumm: Some(
7354 "Dtae",
7355 ),
7356 },
7357 Field {
7358 name: "dtpe",
7359 description: Some(
7360 "Deadtime preload enable",
7361 ),
7362 bit_offset: BitOffset::Regular(
7363 RegularBitOffset {
7364 offset: 17,
7365 },
7366 ),
7367 bit_size: 1,
7368 array: None,
7369 enumm: None,
7370 },
7371 ],
7372 },
7373 FieldSet {
7374 name: "EcrGp16",
7375 extends: None,
7376 description: Some(
7377 "encoder control register",
7378 ),
7379 bit_size: 32,
7380 fields: &[
7381 Field {
7382 name: "ie",
7383 description: Some(
7384 "Index enable",
7385 ),
7386 bit_offset: BitOffset::Regular(
7387 RegularBitOffset {
7388 offset: 0,
7389 },
7390 ),
7391 bit_size: 1,
7392 array: None,
7393 enumm: None,
7394 },
7395 Field {
7396 name: "idir",
7397 description: Some(
7398 "Index direction",
7399 ),
7400 bit_offset: BitOffset::Regular(
7401 RegularBitOffset {
7402 offset: 1,
7403 },
7404 ),
7405 bit_size: 2,
7406 array: None,
7407 enumm: Some(
7408 "Idir",
7409 ),
7410 },
7411 Field {
7412 name: "iblk",
7413 description: Some(
7414 "Index blanking",
7415 ),
7416 bit_offset: BitOffset::Regular(
7417 RegularBitOffset {
7418 offset: 3,
7419 },
7420 ),
7421 bit_size: 2,
7422 array: None,
7423 enumm: Some(
7424 "Iblk",
7425 ),
7426 },
7427 Field {
7428 name: "fidx",
7429 description: Some(
7430 "First index",
7431 ),
7432 bit_offset: BitOffset::Regular(
7433 RegularBitOffset {
7434 offset: 5,
7435 },
7436 ),
7437 bit_size: 1,
7438 array: None,
7439 enumm: Some(
7440 "Fidx",
7441 ),
7442 },
7443 Field {
7444 name: "ipos",
7445 description: Some(
7446 "Index positioning",
7447 ),
7448 bit_offset: BitOffset::Regular(
7449 RegularBitOffset {
7450 offset: 6,
7451 },
7452 ),
7453 bit_size: 2,
7454 array: None,
7455 enumm: None,
7456 },
7457 Field {
7458 name: "pw",
7459 description: Some(
7460 "Pulse width",
7461 ),
7462 bit_offset: BitOffset::Regular(
7463 RegularBitOffset {
7464 offset: 16,
7465 },
7466 ),
7467 bit_size: 8,
7468 array: None,
7469 enumm: None,
7470 },
7471 Field {
7472 name: "pwprsc",
7473 description: Some(
7474 "Pulse width prescaler",
7475 ),
7476 bit_offset: BitOffset::Regular(
7477 RegularBitOffset {
7478 offset: 24,
7479 },
7480 ),
7481 bit_size: 2,
7482 array: None,
7483 enumm: None,
7484 },
7485 ],
7486 },
7487 FieldSet {
7488 name: "Egr1ch",
7489 extends: Some(
7490 "EGR_CORE",
7491 ),
7492 description: Some(
7493 "event generation register",
7494 ),
7495 bit_size: 32,
7496 fields: &[
7497 Field {
7498 name: "ug",
7499 description: Some(
7500 "Update generation",
7501 ),
7502 bit_offset: BitOffset::Regular(
7503 RegularBitOffset {
7504 offset: 0,
7505 },
7506 ),
7507 bit_size: 1,
7508 array: None,
7509 enumm: None,
7510 },
7511 Field {
7512 name: "ccg",
7513 description: Some(
7514 "Capture/compare x (x=1) generation",
7515 ),
7516 bit_offset: BitOffset::Regular(
7517 RegularBitOffset {
7518 offset: 1,
7519 },
7520 ),
7521 bit_size: 1,
7522 array: Some(
7523 Array::Regular(
7524 RegularArray {
7525 len: 1,
7526 stride: 1,
7527 },
7528 ),
7529 ),
7530 enumm: None,
7531 },
7532 ],
7533 },
7534 FieldSet {
7535 name: "Egr1chCmp",
7536 extends: Some(
7537 "EGR_1CH",
7538 ),
7539 description: Some(
7540 "event generation register",
7541 ),
7542 bit_size: 32,
7543 fields: &[
7544 Field {
7545 name: "ug",
7546 description: Some(
7547 "Update generation",
7548 ),
7549 bit_offset: BitOffset::Regular(
7550 RegularBitOffset {
7551 offset: 0,
7552 },
7553 ),
7554 bit_size: 1,
7555 array: None,
7556 enumm: None,
7557 },
7558 Field {
7559 name: "ccg",
7560 description: Some(
7561 "Capture/compare x (x=1) generation",
7562 ),
7563 bit_offset: BitOffset::Regular(
7564 RegularBitOffset {
7565 offset: 1,
7566 },
7567 ),
7568 bit_size: 1,
7569 array: Some(
7570 Array::Regular(
7571 RegularArray {
7572 len: 1,
7573 stride: 1,
7574 },
7575 ),
7576 ),
7577 enumm: None,
7578 },
7579 Field {
7580 name: "comg",
7581 description: Some(
7582 "Capture/Compare control update generation",
7583 ),
7584 bit_offset: BitOffset::Regular(
7585 RegularBitOffset {
7586 offset: 5,
7587 },
7588 ),
7589 bit_size: 1,
7590 array: None,
7591 enumm: None,
7592 },
7593 Field {
7594 name: "bg",
7595 description: Some(
7596 "Break x (x=1) generation",
7597 ),
7598 bit_offset: BitOffset::Regular(
7599 RegularBitOffset {
7600 offset: 7,
7601 },
7602 ),
7603 bit_size: 1,
7604 array: Some(
7605 Array::Regular(
7606 RegularArray {
7607 len: 1,
7608 stride: 1,
7609 },
7610 ),
7611 ),
7612 enumm: None,
7613 },
7614 ],
7615 },
7616 FieldSet {
7617 name: "Egr2ch",
7618 extends: Some(
7619 "EGR_1CH",
7620 ),
7621 description: Some(
7622 "event generation register",
7623 ),
7624 bit_size: 32,
7625 fields: &[
7626 Field {
7627 name: "ug",
7628 description: Some(
7629 "Update generation",
7630 ),
7631 bit_offset: BitOffset::Regular(
7632 RegularBitOffset {
7633 offset: 0,
7634 },
7635 ),
7636 bit_size: 1,
7637 array: None,
7638 enumm: None,
7639 },
7640 Field {
7641 name: "ccg",
7642 description: Some(
7643 "Capture/compare x (x=1-2) generation",
7644 ),
7645 bit_offset: BitOffset::Regular(
7646 RegularBitOffset {
7647 offset: 1,
7648 },
7649 ),
7650 bit_size: 1,
7651 array: Some(
7652 Array::Regular(
7653 RegularArray {
7654 len: 2,
7655 stride: 1,
7656 },
7657 ),
7658 ),
7659 enumm: None,
7660 },
7661 Field {
7662 name: "tg",
7663 description: Some(
7664 "Trigger generation",
7665 ),
7666 bit_offset: BitOffset::Regular(
7667 RegularBitOffset {
7668 offset: 6,
7669 },
7670 ),
7671 bit_size: 1,
7672 array: None,
7673 enumm: None,
7674 },
7675 ],
7676 },
7677 FieldSet {
7678 name: "Egr2chCmp",
7679 extends: Some(
7680 "EGR_1CH_CMP",
7681 ),
7682 description: Some(
7683 "event generation register",
7684 ),
7685 bit_size: 32,
7686 fields: &[
7687 Field {
7688 name: "ug",
7689 description: Some(
7690 "Update generation",
7691 ),
7692 bit_offset: BitOffset::Regular(
7693 RegularBitOffset {
7694 offset: 0,
7695 },
7696 ),
7697 bit_size: 1,
7698 array: None,
7699 enumm: None,
7700 },
7701 Field {
7702 name: "ccg",
7703 description: Some(
7704 "Capture/compare x (x=1,2) generation",
7705 ),
7706 bit_offset: BitOffset::Regular(
7707 RegularBitOffset {
7708 offset: 1,
7709 },
7710 ),
7711 bit_size: 1,
7712 array: Some(
7713 Array::Regular(
7714 RegularArray {
7715 len: 2,
7716 stride: 1,
7717 },
7718 ),
7719 ),
7720 enumm: None,
7721 },
7722 Field {
7723 name: "comg",
7724 description: Some(
7725 "Capture/Compare control update generation",
7726 ),
7727 bit_offset: BitOffset::Regular(
7728 RegularBitOffset {
7729 offset: 5,
7730 },
7731 ),
7732 bit_size: 1,
7733 array: None,
7734 enumm: None,
7735 },
7736 Field {
7737 name: "tg",
7738 description: Some(
7739 "Trigger generation",
7740 ),
7741 bit_offset: BitOffset::Regular(
7742 RegularBitOffset {
7743 offset: 6,
7744 },
7745 ),
7746 bit_size: 1,
7747 array: None,
7748 enumm: None,
7749 },
7750 Field {
7751 name: "bg",
7752 description: Some(
7753 "Break x (x=1) generation",
7754 ),
7755 bit_offset: BitOffset::Regular(
7756 RegularBitOffset {
7757 offset: 7,
7758 },
7759 ),
7760 bit_size: 1,
7761 array: Some(
7762 Array::Regular(
7763 RegularArray {
7764 len: 1,
7765 stride: 1,
7766 },
7767 ),
7768 ),
7769 enumm: None,
7770 },
7771 ],
7772 },
7773 FieldSet {
7774 name: "EgrAdv",
7775 extends: Some(
7776 "EGR_2CH_CMP",
7777 ),
7778 description: Some(
7779 "event generation register",
7780 ),
7781 bit_size: 32,
7782 fields: &[
7783 Field {
7784 name: "ug",
7785 description: Some(
7786 "Update generation",
7787 ),
7788 bit_offset: BitOffset::Regular(
7789 RegularBitOffset {
7790 offset: 0,
7791 },
7792 ),
7793 bit_size: 1,
7794 array: None,
7795 enumm: None,
7796 },
7797 Field {
7798 name: "ccg",
7799 description: Some(
7800 "Capture/compare x (x=1-4) generation",
7801 ),
7802 bit_offset: BitOffset::Regular(
7803 RegularBitOffset {
7804 offset: 1,
7805 },
7806 ),
7807 bit_size: 1,
7808 array: Some(
7809 Array::Regular(
7810 RegularArray {
7811 len: 4,
7812 stride: 1,
7813 },
7814 ),
7815 ),
7816 enumm: None,
7817 },
7818 Field {
7819 name: "comg",
7820 description: Some(
7821 "Capture/Compare control update generation",
7822 ),
7823 bit_offset: BitOffset::Regular(
7824 RegularBitOffset {
7825 offset: 5,
7826 },
7827 ),
7828 bit_size: 1,
7829 array: None,
7830 enumm: None,
7831 },
7832 Field {
7833 name: "tg",
7834 description: Some(
7835 "Trigger generation",
7836 ),
7837 bit_offset: BitOffset::Regular(
7838 RegularBitOffset {
7839 offset: 6,
7840 },
7841 ),
7842 bit_size: 1,
7843 array: None,
7844 enumm: None,
7845 },
7846 Field {
7847 name: "bg",
7848 description: Some(
7849 "Break x (x=1-2) generation",
7850 ),
7851 bit_offset: BitOffset::Regular(
7852 RegularBitOffset {
7853 offset: 7,
7854 },
7855 ),
7856 bit_size: 1,
7857 array: Some(
7858 Array::Regular(
7859 RegularArray {
7860 len: 2,
7861 stride: 1,
7862 },
7863 ),
7864 ),
7865 enumm: None,
7866 },
7867 ],
7868 },
7869 FieldSet {
7870 name: "EgrCore",
7871 extends: None,
7872 description: Some(
7873 "event generation register",
7874 ),
7875 bit_size: 32,
7876 fields: &[
7877 Field {
7878 name: "ug",
7879 description: Some(
7880 "Update generation",
7881 ),
7882 bit_offset: BitOffset::Regular(
7883 RegularBitOffset {
7884 offset: 0,
7885 },
7886 ),
7887 bit_size: 1,
7888 array: None,
7889 enumm: None,
7890 },
7891 ],
7892 },
7893 FieldSet {
7894 name: "EgrGp16",
7895 extends: Some(
7896 "EGR_CORE",
7897 ),
7898 description: Some(
7899 "event generation register",
7900 ),
7901 bit_size: 32,
7902 fields: &[
7903 Field {
7904 name: "ug",
7905 description: Some(
7906 "Update generation",
7907 ),
7908 bit_offset: BitOffset::Regular(
7909 RegularBitOffset {
7910 offset: 0,
7911 },
7912 ),
7913 bit_size: 1,
7914 array: None,
7915 enumm: None,
7916 },
7917 Field {
7918 name: "ccg",
7919 description: Some(
7920 "Capture/compare x (x=1-4) generation",
7921 ),
7922 bit_offset: BitOffset::Regular(
7923 RegularBitOffset {
7924 offset: 1,
7925 },
7926 ),
7927 bit_size: 1,
7928 array: Some(
7929 Array::Regular(
7930 RegularArray {
7931 len: 4,
7932 stride: 1,
7933 },
7934 ),
7935 ),
7936 enumm: None,
7937 },
7938 Field {
7939 name: "tg",
7940 description: Some(
7941 "Trigger generation",
7942 ),
7943 bit_offset: BitOffset::Regular(
7944 RegularBitOffset {
7945 offset: 6,
7946 },
7947 ),
7948 bit_size: 1,
7949 array: None,
7950 enumm: None,
7951 },
7952 ],
7953 },
7954 FieldSet {
7955 name: "Rcr1chCmp",
7956 extends: None,
7957 description: Some(
7958 "repetition counter register",
7959 ),
7960 bit_size: 32,
7961 fields: &[
7962 Field {
7963 name: "rep",
7964 description: Some(
7965 "Repetition counter value",
7966 ),
7967 bit_offset: BitOffset::Regular(
7968 RegularBitOffset {
7969 offset: 0,
7970 },
7971 ),
7972 bit_size: 8,
7973 array: None,
7974 enumm: None,
7975 },
7976 ],
7977 },
7978 FieldSet {
7979 name: "RcrAdv",
7980 extends: None,
7981 description: Some(
7982 "repetition counter register",
7983 ),
7984 bit_size: 32,
7985 fields: &[
7986 Field {
7987 name: "rep",
7988 description: Some(
7989 "Repetition counter value",
7990 ),
7991 bit_offset: BitOffset::Regular(
7992 RegularBitOffset {
7993 offset: 0,
7994 },
7995 ),
7996 bit_size: 16,
7997 array: None,
7998 enumm: None,
7999 },
8000 ],
8001 },
8002 FieldSet {
8003 name: "Smcr2ch",
8004 extends: None,
8005 description: Some(
8006 "slave mode control register",
8007 ),
8008 bit_size: 32,
8009 fields: &[
8010 Field {
8011 name: "sms",
8012 description: Some(
8013 "Slave mode selection",
8014 ),
8015 bit_offset: BitOffset::Cursed(
8016 CursedBitOffset {
8017 ranges: &[
8018 0..=2,
8019 16..=16,
8020 ],
8021 },
8022 ),
8023 bit_size: 4,
8024 array: None,
8025 enumm: Some(
8026 "Sms",
8027 ),
8028 },
8029 Field {
8030 name: "ts",
8031 description: Some(
8032 "Trigger selection",
8033 ),
8034 bit_offset: BitOffset::Cursed(
8035 CursedBitOffset {
8036 ranges: &[
8037 4..=6,
8038 20..=21,
8039 ],
8040 },
8041 ),
8042 bit_size: 5,
8043 array: None,
8044 enumm: Some(
8045 "Ts",
8046 ),
8047 },
8048 Field {
8049 name: "msm",
8050 description: Some(
8051 "Master/Slave mode",
8052 ),
8053 bit_offset: BitOffset::Regular(
8054 RegularBitOffset {
8055 offset: 7,
8056 },
8057 ),
8058 bit_size: 1,
8059 array: None,
8060 enumm: Some(
8061 "Msm",
8062 ),
8063 },
8064 ],
8065 },
8066 FieldSet {
8067 name: "Smcr2chCmp",
8068 extends: Some(
8069 "SMCR_2CH",
8070 ),
8071 description: Some(
8072 "slave mode control register",
8073 ),
8074 bit_size: 32,
8075 fields: &[
8076 Field {
8077 name: "sms",
8078 description: Some(
8079 "Slave mode selection",
8080 ),
8081 bit_offset: BitOffset::Cursed(
8082 CursedBitOffset {
8083 ranges: &[
8084 0..=2,
8085 16..=16,
8086 ],
8087 },
8088 ),
8089 bit_size: 4,
8090 array: None,
8091 enumm: Some(
8092 "Sms",
8093 ),
8094 },
8095 Field {
8096 name: "ts",
8097 description: Some(
8098 "Trigger selection",
8099 ),
8100 bit_offset: BitOffset::Cursed(
8101 CursedBitOffset {
8102 ranges: &[
8103 4..=6,
8104 20..=21,
8105 ],
8106 },
8107 ),
8108 bit_size: 5,
8109 array: None,
8110 enumm: Some(
8111 "Ts",
8112 ),
8113 },
8114 Field {
8115 name: "msm",
8116 description: Some(
8117 "Master/Slave mode",
8118 ),
8119 bit_offset: BitOffset::Regular(
8120 RegularBitOffset {
8121 offset: 7,
8122 },
8123 ),
8124 bit_size: 1,
8125 array: None,
8126 enumm: Some(
8127 "Msm",
8128 ),
8129 },
8130 Field {
8131 name: "smspe",
8132 description: Some(
8133 "SMS preload enable",
8134 ),
8135 bit_offset: BitOffset::Regular(
8136 RegularBitOffset {
8137 offset: 24,
8138 },
8139 ),
8140 bit_size: 1,
8141 array: None,
8142 enumm: None,
8143 },
8144 ],
8145 },
8146 FieldSet {
8147 name: "SmcrAdv",
8148 extends: Some(
8149 "SMCR_2CH_CMP",
8150 ),
8151 description: Some(
8152 "slave mode control register",
8153 ),
8154 bit_size: 32,
8155 fields: &[
8156 Field {
8157 name: "sms",
8158 description: Some(
8159 "Slave mode selection",
8160 ),
8161 bit_offset: BitOffset::Cursed(
8162 CursedBitOffset {
8163 ranges: &[
8164 0..=2,
8165 16..=16,
8166 ],
8167 },
8168 ),
8169 bit_size: 4,
8170 array: None,
8171 enumm: Some(
8172 "Sms",
8173 ),
8174 },
8175 Field {
8176 name: "occs",
8177 description: Some(
8178 "OCREF clear selection",
8179 ),
8180 bit_offset: BitOffset::Regular(
8181 RegularBitOffset {
8182 offset: 3,
8183 },
8184 ),
8185 bit_size: 1,
8186 array: None,
8187 enumm: Some(
8188 "Occs",
8189 ),
8190 },
8191 Field {
8192 name: "ts",
8193 description: Some(
8194 "Trigger selection",
8195 ),
8196 bit_offset: BitOffset::Cursed(
8197 CursedBitOffset {
8198 ranges: &[
8199 4..=6,
8200 20..=21,
8201 ],
8202 },
8203 ),
8204 bit_size: 5,
8205 array: None,
8206 enumm: Some(
8207 "Ts",
8208 ),
8209 },
8210 Field {
8211 name: "msm",
8212 description: Some(
8213 "Master/Slave mode",
8214 ),
8215 bit_offset: BitOffset::Regular(
8216 RegularBitOffset {
8217 offset: 7,
8218 },
8219 ),
8220 bit_size: 1,
8221 array: None,
8222 enumm: Some(
8223 "Msm",
8224 ),
8225 },
8226 Field {
8227 name: "etf",
8228 description: Some(
8229 "External trigger filter",
8230 ),
8231 bit_offset: BitOffset::Regular(
8232 RegularBitOffset {
8233 offset: 8,
8234 },
8235 ),
8236 bit_size: 4,
8237 array: None,
8238 enumm: Some(
8239 "FilterValue",
8240 ),
8241 },
8242 Field {
8243 name: "etps",
8244 description: Some(
8245 "External trigger prescaler",
8246 ),
8247 bit_offset: BitOffset::Regular(
8248 RegularBitOffset {
8249 offset: 12,
8250 },
8251 ),
8252 bit_size: 2,
8253 array: None,
8254 enumm: Some(
8255 "Etps",
8256 ),
8257 },
8258 Field {
8259 name: "ece",
8260 description: Some(
8261 "External clock mode 2 enable",
8262 ),
8263 bit_offset: BitOffset::Regular(
8264 RegularBitOffset {
8265 offset: 14,
8266 },
8267 ),
8268 bit_size: 1,
8269 array: None,
8270 enumm: None,
8271 },
8272 Field {
8273 name: "etp",
8274 description: Some(
8275 "External trigger polarity",
8276 ),
8277 bit_offset: BitOffset::Regular(
8278 RegularBitOffset {
8279 offset: 15,
8280 },
8281 ),
8282 bit_size: 1,
8283 array: None,
8284 enumm: Some(
8285 "Etp",
8286 ),
8287 },
8288 Field {
8289 name: "smspe",
8290 description: Some(
8291 "SMS preload enable",
8292 ),
8293 bit_offset: BitOffset::Regular(
8294 RegularBitOffset {
8295 offset: 24,
8296 },
8297 ),
8298 bit_size: 1,
8299 array: None,
8300 enumm: None,
8301 },
8302 Field {
8303 name: "smsps",
8304 description: Some(
8305 "SMS preload source",
8306 ),
8307 bit_offset: BitOffset::Regular(
8308 RegularBitOffset {
8309 offset: 25,
8310 },
8311 ),
8312 bit_size: 1,
8313 array: None,
8314 enumm: Some(
8315 "Smsps",
8316 ),
8317 },
8318 ],
8319 },
8320 FieldSet {
8321 name: "SmcrGp16",
8322 extends: Some(
8323 "SMCR_2CH",
8324 ),
8325 description: Some(
8326 "slave mode control register",
8327 ),
8328 bit_size: 32,
8329 fields: &[
8330 Field {
8331 name: "sms",
8332 description: Some(
8333 "Slave mode selection",
8334 ),
8335 bit_offset: BitOffset::Cursed(
8336 CursedBitOffset {
8337 ranges: &[
8338 0..=2,
8339 16..=16,
8340 ],
8341 },
8342 ),
8343 bit_size: 4,
8344 array: None,
8345 enumm: Some(
8346 "Sms",
8347 ),
8348 },
8349 Field {
8350 name: "ts",
8351 description: Some(
8352 "Trigger selection",
8353 ),
8354 bit_offset: BitOffset::Cursed(
8355 CursedBitOffset {
8356 ranges: &[
8357 4..=6,
8358 20..=21,
8359 ],
8360 },
8361 ),
8362 bit_size: 5,
8363 array: None,
8364 enumm: Some(
8365 "Ts",
8366 ),
8367 },
8368 Field {
8369 name: "msm",
8370 description: Some(
8371 "Master/Slave mode",
8372 ),
8373 bit_offset: BitOffset::Regular(
8374 RegularBitOffset {
8375 offset: 7,
8376 },
8377 ),
8378 bit_size: 1,
8379 array: None,
8380 enumm: Some(
8381 "Msm",
8382 ),
8383 },
8384 Field {
8385 name: "etf",
8386 description: Some(
8387 "External trigger filter",
8388 ),
8389 bit_offset: BitOffset::Regular(
8390 RegularBitOffset {
8391 offset: 8,
8392 },
8393 ),
8394 bit_size: 4,
8395 array: None,
8396 enumm: Some(
8397 "FilterValue",
8398 ),
8399 },
8400 Field {
8401 name: "etps",
8402 description: Some(
8403 "External trigger prescaler",
8404 ),
8405 bit_offset: BitOffset::Regular(
8406 RegularBitOffset {
8407 offset: 12,
8408 },
8409 ),
8410 bit_size: 2,
8411 array: None,
8412 enumm: Some(
8413 "Etps",
8414 ),
8415 },
8416 Field {
8417 name: "ece",
8418 description: Some(
8419 "External clock mode 2 enable",
8420 ),
8421 bit_offset: BitOffset::Regular(
8422 RegularBitOffset {
8423 offset: 14,
8424 },
8425 ),
8426 bit_size: 1,
8427 array: None,
8428 enumm: None,
8429 },
8430 Field {
8431 name: "etp",
8432 description: Some(
8433 "External trigger polarity",
8434 ),
8435 bit_offset: BitOffset::Regular(
8436 RegularBitOffset {
8437 offset: 15,
8438 },
8439 ),
8440 bit_size: 1,
8441 array: None,
8442 enumm: Some(
8443 "Etp",
8444 ),
8445 },
8446 Field {
8447 name: "smspe",
8448 description: Some(
8449 "SMS preload enable",
8450 ),
8451 bit_offset: BitOffset::Regular(
8452 RegularBitOffset {
8453 offset: 24,
8454 },
8455 ),
8456 bit_size: 1,
8457 array: None,
8458 enumm: None,
8459 },
8460 Field {
8461 name: "smsps",
8462 description: Some(
8463 "SMS preload source",
8464 ),
8465 bit_offset: BitOffset::Regular(
8466 RegularBitOffset {
8467 offset: 25,
8468 },
8469 ),
8470 bit_size: 1,
8471 array: None,
8472 enumm: Some(
8473 "Smsps",
8474 ),
8475 },
8476 ],
8477 },
8478 FieldSet {
8479 name: "Sr1ch",
8480 extends: Some(
8481 "SR_CORE",
8482 ),
8483 description: Some(
8484 "status register",
8485 ),
8486 bit_size: 32,
8487 fields: &[
8488 Field {
8489 name: "uif",
8490 description: Some(
8491 "Update interrupt flag",
8492 ),
8493 bit_offset: BitOffset::Regular(
8494 RegularBitOffset {
8495 offset: 0,
8496 },
8497 ),
8498 bit_size: 1,
8499 array: None,
8500 enumm: None,
8501 },
8502 Field {
8503 name: "ccif",
8504 description: Some(
8505 "Capture/compare x (x=1) interrupt flag",
8506 ),
8507 bit_offset: BitOffset::Regular(
8508 RegularBitOffset {
8509 offset: 1,
8510 },
8511 ),
8512 bit_size: 1,
8513 array: Some(
8514 Array::Regular(
8515 RegularArray {
8516 len: 1,
8517 stride: 1,
8518 },
8519 ),
8520 ),
8521 enumm: None,
8522 },
8523 Field {
8524 name: "ccof",
8525 description: Some(
8526 "Capture/Compare x (x=1) overcapture flag",
8527 ),
8528 bit_offset: BitOffset::Regular(
8529 RegularBitOffset {
8530 offset: 9,
8531 },
8532 ),
8533 bit_size: 1,
8534 array: Some(
8535 Array::Regular(
8536 RegularArray {
8537 len: 1,
8538 stride: 1,
8539 },
8540 ),
8541 ),
8542 enumm: None,
8543 },
8544 ],
8545 },
8546 FieldSet {
8547 name: "Sr1chCmp",
8548 extends: Some(
8549 "SR_1CH",
8550 ),
8551 description: Some(
8552 "status register",
8553 ),
8554 bit_size: 32,
8555 fields: &[
8556 Field {
8557 name: "uif",
8558 description: Some(
8559 "Update interrupt flag",
8560 ),
8561 bit_offset: BitOffset::Regular(
8562 RegularBitOffset {
8563 offset: 0,
8564 },
8565 ),
8566 bit_size: 1,
8567 array: None,
8568 enumm: None,
8569 },
8570 Field {
8571 name: "ccif",
8572 description: Some(
8573 "Capture/compare x (x=1) interrupt flag",
8574 ),
8575 bit_offset: BitOffset::Regular(
8576 RegularBitOffset {
8577 offset: 1,
8578 },
8579 ),
8580 bit_size: 1,
8581 array: Some(
8582 Array::Regular(
8583 RegularArray {
8584 len: 1,
8585 stride: 1,
8586 },
8587 ),
8588 ),
8589 enumm: None,
8590 },
8591 Field {
8592 name: "comif",
8593 description: Some(
8594 "COM interrupt flag",
8595 ),
8596 bit_offset: BitOffset::Regular(
8597 RegularBitOffset {
8598 offset: 5,
8599 },
8600 ),
8601 bit_size: 1,
8602 array: None,
8603 enumm: None,
8604 },
8605 Field {
8606 name: "bif",
8607 description: Some(
8608 "Break x (x=1) interrupt flag",
8609 ),
8610 bit_offset: BitOffset::Regular(
8611 RegularBitOffset {
8612 offset: 7,
8613 },
8614 ),
8615 bit_size: 1,
8616 array: Some(
8617 Array::Regular(
8618 RegularArray {
8619 len: 1,
8620 stride: 1,
8621 },
8622 ),
8623 ),
8624 enumm: None,
8625 },
8626 Field {
8627 name: "ccof",
8628 description: Some(
8629 "Capture/Compare x (x=1) overcapture flag",
8630 ),
8631 bit_offset: BitOffset::Regular(
8632 RegularBitOffset {
8633 offset: 9,
8634 },
8635 ),
8636 bit_size: 1,
8637 array: Some(
8638 Array::Regular(
8639 RegularArray {
8640 len: 1,
8641 stride: 1,
8642 },
8643 ),
8644 ),
8645 enumm: None,
8646 },
8647 ],
8648 },
8649 FieldSet {
8650 name: "Sr2ch",
8651 extends: Some(
8652 "SR_1CH",
8653 ),
8654 description: Some(
8655 "status register",
8656 ),
8657 bit_size: 32,
8658 fields: &[
8659 Field {
8660 name: "uif",
8661 description: Some(
8662 "Update interrupt flag",
8663 ),
8664 bit_offset: BitOffset::Regular(
8665 RegularBitOffset {
8666 offset: 0,
8667 },
8668 ),
8669 bit_size: 1,
8670 array: None,
8671 enumm: None,
8672 },
8673 Field {
8674 name: "ccif",
8675 description: Some(
8676 "Capture/compare x (x=1-2) interrupt flag",
8677 ),
8678 bit_offset: BitOffset::Regular(
8679 RegularBitOffset {
8680 offset: 1,
8681 },
8682 ),
8683 bit_size: 1,
8684 array: Some(
8685 Array::Regular(
8686 RegularArray {
8687 len: 2,
8688 stride: 1,
8689 },
8690 ),
8691 ),
8692 enumm: None,
8693 },
8694 Field {
8695 name: "tif",
8696 description: Some(
8697 "Trigger interrupt flag",
8698 ),
8699 bit_offset: BitOffset::Regular(
8700 RegularBitOffset {
8701 offset: 6,
8702 },
8703 ),
8704 bit_size: 1,
8705 array: None,
8706 enumm: None,
8707 },
8708 Field {
8709 name: "ccof",
8710 description: Some(
8711 "Capture/Compare x (x=1-2) overcapture flag",
8712 ),
8713 bit_offset: BitOffset::Regular(
8714 RegularBitOffset {
8715 offset: 9,
8716 },
8717 ),
8718 bit_size: 1,
8719 array: Some(
8720 Array::Regular(
8721 RegularArray {
8722 len: 2,
8723 stride: 1,
8724 },
8725 ),
8726 ),
8727 enumm: None,
8728 },
8729 ],
8730 },
8731 FieldSet {
8732 name: "Sr2chCmp",
8733 extends: Some(
8734 "SR_1CH_CMP",
8735 ),
8736 description: Some(
8737 "status register",
8738 ),
8739 bit_size: 32,
8740 fields: &[
8741 Field {
8742 name: "uif",
8743 description: Some(
8744 "Update interrupt flag",
8745 ),
8746 bit_offset: BitOffset::Regular(
8747 RegularBitOffset {
8748 offset: 0,
8749 },
8750 ),
8751 bit_size: 1,
8752 array: None,
8753 enumm: None,
8754 },
8755 Field {
8756 name: "ccif",
8757 description: Some(
8758 "Capture/compare x (x=1,2) interrupt flag",
8759 ),
8760 bit_offset: BitOffset::Regular(
8761 RegularBitOffset {
8762 offset: 1,
8763 },
8764 ),
8765 bit_size: 1,
8766 array: Some(
8767 Array::Regular(
8768 RegularArray {
8769 len: 2,
8770 stride: 1,
8771 },
8772 ),
8773 ),
8774 enumm: None,
8775 },
8776 Field {
8777 name: "comif",
8778 description: Some(
8779 "COM interrupt flag",
8780 ),
8781 bit_offset: BitOffset::Regular(
8782 RegularBitOffset {
8783 offset: 5,
8784 },
8785 ),
8786 bit_size: 1,
8787 array: None,
8788 enumm: None,
8789 },
8790 Field {
8791 name: "tif",
8792 description: Some(
8793 "Trigger interrupt flag",
8794 ),
8795 bit_offset: BitOffset::Regular(
8796 RegularBitOffset {
8797 offset: 6,
8798 },
8799 ),
8800 bit_size: 1,
8801 array: None,
8802 enumm: None,
8803 },
8804 Field {
8805 name: "bif",
8806 description: Some(
8807 "Break x (x=1) interrupt flag",
8808 ),
8809 bit_offset: BitOffset::Regular(
8810 RegularBitOffset {
8811 offset: 7,
8812 },
8813 ),
8814 bit_size: 1,
8815 array: Some(
8816 Array::Regular(
8817 RegularArray {
8818 len: 1,
8819 stride: 1,
8820 },
8821 ),
8822 ),
8823 enumm: None,
8824 },
8825 Field {
8826 name: "ccof",
8827 description: Some(
8828 "Capture/Compare x (x=1,2) overcapture flag",
8829 ),
8830 bit_offset: BitOffset::Regular(
8831 RegularBitOffset {
8832 offset: 9,
8833 },
8834 ),
8835 bit_size: 1,
8836 array: Some(
8837 Array::Regular(
8838 RegularArray {
8839 len: 2,
8840 stride: 1,
8841 },
8842 ),
8843 ),
8844 enumm: None,
8845 },
8846 ],
8847 },
8848 FieldSet {
8849 name: "SrAdv",
8850 extends: Some(
8851 "SR_2CH_CMP",
8852 ),
8853 description: Some(
8854 "status register",
8855 ),
8856 bit_size: 32,
8857 fields: &[
8858 Field {
8859 name: "uif",
8860 description: Some(
8861 "Update interrupt flag",
8862 ),
8863 bit_offset: BitOffset::Regular(
8864 RegularBitOffset {
8865 offset: 0,
8866 },
8867 ),
8868 bit_size: 1,
8869 array: None,
8870 enumm: None,
8871 },
8872 Field {
8873 name: "ccif",
8874 description: Some(
8875 "Capture/compare x (x=1-4) interrupt flag",
8876 ),
8877 bit_offset: BitOffset::Regular(
8878 RegularBitOffset {
8879 offset: 1,
8880 },
8881 ),
8882 bit_size: 1,
8883 array: Some(
8884 Array::Regular(
8885 RegularArray {
8886 len: 4,
8887 stride: 1,
8888 },
8889 ),
8890 ),
8891 enumm: None,
8892 },
8893 Field {
8894 name: "comif",
8895 description: Some(
8896 "COM interrupt flag",
8897 ),
8898 bit_offset: BitOffset::Regular(
8899 RegularBitOffset {
8900 offset: 5,
8901 },
8902 ),
8903 bit_size: 1,
8904 array: None,
8905 enumm: None,
8906 },
8907 Field {
8908 name: "tif",
8909 description: Some(
8910 "Trigger interrupt flag",
8911 ),
8912 bit_offset: BitOffset::Regular(
8913 RegularBitOffset {
8914 offset: 6,
8915 },
8916 ),
8917 bit_size: 1,
8918 array: None,
8919 enumm: None,
8920 },
8921 Field {
8922 name: "bif",
8923 description: Some(
8924 "Break x (x=1,2) interrupt flag",
8925 ),
8926 bit_offset: BitOffset::Regular(
8927 RegularBitOffset {
8928 offset: 7,
8929 },
8930 ),
8931 bit_size: 1,
8932 array: Some(
8933 Array::Regular(
8934 RegularArray {
8935 len: 2,
8936 stride: 1,
8937 },
8938 ),
8939 ),
8940 enumm: None,
8941 },
8942 Field {
8943 name: "ccof",
8944 description: Some(
8945 "Capture/Compare x (x=1-4) overcapture flag",
8946 ),
8947 bit_offset: BitOffset::Regular(
8948 RegularBitOffset {
8949 offset: 9,
8950 },
8951 ),
8952 bit_size: 1,
8953 array: Some(
8954 Array::Regular(
8955 RegularArray {
8956 len: 4,
8957 stride: 1,
8958 },
8959 ),
8960 ),
8961 enumm: None,
8962 },
8963 Field {
8964 name: "sbif",
8965 description: Some(
8966 "System break interrupt flag",
8967 ),
8968 bit_offset: BitOffset::Regular(
8969 RegularBitOffset {
8970 offset: 13,
8971 },
8972 ),
8973 bit_size: 1,
8974 array: None,
8975 enumm: None,
8976 },
8977 Field {
8978 name: "ccif5",
8979 description: Some(
8980 "Capture/compare 5 interrupt flag",
8981 ),
8982 bit_offset: BitOffset::Regular(
8983 RegularBitOffset {
8984 offset: 16,
8985 },
8986 ),
8987 bit_size: 1,
8988 array: None,
8989 enumm: None,
8990 },
8991 Field {
8992 name: "ccif6",
8993 description: Some(
8994 "Capture/compare 6 interrupt flag",
8995 ),
8996 bit_offset: BitOffset::Regular(
8997 RegularBitOffset {
8998 offset: 17,
8999 },
9000 ),
9001 bit_size: 1,
9002 array: None,
9003 enumm: None,
9004 },
9005 Field {
9006 name: "idxif",
9007 description: Some(
9008 "Index interrupt flag",
9009 ),
9010 bit_offset: BitOffset::Regular(
9011 RegularBitOffset {
9012 offset: 20,
9013 },
9014 ),
9015 bit_size: 1,
9016 array: None,
9017 enumm: None,
9018 },
9019 Field {
9020 name: "dirif",
9021 description: Some(
9022 "Direction change interrupt flag",
9023 ),
9024 bit_offset: BitOffset::Regular(
9025 RegularBitOffset {
9026 offset: 21,
9027 },
9028 ),
9029 bit_size: 1,
9030 array: None,
9031 enumm: None,
9032 },
9033 Field {
9034 name: "ierrif",
9035 description: Some(
9036 "Index error interrupt flag",
9037 ),
9038 bit_offset: BitOffset::Regular(
9039 RegularBitOffset {
9040 offset: 22,
9041 },
9042 ),
9043 bit_size: 1,
9044 array: None,
9045 enumm: None,
9046 },
9047 Field {
9048 name: "terrif",
9049 description: Some(
9050 "Transition error interrupt flag",
9051 ),
9052 bit_offset: BitOffset::Regular(
9053 RegularBitOffset {
9054 offset: 23,
9055 },
9056 ),
9057 bit_size: 1,
9058 array: None,
9059 enumm: None,
9060 },
9061 ],
9062 },
9063 FieldSet {
9064 name: "SrCore",
9065 extends: None,
9066 description: Some(
9067 "status register",
9068 ),
9069 bit_size: 32,
9070 fields: &[
9071 Field {
9072 name: "uif",
9073 description: Some(
9074 "Update interrupt flag",
9075 ),
9076 bit_offset: BitOffset::Regular(
9077 RegularBitOffset {
9078 offset: 0,
9079 },
9080 ),
9081 bit_size: 1,
9082 array: None,
9083 enumm: None,
9084 },
9085 ],
9086 },
9087 FieldSet {
9088 name: "SrGp16",
9089 extends: Some(
9090 "SR_CORE",
9091 ),
9092 description: Some(
9093 "status register",
9094 ),
9095 bit_size: 32,
9096 fields: &[
9097 Field {
9098 name: "uif",
9099 description: Some(
9100 "Update interrupt flag",
9101 ),
9102 bit_offset: BitOffset::Regular(
9103 RegularBitOffset {
9104 offset: 0,
9105 },
9106 ),
9107 bit_size: 1,
9108 array: None,
9109 enumm: None,
9110 },
9111 Field {
9112 name: "ccif",
9113 description: Some(
9114 "Capture/compare x (x=1-4) interrupt flag",
9115 ),
9116 bit_offset: BitOffset::Regular(
9117 RegularBitOffset {
9118 offset: 1,
9119 },
9120 ),
9121 bit_size: 1,
9122 array: Some(
9123 Array::Regular(
9124 RegularArray {
9125 len: 4,
9126 stride: 1,
9127 },
9128 ),
9129 ),
9130 enumm: None,
9131 },
9132 Field {
9133 name: "tif",
9134 description: Some(
9135 "Trigger interrupt flag",
9136 ),
9137 bit_offset: BitOffset::Regular(
9138 RegularBitOffset {
9139 offset: 6,
9140 },
9141 ),
9142 bit_size: 1,
9143 array: None,
9144 enumm: None,
9145 },
9146 Field {
9147 name: "ccof",
9148 description: Some(
9149 "Capture/Compare x (x=1-4) overcapture flag",
9150 ),
9151 bit_offset: BitOffset::Regular(
9152 RegularBitOffset {
9153 offset: 9,
9154 },
9155 ),
9156 bit_size: 1,
9157 array: Some(
9158 Array::Regular(
9159 RegularArray {
9160 len: 4,
9161 stride: 1,
9162 },
9163 ),
9164 ),
9165 enumm: None,
9166 },
9167 Field {
9168 name: "idxif",
9169 description: Some(
9170 "Index interrupt flag",
9171 ),
9172 bit_offset: BitOffset::Regular(
9173 RegularBitOffset {
9174 offset: 20,
9175 },
9176 ),
9177 bit_size: 1,
9178 array: None,
9179 enumm: None,
9180 },
9181 Field {
9182 name: "dirif",
9183 description: Some(
9184 "Direction change interrupt flag",
9185 ),
9186 bit_offset: BitOffset::Regular(
9187 RegularBitOffset {
9188 offset: 21,
9189 },
9190 ),
9191 bit_size: 1,
9192 array: None,
9193 enumm: None,
9194 },
9195 Field {
9196 name: "ierrif",
9197 description: Some(
9198 "Index error interrupt flag",
9199 ),
9200 bit_offset: BitOffset::Regular(
9201 RegularBitOffset {
9202 offset: 22,
9203 },
9204 ),
9205 bit_size: 1,
9206 array: None,
9207 enumm: None,
9208 },
9209 Field {
9210 name: "terrif",
9211 description: Some(
9212 "Transition error interrupt flag",
9213 ),
9214 bit_offset: BitOffset::Regular(
9215 RegularBitOffset {
9216 offset: 23,
9217 },
9218 ),
9219 bit_size: 1,
9220 array: None,
9221 enumm: None,
9222 },
9223 ],
9224 },
9225 FieldSet {
9226 name: "Tisel1ch",
9227 extends: None,
9228 description: Some(
9229 "input selection register",
9230 ),
9231 bit_size: 32,
9232 fields: &[
9233 Field {
9234 name: "tisel",
9235 description: Some(
9236 "Selects TIM_TIx (x=1) input",
9237 ),
9238 bit_offset: BitOffset::Regular(
9239 RegularBitOffset {
9240 offset: 0,
9241 },
9242 ),
9243 bit_size: 4,
9244 array: Some(
9245 Array::Regular(
9246 RegularArray {
9247 len: 1,
9248 stride: 8,
9249 },
9250 ),
9251 ),
9252 enumm: None,
9253 },
9254 ],
9255 },
9256 FieldSet {
9257 name: "Tisel2ch",
9258 extends: Some(
9259 "TISEL_1CH",
9260 ),
9261 description: Some(
9262 "input selection register",
9263 ),
9264 bit_size: 32,
9265 fields: &[
9266 Field {
9267 name: "tisel",
9268 description: Some(
9269 "Selects TIM_TIx (x=1-2) input",
9270 ),
9271 bit_offset: BitOffset::Regular(
9272 RegularBitOffset {
9273 offset: 0,
9274 },
9275 ),
9276 bit_size: 4,
9277 array: Some(
9278 Array::Regular(
9279 RegularArray {
9280 len: 2,
9281 stride: 8,
9282 },
9283 ),
9284 ),
9285 enumm: None,
9286 },
9287 ],
9288 },
9289 FieldSet {
9290 name: "TiselGp16",
9291 extends: None,
9292 description: Some(
9293 "input selection register",
9294 ),
9295 bit_size: 32,
9296 fields: &[
9297 Field {
9298 name: "tisel",
9299 description: Some(
9300 "Selects TIM_TIx (x=1-4) input",
9301 ),
9302 bit_offset: BitOffset::Regular(
9303 RegularBitOffset {
9304 offset: 0,
9305 },
9306 ),
9307 bit_size: 4,
9308 array: Some(
9309 Array::Regular(
9310 RegularArray {
9311 len: 4,
9312 stride: 8,
9313 },
9314 ),
9315 ),
9316 enumm: None,
9317 },
9318 ],
9319 },
9320 ],
9321 enums: &[
9322 Enum {
9323 name: "Bkbid",
9324 description: None,
9325 bit_size: 1,
9326 variants: &[
9327 EnumVariant {
9328 name: "INPUT",
9329 description: Some(
9330 "Break input tim_brk in input mode",
9331 ),
9332 value: 0,
9333 },
9334 EnumVariant {
9335 name: "BIDIRECTIONAL",
9336 description: Some(
9337 "Break input tim_brk in bidirectional mode",
9338 ),
9339 value: 1,
9340 },
9341 ],
9342 },
9343 Enum {
9344 name: "Bkdsrm",
9345 description: None,
9346 bit_size: 1,
9347 variants: &[
9348 EnumVariant {
9349 name: "ARMED",
9350 description: Some(
9351 "Break input tim_brk is armed",
9352 ),
9353 value: 0,
9354 },
9355 EnumVariant {
9356 name: "DISARMED",
9357 description: Some(
9358 "Break input tim_brk is disarmed",
9359 ),
9360 value: 1,
9361 },
9362 ],
9363 },
9364 Enum {
9365 name: "Bkinp",
9366 description: None,
9367 bit_size: 1,
9368 variants: &[
9369 EnumVariant {
9370 name: "NOT_INVERTED",
9371 description: Some(
9372 "input polarity is not inverted (active low if BKxP = 0, active high if BKxP = 1)",
9373 ),
9374 value: 0,
9375 },
9376 EnumVariant {
9377 name: "INVERTED",
9378 description: Some(
9379 "input polarity is inverted (active high if BKxP = 0, active low if BKxP = 1)",
9380 ),
9381 value: 1,
9382 },
9383 ],
9384 },
9385 Enum {
9386 name: "Bkp",
9387 description: None,
9388 bit_size: 1,
9389 variants: &[
9390 EnumVariant {
9391 name: "ACTIVE_LOW",
9392 description: Some(
9393 "Break input tim_brk is active low",
9394 ),
9395 value: 0,
9396 },
9397 EnumVariant {
9398 name: "ACTIVE_HIGH",
9399 description: Some(
9400 "Break input tim_brk is active high",
9401 ),
9402 value: 1,
9403 },
9404 ],
9405 },
9406 Enum {
9407 name: "Ccds",
9408 description: None,
9409 bit_size: 1,
9410 variants: &[
9411 EnumVariant {
9412 name: "ON_COMPARE",
9413 description: Some(
9414 "CCx DMA request sent when CCx event occurs",
9415 ),
9416 value: 0,
9417 },
9418 EnumVariant {
9419 name: "ON_UPDATE",
9420 description: Some(
9421 "CCx DMA request sent when update event occurs",
9422 ),
9423 value: 1,
9424 },
9425 ],
9426 },
9427 Enum {
9428 name: "CcmrInputCcs",
9429 description: None,
9430 bit_size: 2,
9431 variants: &[
9432 EnumVariant {
9433 name: "TI4",
9434 description: Some(
9435 "CCx channel is configured as input, normal mapping: ICx mapped to TIx",
9436 ),
9437 value: 1,
9438 },
9439 EnumVariant {
9440 name: "TI3",
9441 description: Some(
9442 "CCx channel is configured as input, alternate mapping (switches 1 with 2, 3 with 4)",
9443 ),
9444 value: 2,
9445 },
9446 EnumVariant {
9447 name: "TRC",
9448 description: Some(
9449 "CCx channel is configured as input, ICx is mapped on TRC",
9450 ),
9451 value: 3,
9452 },
9453 ],
9454 },
9455 Enum {
9456 name: "CcmrOutputCcs",
9457 description: None,
9458 bit_size: 2,
9459 variants: &[
9460 EnumVariant {
9461 name: "OUTPUT",
9462 description: Some(
9463 "CCx channel is configured as output",
9464 ),
9465 value: 0,
9466 },
9467 ],
9468 },
9469 Enum {
9470 name: "Ckd",
9471 description: None,
9472 bit_size: 2,
9473 variants: &[
9474 EnumVariant {
9475 name: "DIV1",
9476 description: Some(
9477 "t_DTS = t_CK_INT",
9478 ),
9479 value: 0,
9480 },
9481 EnumVariant {
9482 name: "DIV2",
9483 description: Some(
9484 "t_DTS = 2 × t_CK_INT",
9485 ),
9486 value: 1,
9487 },
9488 EnumVariant {
9489 name: "DIV4",
9490 description: Some(
9491 "t_DTS = 4 × t_CK_INT",
9492 ),
9493 value: 2,
9494 },
9495 ],
9496 },
9497 Enum {
9498 name: "Cms",
9499 description: None,
9500 bit_size: 2,
9501 variants: &[
9502 EnumVariant {
9503 name: "EDGE_ALIGNED",
9504 description: Some(
9505 "The counter counts up or down depending on the direction bit",
9506 ),
9507 value: 0,
9508 },
9509 EnumVariant {
9510 name: "CENTER_ALIGNED1",
9511 description: Some(
9512 "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting down.",
9513 ),
9514 value: 1,
9515 },
9516 EnumVariant {
9517 name: "CENTER_ALIGNED2",
9518 description: Some(
9519 "The counter counts up and down alternatively. Output compare interrupt flags are set only when the counter is counting up.",
9520 ),
9521 value: 2,
9522 },
9523 EnumVariant {
9524 name: "CENTER_ALIGNED3",
9525 description: Some(
9526 "The counter counts up and down alternatively. Output compare interrupt flags are set both when the counter is counting up or down.",
9527 ),
9528 value: 3,
9529 },
9530 ],
9531 },
9532 Enum {
9533 name: "Dbss",
9534 description: None,
9535 bit_size: 4,
9536 variants: &[
9537 EnumVariant {
9538 name: "UPDATE",
9539 description: Some(
9540 "Update",
9541 ),
9542 value: 1,
9543 },
9544 EnumVariant {
9545 name: "CC1",
9546 description: Some(
9547 "CC1",
9548 ),
9549 value: 2,
9550 },
9551 EnumVariant {
9552 name: "CC2",
9553 description: Some(
9554 "CC2",
9555 ),
9556 value: 3,
9557 },
9558 EnumVariant {
9559 name: "CC3",
9560 description: Some(
9561 "CC3",
9562 ),
9563 value: 4,
9564 },
9565 EnumVariant {
9566 name: "CC4",
9567 description: Some(
9568 "CC4",
9569 ),
9570 value: 5,
9571 },
9572 EnumVariant {
9573 name: "COM",
9574 description: Some(
9575 "COM",
9576 ),
9577 value: 6,
9578 },
9579 EnumVariant {
9580 name: "TRIGGER",
9581 description: Some(
9582 "Trigger",
9583 ),
9584 value: 7,
9585 },
9586 ],
9587 },
9588 Enum {
9589 name: "Dir",
9590 description: None,
9591 bit_size: 1,
9592 variants: &[
9593 EnumVariant {
9594 name: "UP",
9595 description: Some(
9596 "Counter used as upcounter",
9597 ),
9598 value: 0,
9599 },
9600 EnumVariant {
9601 name: "DOWN",
9602 description: Some(
9603 "Counter used as downcounter",
9604 ),
9605 value: 1,
9606 },
9607 ],
9608 },
9609 Enum {
9610 name: "Dtae",
9611 description: None,
9612 bit_size: 1,
9613 variants: &[
9614 EnumVariant {
9615 name: "IDENTICAL",
9616 description: Some(
9617 "Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register",
9618 ),
9619 value: 0,
9620 },
9621 EnumVariant {
9622 name: "DISTINCT",
9623 description: Some(
9624 "Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits.",
9625 ),
9626 value: 1,
9627 },
9628 ],
9629 },
9630 Enum {
9631 name: "Etp",
9632 description: None,
9633 bit_size: 1,
9634 variants: &[
9635 EnumVariant {
9636 name: "NOT_INVERTED",
9637 description: Some(
9638 "ETR is noninverted, active at high level or rising edge",
9639 ),
9640 value: 0,
9641 },
9642 EnumVariant {
9643 name: "INVERTED",
9644 description: Some(
9645 "ETR is inverted, active at low level or falling edge",
9646 ),
9647 value: 1,
9648 },
9649 ],
9650 },
9651 Enum {
9652 name: "Etps",
9653 description: None,
9654 bit_size: 2,
9655 variants: &[
9656 EnumVariant {
9657 name: "DIV1",
9658 description: Some(
9659 "Prescaler OFF",
9660 ),
9661 value: 0,
9662 },
9663 EnumVariant {
9664 name: "DIV2",
9665 description: Some(
9666 "ETRP frequency divided by 2",
9667 ),
9668 value: 1,
9669 },
9670 EnumVariant {
9671 name: "DIV4",
9672 description: Some(
9673 "ETRP frequency divided by 4",
9674 ),
9675 value: 2,
9676 },
9677 EnumVariant {
9678 name: "DIV8",
9679 description: Some(
9680 "ETRP frequency divided by 8",
9681 ),
9682 value: 3,
9683 },
9684 ],
9685 },
9686 Enum {
9687 name: "Fidx",
9688 description: None,
9689 bit_size: 1,
9690 variants: &[
9691 EnumVariant {
9692 name: "ALWAYS_ACTIVE",
9693 description: Some(
9694 "Index is always active",
9695 ),
9696 value: 0,
9697 },
9698 EnumVariant {
9699 name: "FIRST_ONLY",
9700 description: Some(
9701 "the first Index only resets the counter",
9702 ),
9703 value: 1,
9704 },
9705 ],
9706 },
9707 Enum {
9708 name: "FilterValue",
9709 description: None,
9710 bit_size: 4,
9711 variants: &[
9712 EnumVariant {
9713 name: "NO_FILTER",
9714 description: Some(
9715 "No filter, sampling is done at fDTS",
9716 ),
9717 value: 0,
9718 },
9719 EnumVariant {
9720 name: "FCK_INT_N2",
9721 description: Some(
9722 "fSAMPLING=fCK_INT, N=2",
9723 ),
9724 value: 1,
9725 },
9726 EnumVariant {
9727 name: "FCK_INT_N4",
9728 description: Some(
9729 "fSAMPLING=fCK_INT, N=4",
9730 ),
9731 value: 2,
9732 },
9733 EnumVariant {
9734 name: "FCK_INT_N8",
9735 description: Some(
9736 "fSAMPLING=fCK_INT, N=8",
9737 ),
9738 value: 3,
9739 },
9740 EnumVariant {
9741 name: "FDTS_DIV2_N6",
9742 description: Some(
9743 "fSAMPLING=fDTS/2, N=6",
9744 ),
9745 value: 4,
9746 },
9747 EnumVariant {
9748 name: "FDTS_DIV2_N8",
9749 description: Some(
9750 "fSAMPLING=fDTS/2, N=8",
9751 ),
9752 value: 5,
9753 },
9754 EnumVariant {
9755 name: "FDTS_DIV4_N6",
9756 description: Some(
9757 "fSAMPLING=fDTS/4, N=6",
9758 ),
9759 value: 6,
9760 },
9761 EnumVariant {
9762 name: "FDTS_DIV4_N8",
9763 description: Some(
9764 "fSAMPLING=fDTS/4, N=8",
9765 ),
9766 value: 7,
9767 },
9768 EnumVariant {
9769 name: "FDTS_DIV8_N6",
9770 description: Some(
9771 "fSAMPLING=fDTS/8, N=6",
9772 ),
9773 value: 8,
9774 },
9775 EnumVariant {
9776 name: "FDTS_DIV8_N8",
9777 description: Some(
9778 "fSAMPLING=fDTS/8, N=8",
9779 ),
9780 value: 9,
9781 },
9782 EnumVariant {
9783 name: "FDTS_DIV16_N5",
9784 description: Some(
9785 "fSAMPLING=fDTS/16, N=5",
9786 ),
9787 value: 10,
9788 },
9789 EnumVariant {
9790 name: "FDTS_DIV16_N6",
9791 description: Some(
9792 "fSAMPLING=fDTS/16, N=6",
9793 ),
9794 value: 11,
9795 },
9796 EnumVariant {
9797 name: "FDTS_DIV16_N8",
9798 description: Some(
9799 "fSAMPLING=fDTS/16, N=8",
9800 ),
9801 value: 12,
9802 },
9803 EnumVariant {
9804 name: "FDTS_DIV32_N5",
9805 description: Some(
9806 "fSAMPLING=fDTS/32, N=5",
9807 ),
9808 value: 13,
9809 },
9810 EnumVariant {
9811 name: "FDTS_DIV32_N6",
9812 description: Some(
9813 "fSAMPLING=fDTS/32, N=6",
9814 ),
9815 value: 14,
9816 },
9817 EnumVariant {
9818 name: "FDTS_DIV32_N8",
9819 description: Some(
9820 "fSAMPLING=fDTS/32, N=8",
9821 ),
9822 value: 15,
9823 },
9824 ],
9825 },
9826 Enum {
9827 name: "Gc5c",
9828 description: None,
9829 bit_size: 1,
9830 variants: &[
9831 EnumVariant {
9832 name: "NO_EFFECT",
9833 description: Some(
9834 "No effect of TIM_OC5REF on TIM_OCxREFC (x=1-3)",
9835 ),
9836 value: 0,
9837 },
9838 EnumVariant {
9839 name: "LOGICAL_AND",
9840 description: Some(
9841 "TIM_OCxREFC is the logical AND of TIM_OCxREF and TIM_OC5REF",
9842 ),
9843 value: 1,
9844 },
9845 ],
9846 },
9847 Enum {
9848 name: "Iblk",
9849 description: None,
9850 bit_size: 2,
9851 variants: &[
9852 EnumVariant {
9853 name: "ALWAYS_ACTIVE",
9854 description: Some(
9855 "Index always active",
9856 ),
9857 value: 0,
9858 },
9859 EnumVariant {
9860 name: "CC3P",
9861 description: Some(
9862 "Index disabled when tim_ti3 input is active, as per CC3P bitfield",
9863 ),
9864 value: 1,
9865 },
9866 EnumVariant {
9867 name: "CC4P",
9868 description: Some(
9869 "Index disabled when tim_ti4 input is active, as per CC4P bitfield",
9870 ),
9871 value: 2,
9872 },
9873 ],
9874 },
9875 Enum {
9876 name: "Idir",
9877 description: None,
9878 bit_size: 2,
9879 variants: &[
9880 EnumVariant {
9881 name: "BOTH",
9882 description: Some(
9883 "Index resets the counter whatever the direction",
9884 ),
9885 value: 0,
9886 },
9887 EnumVariant {
9888 name: "UP",
9889 description: Some(
9890 "Index resets the counter when up-counting only",
9891 ),
9892 value: 1,
9893 },
9894 EnumVariant {
9895 name: "DOWN",
9896 description: Some(
9897 "Index resets the counter when down-counting only",
9898 ),
9899 value: 2,
9900 },
9901 ],
9902 },
9903 Enum {
9904 name: "Lock",
9905 description: None,
9906 bit_size: 2,
9907 variants: &[
9908 EnumVariant {
9909 name: "DISABLED",
9910 description: Some(
9911 "No bit is write protected",
9912 ),
9913 value: 0,
9914 },
9915 EnumVariant {
9916 name: "LEVEL1",
9917 description: Some(
9918 "DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written",
9919 ),
9920 value: 1,
9921 },
9922 EnumVariant {
9923 name: "LEVEL2",
9924 description: Some(
9925 "LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.",
9926 ),
9927 value: 2,
9928 },
9929 EnumVariant {
9930 name: "LEVEL3",
9931 description: Some(
9932 "LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.",
9933 ),
9934 value: 3,
9935 },
9936 ],
9937 },
9938 Enum {
9939 name: "Mms",
9940 description: None,
9941 bit_size: 4,
9942 variants: &[
9943 EnumVariant {
9944 name: "RESET",
9945 description: Some(
9946 "The UG bit from the TIMx_EGR register is used as trigger output",
9947 ),
9948 value: 0,
9949 },
9950 EnumVariant {
9951 name: "ENABLE",
9952 description: Some(
9953 "The counter enable signal, CNT_EN, is used as trigger output",
9954 ),
9955 value: 1,
9956 },
9957 EnumVariant {
9958 name: "UPDATE",
9959 description: Some(
9960 "The update event is selected as trigger output",
9961 ),
9962 value: 2,
9963 },
9964 EnumVariant {
9965 name: "COMPARE_PULSE",
9966 description: Some(
9967 "The trigger output send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred",
9968 ),
9969 value: 3,
9970 },
9971 EnumVariant {
9972 name: "COMPARE_OC1",
9973 description: Some(
9974 "OC1REF signal is used as trigger output",
9975 ),
9976 value: 4,
9977 },
9978 EnumVariant {
9979 name: "COMPARE_OC2",
9980 description: Some(
9981 "OC2REF signal is used as trigger output",
9982 ),
9983 value: 5,
9984 },
9985 EnumVariant {
9986 name: "COMPARE_OC3",
9987 description: Some(
9988 "OC3REF signal is used as trigger output",
9989 ),
9990 value: 6,
9991 },
9992 EnumVariant {
9993 name: "COMPARE_OC4",
9994 description: Some(
9995 "OC4REF signal is used as trigger output",
9996 ),
9997 value: 7,
9998 },
9999 EnumVariant {
10000 name: "ENCODER_CLOCK_OUTPUT",
10001 description: Some(
10002 "The encoder clock signal is used as trigger output",
10003 ),
10004 value: 8,
10005 },
10006 ],
10007 },
10008 Enum {
10009 name: "Mms2",
10010 description: None,
10011 bit_size: 4,
10012 variants: &[
10013 EnumVariant {
10014 name: "RESET",
10015 description: Some(
10016 "The UG bit from the TIMx_EGR register is used as TRGO2",
10017 ),
10018 value: 0,
10019 },
10020 EnumVariant {
10021 name: "ENABLE",
10022 description: Some(
10023 "The counter enable signal, CNT_EN, is used as TRGO2",
10024 ),
10025 value: 1,
10026 },
10027 EnumVariant {
10028 name: "UPDATE",
10029 description: Some(
10030 "The update event is selected as TRGO2",
10031 ),
10032 value: 2,
10033 },
10034 EnumVariant {
10035 name: "COMPARE_PULSE",
10036 description: Some(
10037 "TRGO2 send a positive pulse when the CC1IF flag it to be set, as soon as a capture or a compare match occurred",
10038 ),
10039 value: 3,
10040 },
10041 EnumVariant {
10042 name: "COMPARE_OC1",
10043 description: Some(
10044 "OC1REF signal is used as TRGO2",
10045 ),
10046 value: 4,
10047 },
10048 EnumVariant {
10049 name: "COMPARE_OC2",
10050 description: Some(
10051 "OC2REF signal is used as TRGO2",
10052 ),
10053 value: 5,
10054 },
10055 EnumVariant {
10056 name: "COMPARE_OC3",
10057 description: Some(
10058 "OC3REF signal is used as TRGO2",
10059 ),
10060 value: 6,
10061 },
10062 EnumVariant {
10063 name: "COMPARE_OC4",
10064 description: Some(
10065 "OC4REF signal is used as TRGO2",
10066 ),
10067 value: 7,
10068 },
10069 EnumVariant {
10070 name: "COMPARE_OC5",
10071 description: Some(
10072 "OC5REF signal is used as TRGO2",
10073 ),
10074 value: 8,
10075 },
10076 EnumVariant {
10077 name: "COMPARE_OC6",
10078 description: Some(
10079 "OC6REF signal is used as TRGO2",
10080 ),
10081 value: 9,
10082 },
10083 EnumVariant {
10084 name: "COMPARE_PULSE_OC4",
10085 description: Some(
10086 "OC4REF rising or falling edges generate pulses on TRGO2",
10087 ),
10088 value: 10,
10089 },
10090 EnumVariant {
10091 name: "COMPARE_PULSE_OC6",
10092 description: Some(
10093 "OC6REF rising or falling edges generate pulses on TRGO2",
10094 ),
10095 value: 11,
10096 },
10097 EnumVariant {
10098 name: "COMPARE_PULSE_OC4_OR_OC6_RISING",
10099 description: Some(
10100 "OC4REF or OC6REF rising edges generate pulses on TRGO2",
10101 ),
10102 value: 12,
10103 },
10104 EnumVariant {
10105 name: "COMPARE_PULSE_OC4_RISING_OR_OC6_FALLING",
10106 description: Some(
10107 "OC4REF rising or OC6REF falling edges generate pulses on TRGO2",
10108 ),
10109 value: 13,
10110 },
10111 EnumVariant {
10112 name: "COMPARE_PULSE_OC5_OR_OC6_RISING",
10113 description: Some(
10114 "OC5REF or OC6REF rising edges generate pulses on TRGO2",
10115 ),
10116 value: 14,
10117 },
10118 EnumVariant {
10119 name: "COMPARE_PULSE_OC5_RISING_OR_OC6_FALLING",
10120 description: Some(
10121 "OC5REF rising or OC6REF falling edges generate pulses on TRGO2",
10122 ),
10123 value: 15,
10124 },
10125 ],
10126 },
10127 Enum {
10128 name: "Msm",
10129 description: None,
10130 bit_size: 1,
10131 variants: &[
10132 EnumVariant {
10133 name: "NO_SYNC",
10134 description: Some(
10135 "No action",
10136 ),
10137 value: 0,
10138 },
10139 EnumVariant {
10140 name: "SYNC",
10141 description: Some(
10142 "The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event.",
10143 ),
10144 value: 1,
10145 },
10146 ],
10147 },
10148 Enum {
10149 name: "Occs",
10150 description: None,
10151 bit_size: 1,
10152 variants: &[
10153 EnumVariant {
10154 name: "INPUT",
10155 description: Some(
10156 "tim_ocref_clr_int is connected to the tim_ocref_clr input",
10157 ),
10158 value: 0,
10159 },
10160 EnumVariant {
10161 name: "ETRF",
10162 description: Some(
10163 "tim_ocref_clr_int is connected to tim_etrf",
10164 ),
10165 value: 1,
10166 },
10167 ],
10168 },
10169 Enum {
10170 name: "Ocm",
10171 description: None,
10172 bit_size: 4,
10173 variants: &[
10174 EnumVariant {
10175 name: "FROZEN",
10176 description: Some(
10177 "The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs",
10178 ),
10179 value: 0,
10180 },
10181 EnumVariant {
10182 name: "ACTIVE_ON_MATCH",
10183 description: Some(
10184 "Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register",
10185 ),
10186 value: 1,
10187 },
10188 EnumVariant {
10189 name: "INACTIVE_ON_MATCH",
10190 description: Some(
10191 "Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register",
10192 ),
10193 value: 2,
10194 },
10195 EnumVariant {
10196 name: "TOGGLE",
10197 description: Some(
10198 "OCyREF toggles when TIMx_CNT=TIMx_CCRy",
10199 ),
10200 value: 3,
10201 },
10202 EnumVariant {
10203 name: "FORCE_INACTIVE",
10204 description: Some(
10205 "OCyREF is forced low",
10206 ),
10207 value: 4,
10208 },
10209 EnumVariant {
10210 name: "FORCE_ACTIVE",
10211 description: Some(
10212 "OCyREF is forced high",
10213 ),
10214 value: 5,
10215 },
10216 EnumVariant {
10217 name: "PWM_MODE1",
10218 description: Some(
10219 "In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active",
10220 ),
10221 value: 6,
10222 },
10223 EnumVariant {
10224 name: "PWM_MODE2",
10225 description: Some(
10226 "Inversely to PwmMode1",
10227 ),
10228 value: 7,
10229 },
10230 EnumVariant {
10231 name: "RETRIGERRABLE_OPM_MODE_1",
10232 description: Some(
10233 "In up-counting mode, the channel is active until a trigger\nevent is detected (on tim_trgi signal). Then, a comparison is performed as in PWM\nmode 1 and the channels becomes active again at the next update. In down-counting\nmode, the channel is inactive until a trigger event is detected (on tim_trgi signal).\nThen, a comparison is performed as in PWM mode 1 and the channels becomes\ninactive again at the next update.",
10234 ),
10235 value: 8,
10236 },
10237 EnumVariant {
10238 name: "RETRIGERRABLE_OPM_MODE_2",
10239 description: Some(
10240 "In up-counting mode, the channel is inactive until a\ntrigger event is detected (on tim_trgi signal). Then, a comparison is performed as in\nPWM mode 2 and the channels becomes inactive again at the next update. In down-\ncounting mode, the channel is active until a trigger event is detected (on tim_trgi\nsignal). Then, a comparison is performed as in PWM mode 1 and the channels\nbecomes active again at the next update.",
10241 ),
10242 value: 9,
10243 },
10244 EnumVariant {
10245 name: "_RESERVED1",
10246 description: Some(
10247 "_reserved1",
10248 ),
10249 value: 10,
10250 },
10251 EnumVariant {
10252 name: "_RESERVED2",
10253 description: Some(
10254 "_reserved2",
10255 ),
10256 value: 11,
10257 },
10258 EnumVariant {
10259 name: "COMBINED_PWM_MODE_1",
10260 description: Some(
10261 "tim_oc1ref has the same behavior as in PWM mode 1.\ntim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.",
10262 ),
10263 value: 12,
10264 },
10265 EnumVariant {
10266 name: "COMBINED_PWM_MODE_2",
10267 description: Some(
10268 "tim_oc1ref has the same behavior as in PWM mode 2.\ntim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.",
10269 ),
10270 value: 13,
10271 },
10272 EnumVariant {
10273 name: "ASYMMETRIC_PWM_MODE_1",
10274 description: Some(
10275 "tim_oc1ref has the same behavior as in PWM mode 1.\ntim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is\ncounting down.",
10276 ),
10277 value: 14,
10278 },
10279 EnumVariant {
10280 name: "ASYMMETRIC_PWM_MODE_2",
10281 description: Some(
10282 "tim_oc1ref has the same behavior as in PWM mode 2.\ntim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is\ncounting down.",
10283 ),
10284 value: 15,
10285 },
10286 ],
10287 },
10288 Enum {
10289 name: "Ossi",
10290 description: None,
10291 bit_size: 1,
10292 variants: &[
10293 EnumVariant {
10294 name: "DISABLED",
10295 description: Some(
10296 "When inactive, OC/OCN outputs are disabled",
10297 ),
10298 value: 0,
10299 },
10300 EnumVariant {
10301 name: "IDLE_LEVEL",
10302 description: Some(
10303 "When inactive, OC/OCN outputs are forced to idle level",
10304 ),
10305 value: 1,
10306 },
10307 ],
10308 },
10309 Enum {
10310 name: "Ossr",
10311 description: None,
10312 bit_size: 1,
10313 variants: &[
10314 EnumVariant {
10315 name: "DISABLED",
10316 description: Some(
10317 "When inactive, OC/OCN outputs are disabled",
10318 ),
10319 value: 0,
10320 },
10321 EnumVariant {
10322 name: "IDLE_LEVEL",
10323 description: Some(
10324 "When inactive, OC/OCN outputs are enabled with their inactive level",
10325 ),
10326 value: 1,
10327 },
10328 ],
10329 },
10330 Enum {
10331 name: "Sms",
10332 description: None,
10333 bit_size: 4,
10334 variants: &[
10335 EnumVariant {
10336 name: "DISABLED",
10337 description: Some(
10338 "Slave mode disabled - if CEN = '1' then the prescaler is clocked directly by the internal clock.",
10339 ),
10340 value: 0,
10341 },
10342 EnumVariant {
10343 name: "ENCODER_MODE_1",
10344 description: Some(
10345 "Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level.",
10346 ),
10347 value: 1,
10348 },
10349 EnumVariant {
10350 name: "ENCODER_MODE_2",
10351 description: Some(
10352 "Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level.",
10353 ),
10354 value: 2,
10355 },
10356 EnumVariant {
10357 name: "ENCODER_MODE_3",
10358 description: Some(
10359 "Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input.",
10360 ),
10361 value: 3,
10362 },
10363 EnumVariant {
10364 name: "RESET_MODE",
10365 description: Some(
10366 "Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers.",
10367 ),
10368 value: 4,
10369 },
10370 EnumVariant {
10371 name: "GATED_MODE",
10372 description: Some(
10373 "Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.",
10374 ),
10375 value: 5,
10376 },
10377 EnumVariant {
10378 name: "TRIGGER_MODE",
10379 description: Some(
10380 "Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled.",
10381 ),
10382 value: 6,
10383 },
10384 EnumVariant {
10385 name: "EXT_CLOCK_MODE",
10386 description: Some(
10387 "External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.",
10388 ),
10389 value: 7,
10390 },
10391 EnumVariant {
10392 name: "COMBINED_RESET_TRIGGER",
10393 description: Some(
10394 "Rising edge of the selected trigger input (tim_trgi) reinitializes the counter, generates an update of the registers and starts the counter.",
10395 ),
10396 value: 8,
10397 },
10398 EnumVariant {
10399 name: "COMBINED_GATED_TRIGGER",
10400 description: Some(
10401 "The counter clock is enabled when the trigger input (tim_trgi) is high. The counter stops and is reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled.",
10402 ),
10403 value: 9,
10404 },
10405 EnumVariant {
10406 name: "ENCODER_UP_X2",
10407 description: Some(
10408 "Encoder mode, Clock plus direction, x2 mode.",
10409 ),
10410 value: 10,
10411 },
10412 EnumVariant {
10413 name: "ENCODER_UP_X1",
10414 description: Some(
10415 "Encoder mode, Clock plus direction, x1 mode, tim_ti2fp2 edge sensitivity is set by CC2P",
10416 ),
10417 value: 11,
10418 },
10419 EnumVariant {
10420 name: "ENCODER_DIR_X2",
10421 description: Some(
10422 "Encoder mode, Directional Clock, x2 mode.",
10423 ),
10424 value: 12,
10425 },
10426 EnumVariant {
10427 name: "ENCODER_DIR_X1",
10428 description: Some(
10429 "Encoder mode, Directional Clock, x1 mode, tim_ti1fp1 and tim_ti2fp2 edge sensitivity is set by CC1P and CC2P.",
10430 ),
10431 value: 13,
10432 },
10433 EnumVariant {
10434 name: "QUADRATURE_ENCODER_MODE_X1_TI1PF1",
10435 description: Some(
10436 "Quadrature encoder mode, x1 mode, counting on tim_ti1fp1 edges only, edge sensitivity is set by CC1P.",
10437 ),
10438 value: 14,
10439 },
10440 EnumVariant {
10441 name: "QUADRATURE_ENCODER_MODE_X1_TI2PF2",
10442 description: Some(
10443 "Quadrature encoder mode, x1 mode, counting on tim_ti2fp2 edges only, edge sensitivity is set by CC2P.",
10444 ),
10445 value: 15,
10446 },
10447 ],
10448 },
10449 Enum {
10450 name: "Smsps",
10451 description: None,
10452 bit_size: 1,
10453 variants: &[
10454 EnumVariant {
10455 name: "UPDATE",
10456 description: Some(
10457 "The transfer is triggered by the Timer’s Update event",
10458 ),
10459 value: 0,
10460 },
10461 EnumVariant {
10462 name: "INDEX",
10463 description: Some(
10464 "The transfer is triggered by the Index event",
10465 ),
10466 value: 1,
10467 },
10468 ],
10469 },
10470 Enum {
10471 name: "Ti1s",
10472 description: None,
10473 bit_size: 1,
10474 variants: &[
10475 EnumVariant {
10476 name: "NORMAL",
10477 description: Some(
10478 "The TIMx_CH1 pin is connected to TI1 input",
10479 ),
10480 value: 0,
10481 },
10482 EnumVariant {
10483 name: "XOR",
10484 description: Some(
10485 "The TIMx_CH1, CH2, CH3 pins are connected to TI1 input",
10486 ),
10487 value: 1,
10488 },
10489 ],
10490 },
10491 Enum {
10492 name: "Ts",
10493 description: None,
10494 bit_size: 5,
10495 variants: &[
10496 EnumVariant {
10497 name: "ITR0",
10498 description: Some(
10499 "Internal Trigger 0",
10500 ),
10501 value: 0,
10502 },
10503 EnumVariant {
10504 name: "ITR1",
10505 description: Some(
10506 "Internal Trigger 1",
10507 ),
10508 value: 1,
10509 },
10510 EnumVariant {
10511 name: "ITR2",
10512 description: Some(
10513 "Internal Trigger 2",
10514 ),
10515 value: 2,
10516 },
10517 EnumVariant {
10518 name: "ITR3",
10519 description: Some(
10520 "Internal Trigger 3",
10521 ),
10522 value: 3,
10523 },
10524 EnumVariant {
10525 name: "TI1F_ED",
10526 description: Some(
10527 "TI1 Edge Detector",
10528 ),
10529 value: 4,
10530 },
10531 EnumVariant {
10532 name: "TI1FP1",
10533 description: Some(
10534 "Filtered Timer Input 1",
10535 ),
10536 value: 5,
10537 },
10538 EnumVariant {
10539 name: "TI2FP2",
10540 description: Some(
10541 "Filtered Timer Input 2",
10542 ),
10543 value: 6,
10544 },
10545 EnumVariant {
10546 name: "ETRF",
10547 description: Some(
10548 "External Trigger input",
10549 ),
10550 value: 7,
10551 },
10552 EnumVariant {
10553 name: "ITR4",
10554 description: Some(
10555 "Internal Trigger 4",
10556 ),
10557 value: 8,
10558 },
10559 EnumVariant {
10560 name: "ITR5",
10561 description: Some(
10562 "Internal Trigger 5",
10563 ),
10564 value: 9,
10565 },
10566 EnumVariant {
10567 name: "ITR6",
10568 description: Some(
10569 "Internal Trigger 6",
10570 ),
10571 value: 10,
10572 },
10573 EnumVariant {
10574 name: "ITR7",
10575 description: Some(
10576 "Internal Trigger 7",
10577 ),
10578 value: 11,
10579 },
10580 EnumVariant {
10581 name: "ITR8",
10582 description: Some(
10583 "Internal Trigger 8",
10584 ),
10585 value: 12,
10586 },
10587 EnumVariant {
10588 name: "ITR9",
10589 description: Some(
10590 "Internal Trigger 9",
10591 ),
10592 value: 13,
10593 },
10594 EnumVariant {
10595 name: "ITR10",
10596 description: Some(
10597 "Internal Trigger 10",
10598 ),
10599 value: 14,
10600 },
10601 EnumVariant {
10602 name: "ITR11",
10603 description: Some(
10604 "Internal Trigger 11",
10605 ),
10606 value: 15,
10607 },
10608 EnumVariant {
10609 name: "ITR12",
10610 description: Some(
10611 "Internal Trigger 12",
10612 ),
10613 value: 16,
10614 },
10615 EnumVariant {
10616 name: "ITR13",
10617 description: Some(
10618 "Internal Trigger 13",
10619 ),
10620 value: 17,
10621 },
10622 EnumVariant {
10623 name: "ITR14",
10624 description: Some(
10625 "Internal Trigger 14",
10626 ),
10627 value: 18,
10628 },
10629 EnumVariant {
10630 name: "ITR15",
10631 description: Some(
10632 "Internal Trigger 15",
10633 ),
10634 value: 19,
10635 },
10636 ],
10637 },
10638 Enum {
10639 name: "Urs",
10640 description: None,
10641 bit_size: 1,
10642 variants: &[
10643 EnumVariant {
10644 name: "ANY_EVENT",
10645 description: Some(
10646 "Any of counter overflow/underflow, setting UG, or update through slave mode, generates an update interrupt or DMA request",
10647 ),
10648 value: 0,
10649 },
10650 EnumVariant {
10651 name: "COUNTER_ONLY",
10652 description: Some(
10653 "Only counter overflow/underflow generates an update interrupt or DMA request",
10654 ),
10655 value: 1,
10656 },
10657 ],
10658 },
10659 ],
10660};
10661