1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Ucpd",
7 extends: None,
8 description: Some(
9 "USB Power Delivery interface",
10 ),
11 items: &[
12 BlockItem {
13 name: "cfgr1",
14 description: Some(
15 "configuration register 1",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cfgr1",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "cfgr2",
31 description: Some(
32 "configuration register 2",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Cfgr2",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "cfgr3",
48 description: Some(
49 "configuration register 3",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Cfgr3",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "cr",
65 description: Some(
66 "control register",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Cr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "imr",
82 description: Some(
83 "interrupt mask register",
84 ),
85 array: None,
86 byte_offset: 0x10,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::ReadWrite,
90 bit_size: 32,
91 fieldset: Some(
92 "Imr",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "sr",
99 description: Some(
100 "status register",
101 ),
102 array: None,
103 byte_offset: 0x14,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::ReadWrite,
107 bit_size: 32,
108 fieldset: Some(
109 "Sr",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "icr",
116 description: Some(
117 "interrupt clear register",
118 ),
119 array: None,
120 byte_offset: 0x18,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::ReadWrite,
124 bit_size: 32,
125 fieldset: Some(
126 "Icr",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "tx_ordsetr",
133 description: Some(
134 "Tx ordered set type register",
135 ),
136 array: None,
137 byte_offset: 0x1c,
138 inner: BlockItemInner::Register(
139 Register {
140 access: Access::ReadWrite,
141 bit_size: 32,
142 fieldset: Some(
143 "TxOrdsetr",
144 ),
145 },
146 ),
147 },
148 BlockItem {
149 name: "tx_payszr",
150 description: Some(
151 "Tx payload size register",
152 ),
153 array: None,
154 byte_offset: 0x20,
155 inner: BlockItemInner::Register(
156 Register {
157 access: Access::ReadWrite,
158 bit_size: 32,
159 fieldset: Some(
160 "TxPayszr",
161 ),
162 },
163 ),
164 },
165 BlockItem {
166 name: "txdr",
167 description: Some(
168 "Tx data register",
169 ),
170 array: None,
171 byte_offset: 0x24,
172 inner: BlockItemInner::Register(
173 Register {
174 access: Access::ReadWrite,
175 bit_size: 32,
176 fieldset: Some(
177 "Txdr",
178 ),
179 },
180 ),
181 },
182 BlockItem {
183 name: "rx_ordsetr",
184 description: None,
185 array: None,
186 byte_offset: 0x28,
187 inner: BlockItemInner::Register(
188 Register {
189 access: Access::ReadWrite,
190 bit_size: 32,
191 fieldset: Some(
192 "RxOrdsetr",
193 ),
194 },
195 ),
196 },
197 BlockItem {
198 name: "rx_payszr",
199 description: None,
200 array: None,
201 byte_offset: 0x2c,
202 inner: BlockItemInner::Register(
203 Register {
204 access: Access::ReadWrite,
205 bit_size: 32,
206 fieldset: Some(
207 "RxPayszr",
208 ),
209 },
210 ),
211 },
212 BlockItem {
213 name: "rxdr",
214 description: None,
215 array: None,
216 byte_offset: 0x30,
217 inner: BlockItemInner::Register(
218 Register {
219 access: Access::ReadWrite,
220 bit_size: 32,
221 fieldset: Some(
222 "Rxdr",
223 ),
224 },
225 ),
226 },
227 BlockItem {
228 name: "rx_ordextr1",
229 description: Some(
230 "Rx ordered set extension register 1",
231 ),
232 array: None,
233 byte_offset: 0x34,
234 inner: BlockItemInner::Register(
235 Register {
236 access: Access::ReadWrite,
237 bit_size: 32,
238 fieldset: Some(
239 "RxOrdextr1",
240 ),
241 },
242 ),
243 },
244 BlockItem {
245 name: "rx_ordextr2",
246 description: Some(
247 "Rx ordered set extension register 2",
248 ),
249 array: None,
250 byte_offset: 0x38,
251 inner: BlockItemInner::Register(
252 Register {
253 access: Access::ReadWrite,
254 bit_size: 32,
255 fieldset: Some(
256 "RxOrdextr2",
257 ),
258 },
259 ),
260 },
261 BlockItem {
262 name: "ipver",
263 description: Some(
264 "UCPD IP ID register",
265 ),
266 array: None,
267 byte_offset: 0x3f4,
268 inner: BlockItemInner::Register(
269 Register {
270 access: Access::Read,
271 bit_size: 32,
272 fieldset: Some(
273 "Ipver",
274 ),
275 },
276 ),
277 },
278 BlockItem {
279 name: "ipid",
280 description: Some(
281 "UCPD IP ID register",
282 ),
283 array: None,
284 byte_offset: 0x3f8,
285 inner: BlockItemInner::Register(
286 Register {
287 access: Access::Read,
288 bit_size: 32,
289 fieldset: Some(
290 "Ipid",
291 ),
292 },
293 ),
294 },
295 BlockItem {
296 name: "mid",
297 description: Some(
298 "UCPD IP ID register",
299 ),
300 array: None,
301 byte_offset: 0x3fc,
302 inner: BlockItemInner::Register(
303 Register {
304 access: Access::Read,
305 bit_size: 32,
306 fieldset: Some(
307 "Mid",
308 ),
309 },
310 ),
311 },
312 ],
313 },
314 ],
315 fieldsets: &[
316 FieldSet {
317 name: "Cfgr1",
318 extends: None,
319 description: Some(
320 "configuration register 1",
321 ),
322 bit_size: 32,
323 fields: &[
324 Field {
325 name: "hbitclkdiv",
326 description: Some(
327 "Division ratio for producing half-bit clock\r The bitfield determines the division ratio (the bitfield value plus one) of a clk divider producing half-bit clock (hbit_clk).",
328 ),
329 bit_offset: BitOffset::Regular(
330 RegularBitOffset {
331 offset: 0,
332 },
333 ),
334 bit_size: 6,
335 array: None,
336 enumm: None,
337 },
338 Field {
339 name: "ifrgap",
340 description: Some(
341 "Division ratio for producing inter-frame gap timer clock\r The bitfield determines the division ratio (the bitfield value minus one) of a clk divider producing inter-frame gap timer clock (tInterFrameGap).\r The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal.",
342 ),
343 bit_offset: BitOffset::Regular(
344 RegularBitOffset {
345 offset: 6,
346 },
347 ),
348 bit_size: 5,
349 array: None,
350 enumm: None,
351 },
352 Field {
353 name: "transwin",
354 description: Some(
355 "Transition window duration\r The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval.\r Set a value that produces an interval of 12 to 20 us, taking into account the clk frequency and the HBITCLKDIV[5:0] bitfield setting.",
356 ),
357 bit_offset: BitOffset::Regular(
358 RegularBitOffset {
359 offset: 11,
360 },
361 ),
362 bit_size: 5,
363 array: None,
364 enumm: None,
365 },
366 Field {
367 name: "psc_usbpdclk",
368 description: Some(
369 "Pre-scaler division ratio for generating clk\r The bitfield determines the division ratio of a kernel clock pre-scaler producing peripheral clock (clk).\r It is recommended to use the pre-scaler so as to set the clk frequency in the range from 6 to 9 MHz.",
370 ),
371 bit_offset: BitOffset::Regular(
372 RegularBitOffset {
373 offset: 17,
374 },
375 ),
376 bit_size: 3,
377 array: None,
378 enumm: Some(
379 "PscUsbpdclk",
380 ),
381 },
382 Field {
383 name: "rxordseten",
384 description: Some(
385 "Receiver ordered set enable\r The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function:\r 0bxxxxxxxx1: SOP detect enabled\r 0bxxxxxxx1x: SOP' detect enabled\r 0bxxxxxx1xx: SOP'' detect enabled\r 0bxxxxx1xxx: Hard Reset detect enabled\r 0bxxxx1xxxx: Cable Detect reset enabled\r 0bxxx1xxxxx: SOP'_Debug enabled\r 0bxx1xxxxxx: SOP''_Debug enabled\r 0bx1xxxxxxx: SOP extension#1 enabled\r 0b1xxxxxxxx: SOP extension#2 enabled",
386 ),
387 bit_offset: BitOffset::Regular(
388 RegularBitOffset {
389 offset: 20,
390 },
391 ),
392 bit_size: 9,
393 array: None,
394 enumm: None,
395 },
396 Field {
397 name: "txdmaen",
398 description: Some(
399 "Transmission DMA mode enable\r When set, the bit enables DMA mode for transmission.",
400 ),
401 bit_offset: BitOffset::Regular(
402 RegularBitOffset {
403 offset: 29,
404 },
405 ),
406 bit_size: 1,
407 array: None,
408 enumm: None,
409 },
410 Field {
411 name: "rxdmaen",
412 description: Some(
413 "Reception DMA mode enable\r When set, the bit enables DMA mode for reception.",
414 ),
415 bit_offset: BitOffset::Regular(
416 RegularBitOffset {
417 offset: 30,
418 },
419 ),
420 bit_size: 1,
421 array: None,
422 enumm: None,
423 },
424 Field {
425 name: "ucpden",
426 description: Some(
427 "peripheral enable\r General enable of the peripheral.\r Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state.",
428 ),
429 bit_offset: BitOffset::Regular(
430 RegularBitOffset {
431 offset: 31,
432 },
433 ),
434 bit_size: 1,
435 array: None,
436 enumm: None,
437 },
438 ],
439 },
440 FieldSet {
441 name: "Cfgr2",
442 extends: None,
443 description: Some(
444 "configuration register 2",
445 ),
446 bit_size: 32,
447 fields: &[
448 Field {
449 name: "rxfiltdis",
450 description: Some(
451 "BMC decoder Rx pre-filter enable\r The sampling clock is that of the receiver (that is, after pre-scaler).",
452 ),
453 bit_offset: BitOffset::Regular(
454 RegularBitOffset {
455 offset: 0,
456 },
457 ),
458 bit_size: 1,
459 array: None,
460 enumm: None,
461 },
462 Field {
463 name: "rxfilt2n3",
464 description: Some(
465 "BMC decoder Rx pre-filter sampling method\r Number of consistent consecutive samples before confirming a new value.",
466 ),
467 bit_offset: BitOffset::Regular(
468 RegularBitOffset {
469 offset: 1,
470 },
471 ),
472 bit_size: 1,
473 array: None,
474 enumm: None,
475 },
476 Field {
477 name: "forceclk",
478 description: Some(
479 "Force ClkReq clock request",
480 ),
481 bit_offset: BitOffset::Regular(
482 RegularBitOffset {
483 offset: 2,
484 },
485 ),
486 bit_size: 1,
487 array: None,
488 enumm: None,
489 },
490 Field {
491 name: "wupen",
492 description: Some(
493 "Wakeup from Stop mode enable\r Setting the bit enables the ASYNC_INT signal.",
494 ),
495 bit_offset: BitOffset::Regular(
496 RegularBitOffset {
497 offset: 3,
498 },
499 ),
500 bit_size: 1,
501 array: None,
502 enumm: None,
503 },
504 ],
505 },
506 FieldSet {
507 name: "Cfgr3",
508 extends: None,
509 description: Some(
510 "configuration register 3",
511 ),
512 bit_size: 32,
513 fields: &[
514 Field {
515 name: "trim_cc1_rd",
516 description: Some(
517 "SW trim value for Rd resistor on the CC1 line",
518 ),
519 bit_offset: BitOffset::Regular(
520 RegularBitOffset {
521 offset: 0,
522 },
523 ),
524 bit_size: 4,
525 array: None,
526 enumm: None,
527 },
528 Field {
529 name: "trim_cc1_rp",
530 description: Some(
531 "SW trim value for Rp current sources on the CC1 line",
532 ),
533 bit_offset: BitOffset::Regular(
534 RegularBitOffset {
535 offset: 9,
536 },
537 ),
538 bit_size: 4,
539 array: None,
540 enumm: None,
541 },
542 Field {
543 name: "trim_cc2_rd",
544 description: Some(
545 "SW trim value for Rd resistor on the CC2 line",
546 ),
547 bit_offset: BitOffset::Regular(
548 RegularBitOffset {
549 offset: 16,
550 },
551 ),
552 bit_size: 4,
553 array: None,
554 enumm: None,
555 },
556 Field {
557 name: "trim_cc2_rp",
558 description: Some(
559 "SW trim value for Rp current sources on the CC2 line",
560 ),
561 bit_offset: BitOffset::Regular(
562 RegularBitOffset {
563 offset: 25,
564 },
565 ),
566 bit_size: 4,
567 array: None,
568 enumm: None,
569 },
570 ],
571 },
572 FieldSet {
573 name: "Cr",
574 extends: None,
575 description: Some(
576 "control register",
577 ),
578 bit_size: 32,
579 fields: &[
580 Field {
581 name: "txmode",
582 description: Some(
583 "Type of Tx packet\r Writing the bitfield triggers the action as follows, depending on the value:\r Others: invalid\r From V1.1 of the USB PD specification, there is a counter defined for the duration of the BIST Carrier Mode 2. To quit this mode correctly (after the \"tBISTContMode\" delay), disable the peripheral (UCPDEN = 0).",
584 ),
585 bit_offset: BitOffset::Regular(
586 RegularBitOffset {
587 offset: 0,
588 },
589 ),
590 bit_size: 2,
591 array: None,
592 enumm: Some(
593 "Txmode",
594 ),
595 },
596 Field {
597 name: "txsend",
598 description: Some(
599 "Command to send a Tx packet\r The bit is cleared by hardware as soon as the packet transmission begins or is discarded.",
600 ),
601 bit_offset: BitOffset::Regular(
602 RegularBitOffset {
603 offset: 2,
604 },
605 ),
606 bit_size: 1,
607 array: None,
608 enumm: None,
609 },
610 Field {
611 name: "txhrst",
612 description: Some(
613 "Command to send a Tx Hard Reset\r The bit is cleared by hardware as soon as the message transmission begins or is discarded.",
614 ),
615 bit_offset: BitOffset::Regular(
616 RegularBitOffset {
617 offset: 3,
618 },
619 ),
620 bit_size: 1,
621 array: None,
622 enumm: None,
623 },
624 Field {
625 name: "rxmode",
626 description: Some(
627 "Receiver mode\r Determines the mode of the receiver.\r When the bit is set, RXORDSET behaves normally, RXDR no longer receives bytes yet the CRC checking still proceeds as for a normal message.",
628 ),
629 bit_offset: BitOffset::Regular(
630 RegularBitOffset {
631 offset: 4,
632 },
633 ),
634 bit_size: 1,
635 array: None,
636 enumm: None,
637 },
638 Field {
639 name: "phyrxen",
640 description: Some(
641 "USB Power Delivery receiver enable\r Both CC1 and CC2 receivers are disabled when the bit is cleared. Only the CC receiver selected via the PHYCCSEL bit is enabled when the bit is set.",
642 ),
643 bit_offset: BitOffset::Regular(
644 RegularBitOffset {
645 offset: 5,
646 },
647 ),
648 bit_size: 1,
649 array: None,
650 enumm: None,
651 },
652 Field {
653 name: "phyccsel",
654 description: Some(
655 "CC1/CC2 line selector for USB Power Delivery signaling\r The selection depends on the cable orientation as discovered at attach.",
656 ),
657 bit_offset: BitOffset::Regular(
658 RegularBitOffset {
659 offset: 6,
660 },
661 ),
662 bit_size: 1,
663 array: None,
664 enumm: Some(
665 "Phyccsel",
666 ),
667 },
668 Field {
669 name: "anasubmode",
670 description: Some(
671 "Analog PHY sub-mode\r Refer to TYPEC_VSTATE_CCx for the effect of this bitfield.",
672 ),
673 bit_offset: BitOffset::Regular(
674 RegularBitOffset {
675 offset: 7,
676 },
677 ),
678 bit_size: 2,
679 array: None,
680 enumm: None,
681 },
682 Field {
683 name: "anamode",
684 description: Some(
685 "Analog PHY operating mode\r The use of CC1 and CC2 depends on CCENABLE. Refer to ANAMODE, ANASUBMODE and link with TYPEC_VSTATE_CCx for the effect of this bitfield in conjunction with ANASUBMODE[1:0].",
686 ),
687 bit_offset: BitOffset::Regular(
688 RegularBitOffset {
689 offset: 9,
690 },
691 ),
692 bit_size: 1,
693 array: None,
694 enumm: Some(
695 "Anamode",
696 ),
697 },
698 Field {
699 name: "ccenable",
700 description: Some(
701 "CC line enable\r This bitfield enables CC1 and CC2 line analog PHYs (pull-ups and pull-downs) according to ANAMODE and ANASUBMODE[1:0] setting.\r A single line PHY can be enabled when, for example, the other line is driven by VCONN via an external VCONN switch. Enabling both PHYs is the normal usage for sink/source.",
702 ),
703 bit_offset: BitOffset::Regular(
704 RegularBitOffset {
705 offset: 10,
706 },
707 ),
708 bit_size: 2,
709 array: None,
710 enumm: Some(
711 "Ccenable",
712 ),
713 },
714 Field {
715 name: "cc1vconnen",
716 description: Some(
717 "VCONN switch enable for CC1",
718 ),
719 bit_offset: BitOffset::Regular(
720 RegularBitOffset {
721 offset: 13,
722 },
723 ),
724 bit_size: 1,
725 array: None,
726 enumm: None,
727 },
728 Field {
729 name: "cc2vconnen",
730 description: Some(
731 "VCONN switch enable for CC2",
732 ),
733 bit_offset: BitOffset::Regular(
734 RegularBitOffset {
735 offset: 14,
736 },
737 ),
738 bit_size: 1,
739 array: None,
740 enumm: None,
741 },
742 Field {
743 name: "dbatten",
744 description: Some(
745 "Dead battery function enable\r The bit takes effect upon setting the USBPDstrobe bit of the SYS_CONFIG register.\r Dead battery function only operates if the external circuit is appropriately configured.",
746 ),
747 bit_offset: BitOffset::Regular(
748 RegularBitOffset {
749 offset: 15,
750 },
751 ),
752 bit_size: 1,
753 array: None,
754 enumm: None,
755 },
756 Field {
757 name: "frsrxen",
758 description: Some(
759 "FRS event detection enable\r Setting the bit enables FRS Rx event (FRSEVT) detection on the CC line selected through the PHYCCSEL bit. 0: Disable\r Clear the bit when the device is attached to an FRS-incapable source/sink.",
760 ),
761 bit_offset: BitOffset::Regular(
762 RegularBitOffset {
763 offset: 16,
764 },
765 ),
766 bit_size: 1,
767 array: None,
768 enumm: None,
769 },
770 Field {
771 name: "frstx",
772 description: Some(
773 "FRS Tx signaling enable.\r Setting the bit enables FRS Tx signaling.\r The bit is cleared by hardware after a delay respecting the USB Power Delivery specification Revision 3.0.",
774 ),
775 bit_offset: BitOffset::Regular(
776 RegularBitOffset {
777 offset: 17,
778 },
779 ),
780 bit_size: 1,
781 array: None,
782 enumm: None,
783 },
784 Field {
785 name: "rdch",
786 description: Some(
787 "Rdch condition drive\r The bit drives Rdch condition on the CC line selected through the PHYCCSEL bit (thus associated with VCONN), by remaining set during the source-only UnattachedWait.SRC state, to respect the Type-C state. Refer to \"USB Type-C ECN for Source VCONN Discharge\". The CCENABLE[1:0] bitfield must be set accordingly, too.",
788 ),
789 bit_offset: BitOffset::Regular(
790 RegularBitOffset {
791 offset: 18,
792 },
793 ),
794 bit_size: 1,
795 array: None,
796 enumm: None,
797 },
798 Field {
799 name: "cc1tcdis",
800 description: Some(
801 "CC1 Type-C detector disable\r The bit disables the Type-C detector on the CC1 line.\r When enabled, the Type-C detector for CC1 is configured through ANAMODE and ANASUBMODE[1:0].",
802 ),
803 bit_offset: BitOffset::Regular(
804 RegularBitOffset {
805 offset: 20,
806 },
807 ),
808 bit_size: 1,
809 array: None,
810 enumm: None,
811 },
812 Field {
813 name: "cc2tcdis",
814 description: Some(
815 "CC2 Type-C detector disable\r The bit disables the Type-C detector on the CC2 line.\r When enabled, the Type-C detector for CC2 is configured through ANAMODE and ANASUBMODE[1:0].",
816 ),
817 bit_offset: BitOffset::Regular(
818 RegularBitOffset {
819 offset: 21,
820 },
821 ),
822 bit_size: 1,
823 array: None,
824 enumm: None,
825 },
826 ],
827 },
828 FieldSet {
829 name: "Icr",
830 extends: None,
831 description: Some(
832 "interrupt clear register",
833 ),
834 bit_size: 32,
835 fields: &[
836 Field {
837 name: "txmsgdisccf",
838 description: Some(
839 "Tx message discard flag (TXMSGDISC) clear\r Setting the bit clears the TXMSGDISC flag in the SR register.",
840 ),
841 bit_offset: BitOffset::Regular(
842 RegularBitOffset {
843 offset: 1,
844 },
845 ),
846 bit_size: 1,
847 array: None,
848 enumm: None,
849 },
850 Field {
851 name: "txmsgsentcf",
852 description: Some(
853 "Tx message send flag (TXMSGSENT) clear\r Setting the bit clears the TXMSGSENT flag in the SR register.",
854 ),
855 bit_offset: BitOffset::Regular(
856 RegularBitOffset {
857 offset: 2,
858 },
859 ),
860 bit_size: 1,
861 array: None,
862 enumm: None,
863 },
864 Field {
865 name: "txmsgabtcf",
866 description: Some(
867 "Tx message abort flag (TXMSGABT) clear\r Setting the bit clears the TXMSGABT flag in the SR register.",
868 ),
869 bit_offset: BitOffset::Regular(
870 RegularBitOffset {
871 offset: 3,
872 },
873 ),
874 bit_size: 1,
875 array: None,
876 enumm: None,
877 },
878 Field {
879 name: "hrstdisccf",
880 description: Some(
881 "Hard reset discard flag (HRSTDISC) clear\r Setting the bit clears the HRSTDISC flag in the SR register.",
882 ),
883 bit_offset: BitOffset::Regular(
884 RegularBitOffset {
885 offset: 4,
886 },
887 ),
888 bit_size: 1,
889 array: None,
890 enumm: None,
891 },
892 Field {
893 name: "hrstsentcf",
894 description: Some(
895 "Hard reset send flag (HRSTSENT) clear\r Setting the bit clears the HRSTSENT flag in the SR register.",
896 ),
897 bit_offset: BitOffset::Regular(
898 RegularBitOffset {
899 offset: 5,
900 },
901 ),
902 bit_size: 1,
903 array: None,
904 enumm: None,
905 },
906 Field {
907 name: "txundcf",
908 description: Some(
909 "Tx underflow flag (TXUND) clear\r Setting the bit clears the TXUND flag in the SR register.",
910 ),
911 bit_offset: BitOffset::Regular(
912 RegularBitOffset {
913 offset: 6,
914 },
915 ),
916 bit_size: 1,
917 array: None,
918 enumm: None,
919 },
920 Field {
921 name: "rxorddetcf",
922 description: Some(
923 "Rx ordered set detect flag (RXORDDET) clear\r Setting the bit clears the RXORDDET flag in the SR register.",
924 ),
925 bit_offset: BitOffset::Regular(
926 RegularBitOffset {
927 offset: 9,
928 },
929 ),
930 bit_size: 1,
931 array: None,
932 enumm: None,
933 },
934 Field {
935 name: "rxhrstdetcf",
936 description: Some(
937 "Rx Hard Reset detect flag (RXHRSTDET) clear\r Setting the bit clears the RXHRSTDET flag in the SR register.",
938 ),
939 bit_offset: BitOffset::Regular(
940 RegularBitOffset {
941 offset: 10,
942 },
943 ),
944 bit_size: 1,
945 array: None,
946 enumm: None,
947 },
948 Field {
949 name: "rxovrcf",
950 description: Some(
951 "Rx overflow flag (RXOVR) clear\r Setting the bit clears the RXOVR flag in the SR register.",
952 ),
953 bit_offset: BitOffset::Regular(
954 RegularBitOffset {
955 offset: 11,
956 },
957 ),
958 bit_size: 1,
959 array: None,
960 enumm: None,
961 },
962 Field {
963 name: "rxmsgendcf",
964 description: Some(
965 "Rx message received flag (RXMSGEND) clear\r Setting the bit clears the RXMSGEND flag in the SR register.",
966 ),
967 bit_offset: BitOffset::Regular(
968 RegularBitOffset {
969 offset: 12,
970 },
971 ),
972 bit_size: 1,
973 array: None,
974 enumm: None,
975 },
976 Field {
977 name: "typecevt1cf",
978 description: Some(
979 "Type-C CC1 event flag (TYPECEVT1) clear\r Setting the bit clears the TYPECEVT1 flag in the SR register",
980 ),
981 bit_offset: BitOffset::Regular(
982 RegularBitOffset {
983 offset: 14,
984 },
985 ),
986 bit_size: 1,
987 array: None,
988 enumm: None,
989 },
990 Field {
991 name: "typecevt2cf",
992 description: Some(
993 "Type-C CC2 line event flag (TYPECEVT2) clear\r Setting the bit clears the TYPECEVT2 flag in the SR register",
994 ),
995 bit_offset: BitOffset::Regular(
996 RegularBitOffset {
997 offset: 15,
998 },
999 ),
1000 bit_size: 1,
1001 array: None,
1002 enumm: None,
1003 },
1004 Field {
1005 name: "frsevtcf",
1006 description: Some(
1007 "FRS event flag (FRSEVT) clear\r Setting the bit clears the FRSEVT flag in the SR register.",
1008 ),
1009 bit_offset: BitOffset::Regular(
1010 RegularBitOffset {
1011 offset: 20,
1012 },
1013 ),
1014 bit_size: 1,
1015 array: None,
1016 enumm: None,
1017 },
1018 ],
1019 },
1020 FieldSet {
1021 name: "Imr",
1022 extends: None,
1023 description: Some(
1024 "interrupt mask register",
1025 ),
1026 bit_size: 32,
1027 fields: &[
1028 Field {
1029 name: "txisie",
1030 description: Some(
1031 "TXIS interrupt enable",
1032 ),
1033 bit_offset: BitOffset::Regular(
1034 RegularBitOffset {
1035 offset: 0,
1036 },
1037 ),
1038 bit_size: 1,
1039 array: None,
1040 enumm: None,
1041 },
1042 Field {
1043 name: "txmsgdiscie",
1044 description: Some(
1045 "TXMSGDISC interrupt enable",
1046 ),
1047 bit_offset: BitOffset::Regular(
1048 RegularBitOffset {
1049 offset: 1,
1050 },
1051 ),
1052 bit_size: 1,
1053 array: None,
1054 enumm: None,
1055 },
1056 Field {
1057 name: "txmsgsentie",
1058 description: Some(
1059 "TXMSGSENT interrupt enable",
1060 ),
1061 bit_offset: BitOffset::Regular(
1062 RegularBitOffset {
1063 offset: 2,
1064 },
1065 ),
1066 bit_size: 1,
1067 array: None,
1068 enumm: None,
1069 },
1070 Field {
1071 name: "txmsgabtie",
1072 description: Some(
1073 "TXMSGABT interrupt enable",
1074 ),
1075 bit_offset: BitOffset::Regular(
1076 RegularBitOffset {
1077 offset: 3,
1078 },
1079 ),
1080 bit_size: 1,
1081 array: None,
1082 enumm: None,
1083 },
1084 Field {
1085 name: "hrstdiscie",
1086 description: Some(
1087 "HRSTDISC interrupt enable",
1088 ),
1089 bit_offset: BitOffset::Regular(
1090 RegularBitOffset {
1091 offset: 4,
1092 },
1093 ),
1094 bit_size: 1,
1095 array: None,
1096 enumm: None,
1097 },
1098 Field {
1099 name: "hrstsentie",
1100 description: Some(
1101 "HRSTSENT interrupt enable",
1102 ),
1103 bit_offset: BitOffset::Regular(
1104 RegularBitOffset {
1105 offset: 5,
1106 },
1107 ),
1108 bit_size: 1,
1109 array: None,
1110 enumm: None,
1111 },
1112 Field {
1113 name: "txundie",
1114 description: Some(
1115 "TXUND interrupt enable",
1116 ),
1117 bit_offset: BitOffset::Regular(
1118 RegularBitOffset {
1119 offset: 6,
1120 },
1121 ),
1122 bit_size: 1,
1123 array: None,
1124 enumm: None,
1125 },
1126 Field {
1127 name: "rxneie",
1128 description: Some(
1129 "RXNE interrupt enable",
1130 ),
1131 bit_offset: BitOffset::Regular(
1132 RegularBitOffset {
1133 offset: 8,
1134 },
1135 ),
1136 bit_size: 1,
1137 array: None,
1138 enumm: None,
1139 },
1140 Field {
1141 name: "rxorddetie",
1142 description: Some(
1143 "RXORDDET interrupt enable",
1144 ),
1145 bit_offset: BitOffset::Regular(
1146 RegularBitOffset {
1147 offset: 9,
1148 },
1149 ),
1150 bit_size: 1,
1151 array: None,
1152 enumm: None,
1153 },
1154 Field {
1155 name: "rxhrstdetie",
1156 description: Some(
1157 "RXHRSTDET interrupt enable",
1158 ),
1159 bit_offset: BitOffset::Regular(
1160 RegularBitOffset {
1161 offset: 10,
1162 },
1163 ),
1164 bit_size: 1,
1165 array: None,
1166 enumm: None,
1167 },
1168 Field {
1169 name: "rxovrie",
1170 description: Some(
1171 "RXOVR interrupt enable",
1172 ),
1173 bit_offset: BitOffset::Regular(
1174 RegularBitOffset {
1175 offset: 11,
1176 },
1177 ),
1178 bit_size: 1,
1179 array: None,
1180 enumm: None,
1181 },
1182 Field {
1183 name: "rxmsgendie",
1184 description: Some(
1185 "RXMSGEND interrupt enable",
1186 ),
1187 bit_offset: BitOffset::Regular(
1188 RegularBitOffset {
1189 offset: 12,
1190 },
1191 ),
1192 bit_size: 1,
1193 array: None,
1194 enumm: None,
1195 },
1196 Field {
1197 name: "typecevt1ie",
1198 description: Some(
1199 "TYPECEVT1 interrupt enable",
1200 ),
1201 bit_offset: BitOffset::Regular(
1202 RegularBitOffset {
1203 offset: 14,
1204 },
1205 ),
1206 bit_size: 1,
1207 array: None,
1208 enumm: None,
1209 },
1210 Field {
1211 name: "typecevt2ie",
1212 description: Some(
1213 "TYPECEVT2 interrupt enable",
1214 ),
1215 bit_offset: BitOffset::Regular(
1216 RegularBitOffset {
1217 offset: 15,
1218 },
1219 ),
1220 bit_size: 1,
1221 array: None,
1222 enumm: None,
1223 },
1224 Field {
1225 name: "frsevtie",
1226 description: Some(
1227 "FRSEVT interrupt enable",
1228 ),
1229 bit_offset: BitOffset::Regular(
1230 RegularBitOffset {
1231 offset: 20,
1232 },
1233 ),
1234 bit_size: 1,
1235 array: None,
1236 enumm: None,
1237 },
1238 ],
1239 },
1240 FieldSet {
1241 name: "Ipid",
1242 extends: None,
1243 description: Some(
1244 "UCPD IP ID register",
1245 ),
1246 bit_size: 32,
1247 fields: &[
1248 Field {
1249 name: "ipid",
1250 description: Some(
1251 "IPID",
1252 ),
1253 bit_offset: BitOffset::Regular(
1254 RegularBitOffset {
1255 offset: 0,
1256 },
1257 ),
1258 bit_size: 32,
1259 array: None,
1260 enumm: None,
1261 },
1262 ],
1263 },
1264 FieldSet {
1265 name: "Ipver",
1266 extends: None,
1267 description: Some(
1268 "UCPD IP ID register",
1269 ),
1270 bit_size: 32,
1271 fields: &[
1272 Field {
1273 name: "ipver",
1274 description: Some(
1275 "IPVER",
1276 ),
1277 bit_offset: BitOffset::Regular(
1278 RegularBitOffset {
1279 offset: 0,
1280 },
1281 ),
1282 bit_size: 32,
1283 array: None,
1284 enumm: None,
1285 },
1286 ],
1287 },
1288 FieldSet {
1289 name: "Mid",
1290 extends: None,
1291 description: Some(
1292 "UCPD IP ID register",
1293 ),
1294 bit_size: 32,
1295 fields: &[
1296 Field {
1297 name: "ipid",
1298 description: Some(
1299 "IPID",
1300 ),
1301 bit_offset: BitOffset::Regular(
1302 RegularBitOffset {
1303 offset: 0,
1304 },
1305 ),
1306 bit_size: 32,
1307 array: None,
1308 enumm: None,
1309 },
1310 ],
1311 },
1312 FieldSet {
1313 name: "RxOrdextr1",
1314 extends: None,
1315 description: Some(
1316 "Rx ordered set extension register 1",
1317 ),
1318 bit_size: 32,
1319 fields: &[
1320 Field {
1321 name: "rxsopx1",
1322 description: Some(
1323 "Ordered set 1 received\r The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last.",
1324 ),
1325 bit_offset: BitOffset::Regular(
1326 RegularBitOffset {
1327 offset: 0,
1328 },
1329 ),
1330 bit_size: 20,
1331 array: None,
1332 enumm: None,
1333 },
1334 ],
1335 },
1336 FieldSet {
1337 name: "RxOrdextr2",
1338 extends: None,
1339 description: Some(
1340 "Rx ordered set extension register 2",
1341 ),
1342 bit_size: 32,
1343 fields: &[
1344 Field {
1345 name: "rxsopx2",
1346 description: Some(
1347 "Ordered set 2 received\r The bitfield contains a full 20-bit sequence received, consisting of four K‑codes, each of five bits. The bit 0 (bit 0 of K‑code1) is receive first, the bit 19 (bit 4 of K‑code4) last.",
1348 ),
1349 bit_offset: BitOffset::Regular(
1350 RegularBitOffset {
1351 offset: 0,
1352 },
1353 ),
1354 bit_size: 20,
1355 array: None,
1356 enumm: None,
1357 },
1358 ],
1359 },
1360 FieldSet {
1361 name: "RxOrdsetr",
1362 extends: None,
1363 description: None,
1364 bit_size: 32,
1365 fields: &[
1366 Field {
1367 name: "rxordset",
1368 description: Some(
1369 "Rx ordered set code detected",
1370 ),
1371 bit_offset: BitOffset::Regular(
1372 RegularBitOffset {
1373 offset: 0,
1374 },
1375 ),
1376 bit_size: 3,
1377 array: None,
1378 enumm: Some(
1379 "Rxordset",
1380 ),
1381 },
1382 Field {
1383 name: "rxsop3of4",
1384 description: Some(
1385 "The bit indicates the number of correct K‑codes. For debug purposes only.",
1386 ),
1387 bit_offset: BitOffset::Regular(
1388 RegularBitOffset {
1389 offset: 3,
1390 },
1391 ),
1392 bit_size: 1,
1393 array: None,
1394 enumm: None,
1395 },
1396 Field {
1397 name: "rxsopkinvalid",
1398 description: Some(
1399 "The bitfield is for debug purposes only.\r Others: Invalid",
1400 ),
1401 bit_offset: BitOffset::Regular(
1402 RegularBitOffset {
1403 offset: 4,
1404 },
1405 ),
1406 bit_size: 3,
1407 array: None,
1408 enumm: Some(
1409 "Rxsopkinvalid",
1410 ),
1411 },
1412 ],
1413 },
1414 FieldSet {
1415 name: "RxPayszr",
1416 extends: None,
1417 description: None,
1418 bit_size: 32,
1419 fields: &[
1420 Field {
1421 name: "rxpaysz",
1422 description: Some(
1423 "Rx payload size received\r This bitfield contains the number of bytes of a payload (including header but excluding CRC) received: each time a new data byte is received in the RXDR register, the bitfield value increments and the RXMSGEND flag is set (and an interrupt generated if enabled).\r The bitfield may return a spurious value when a byte reception is ongoing (the RXMSGEND flag is low).",
1424 ),
1425 bit_offset: BitOffset::Regular(
1426 RegularBitOffset {
1427 offset: 0,
1428 },
1429 ),
1430 bit_size: 10,
1431 array: None,
1432 enumm: None,
1433 },
1434 ],
1435 },
1436 FieldSet {
1437 name: "Rxdr",
1438 extends: None,
1439 description: None,
1440 bit_size: 32,
1441 fields: &[
1442 Field {
1443 name: "rxdata",
1444 description: Some(
1445 "Data byte received",
1446 ),
1447 bit_offset: BitOffset::Regular(
1448 RegularBitOffset {
1449 offset: 0,
1450 },
1451 ),
1452 bit_size: 8,
1453 array: None,
1454 enumm: None,
1455 },
1456 ],
1457 },
1458 FieldSet {
1459 name: "Sr",
1460 extends: None,
1461 description: Some(
1462 "status register",
1463 ),
1464 bit_size: 32,
1465 fields: &[
1466 Field {
1467 name: "txis",
1468 description: Some(
1469 "Transmit interrupt status\r The flag indicates that the TXDR register is empty and new data write is required (as the amount of data sent has not reached the payload size defined in the TXPAYSZ bitfield). The flag is cleared with the data write into the TXDR register.",
1470 ),
1471 bit_offset: BitOffset::Regular(
1472 RegularBitOffset {
1473 offset: 0,
1474 },
1475 ),
1476 bit_size: 1,
1477 array: None,
1478 enumm: None,
1479 },
1480 Field {
1481 name: "txmsgdisc",
1482 description: Some(
1483 "Message transmission discarded\r The flag indicates that a message transmission was dropped. The flag is cleared by setting the TXMSGDISCCF bit.\r Transmission of a message can be dropped if there is a concurrent receive in progress or at excessive noise on the line. After a Tx message is discarded, the flag is only raised when the CC line becomes idle.",
1484 ),
1485 bit_offset: BitOffset::Regular(
1486 RegularBitOffset {
1487 offset: 1,
1488 },
1489 ),
1490 bit_size: 1,
1491 array: None,
1492 enumm: None,
1493 },
1494 Field {
1495 name: "txmsgsent",
1496 description: Some(
1497 "Message transmission completed\r The flag indicates the completion of packet transmission. It is cleared by setting the TXMSGSENTCF bit.\r In the event of a message transmission interrupted by a Hard Reset, the flag is not raised.",
1498 ),
1499 bit_offset: BitOffset::Regular(
1500 RegularBitOffset {
1501 offset: 2,
1502 },
1503 ),
1504 bit_size: 1,
1505 array: None,
1506 enumm: None,
1507 },
1508 Field {
1509 name: "txmsgabt",
1510 description: Some(
1511 "Transmit message abort\r The flag indicates that a Tx message is aborted due to a subsequent Hard Reset message send request taking priority during transmit. It is cleared by setting the TXMSGABTCF bit.",
1512 ),
1513 bit_offset: BitOffset::Regular(
1514 RegularBitOffset {
1515 offset: 3,
1516 },
1517 ),
1518 bit_size: 1,
1519 array: None,
1520 enumm: None,
1521 },
1522 Field {
1523 name: "hrstdisc",
1524 description: Some(
1525 "Hard Reset discarded\r The flag indicates that the Hard Reset message is discarded. The flag is cleared by setting the HRSTDISCCF bit.",
1526 ),
1527 bit_offset: BitOffset::Regular(
1528 RegularBitOffset {
1529 offset: 4,
1530 },
1531 ),
1532 bit_size: 1,
1533 array: None,
1534 enumm: None,
1535 },
1536 Field {
1537 name: "hrstsent",
1538 description: Some(
1539 "Hard Reset message sent\r The flag indicates that the Hard Reset message is sent. The flag is cleared by setting the HRSTSENTCF bit.",
1540 ),
1541 bit_offset: BitOffset::Regular(
1542 RegularBitOffset {
1543 offset: 5,
1544 },
1545 ),
1546 bit_size: 1,
1547 array: None,
1548 enumm: None,
1549 },
1550 Field {
1551 name: "txund",
1552 description: Some(
1553 "Tx data underrun detection\r The flag indicates that the Tx data register (TXDR) was not written in time for a transmit message to execute normally. It is cleared by setting the TXUNDCF bit.",
1554 ),
1555 bit_offset: BitOffset::Regular(
1556 RegularBitOffset {
1557 offset: 6,
1558 },
1559 ),
1560 bit_size: 1,
1561 array: None,
1562 enumm: None,
1563 },
1564 Field {
1565 name: "rxne",
1566 description: Some(
1567 "Receive data register not empty detection\r The flag indicates that the RXDR register is not empty. It is automatically cleared upon reading RXDR.",
1568 ),
1569 bit_offset: BitOffset::Regular(
1570 RegularBitOffset {
1571 offset: 8,
1572 },
1573 ),
1574 bit_size: 1,
1575 array: None,
1576 enumm: None,
1577 },
1578 Field {
1579 name: "rxorddet",
1580 description: Some(
1581 "Rx ordered set (4 K-codes) detection\r The flag indicates the detection of an ordered set. The relevant information is stored in the RXORDSET[2:0] bitfield of the RX_ORDSET register. It is cleared by setting the RXORDDETCF bit.",
1582 ),
1583 bit_offset: BitOffset::Regular(
1584 RegularBitOffset {
1585 offset: 9,
1586 },
1587 ),
1588 bit_size: 1,
1589 array: None,
1590 enumm: None,
1591 },
1592 Field {
1593 name: "rxhrstdet",
1594 description: Some(
1595 "Rx Hard Reset receipt detection\r The flag indicates the receipt of valid Hard Reset message. It is cleared by setting the RXHRSTDETCF bit.",
1596 ),
1597 bit_offset: BitOffset::Regular(
1598 RegularBitOffset {
1599 offset: 10,
1600 },
1601 ),
1602 bit_size: 1,
1603 array: None,
1604 enumm: None,
1605 },
1606 Field {
1607 name: "rxovr",
1608 description: Some(
1609 "Rx data overflow detection\r The flag indicates Rx data buffer overflow. It is cleared by setting the RXOVRCF bit.\r The buffer overflow can occur if the received data are not read fast enough.",
1610 ),
1611 bit_offset: BitOffset::Regular(
1612 RegularBitOffset {
1613 offset: 11,
1614 },
1615 ),
1616 bit_size: 1,
1617 array: None,
1618 enumm: None,
1619 },
1620 Field {
1621 name: "rxmsgend",
1622 description: Some(
1623 "Rx message received\r The flag indicates whether a message (except Hard Reset message) has been received, regardless the CRC value. The flag is cleared by setting the RXMSGENDCF bit.\r The RXERR flag set when the RXMSGEND flag goes high indicates errors in the last-received message.",
1624 ),
1625 bit_offset: BitOffset::Regular(
1626 RegularBitOffset {
1627 offset: 12,
1628 },
1629 ),
1630 bit_size: 1,
1631 array: None,
1632 enumm: None,
1633 },
1634 Field {
1635 name: "rxerr",
1636 description: Some(
1637 "Receive message error\r The flag indicates errors of the last Rx message declared (via RXMSGEND), such as incorrect CRC or truncated message (a line becoming static before EOP is met). It is asserted whenever the RXMSGEND flag is set.",
1638 ),
1639 bit_offset: BitOffset::Regular(
1640 RegularBitOffset {
1641 offset: 13,
1642 },
1643 ),
1644 bit_size: 1,
1645 array: None,
1646 enumm: None,
1647 },
1648 Field {
1649 name: "typecevt1",
1650 description: Some(
1651 "Type-C voltage level event on CC1 line\r The flag indicates a change of the TYPEC_VSTATE_CC1[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit.",
1652 ),
1653 bit_offset: BitOffset::Regular(
1654 RegularBitOffset {
1655 offset: 14,
1656 },
1657 ),
1658 bit_size: 1,
1659 array: None,
1660 enumm: None,
1661 },
1662 Field {
1663 name: "typecevt2",
1664 description: Some(
1665 "Type-C voltage level event on CC2 line\r The flag indicates a change of the TYPEC_VSTATE_CC2[1:0] bitfield value, which corresponds to a new Type-C event. It is cleared by setting the TYPECEVT2CF bit.",
1666 ),
1667 bit_offset: BitOffset::Regular(
1668 RegularBitOffset {
1669 offset: 15,
1670 },
1671 ),
1672 bit_size: 1,
1673 array: None,
1674 enumm: None,
1675 },
1676 Field {
1677 name: "typec_vstate_cc1",
1678 description: Some(
1679 "The status bitfield indicates the voltage level on the CC1 line in its steady state.\r The voltage variation on the CC1 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value.",
1680 ),
1681 bit_offset: BitOffset::Regular(
1682 RegularBitOffset {
1683 offset: 16,
1684 },
1685 ),
1686 bit_size: 2,
1687 array: None,
1688 enumm: Some(
1689 "TypecVstateCc",
1690 ),
1691 },
1692 Field {
1693 name: "typec_vstate_cc2",
1694 description: Some(
1695 "CC2 line voltage level\r The status bitfield indicates the voltage level on the CC2 line in its steady state.\r The voltage variation on the CC2 line during USB PD messages due to the BMC PHY modulation does not impact the bitfield value.",
1696 ),
1697 bit_offset: BitOffset::Regular(
1698 RegularBitOffset {
1699 offset: 18,
1700 },
1701 ),
1702 bit_size: 2,
1703 array: None,
1704 enumm: Some(
1705 "TypecVstateCc",
1706 ),
1707 },
1708 Field {
1709 name: "frsevt",
1710 description: Some(
1711 "FRS detection event\r The flag is cleared by setting the FRSEVTCF bit.",
1712 ),
1713 bit_offset: BitOffset::Regular(
1714 RegularBitOffset {
1715 offset: 20,
1716 },
1717 ),
1718 bit_size: 1,
1719 array: None,
1720 enumm: None,
1721 },
1722 ],
1723 },
1724 FieldSet {
1725 name: "TxOrdsetr",
1726 extends: None,
1727 description: Some(
1728 "Tx ordered set type register",
1729 ),
1730 bit_size: 32,
1731 fields: &[
1732 Field {
1733 name: "txordset",
1734 description: Some(
1735 "Ordered set to transmit\r The bitfield determines a full 20-bit sequence to transmit, consisting of four K-codes, each of five bits, defining the packet to transmit. The bit 0 (bit 0 of K-code1) is the first, the bit 19 (bit 4 of K‑code4) the last.",
1736 ),
1737 bit_offset: BitOffset::Regular(
1738 RegularBitOffset {
1739 offset: 0,
1740 },
1741 ),
1742 bit_size: 20,
1743 array: None,
1744 enumm: None,
1745 },
1746 ],
1747 },
1748 FieldSet {
1749 name: "TxPayszr",
1750 extends: None,
1751 description: Some(
1752 "Tx payload size register",
1753 ),
1754 bit_size: 32,
1755 fields: &[
1756 Field {
1757 name: "txpaysz",
1758 description: Some(
1759 "Payload size yet to transmit\r The bitfield is modified by software and by hardware. It contains the number of bytes of a payload (including header but excluding CRC) yet to transmit: each time a data byte is written into the TXDR register, the bitfield value decrements and the TXIS bit is set, except when the bitfield value reaches zero. The enumerated values are standard payload sizes before the start of transmission.",
1760 ),
1761 bit_offset: BitOffset::Regular(
1762 RegularBitOffset {
1763 offset: 0,
1764 },
1765 ),
1766 bit_size: 10,
1767 array: None,
1768 enumm: None,
1769 },
1770 ],
1771 },
1772 FieldSet {
1773 name: "Txdr",
1774 extends: None,
1775 description: Some(
1776 "Tx data register",
1777 ),
1778 bit_size: 32,
1779 fields: &[
1780 Field {
1781 name: "txdata",
1782 description: Some(
1783 "Data byte to transmit",
1784 ),
1785 bit_offset: BitOffset::Regular(
1786 RegularBitOffset {
1787 offset: 0,
1788 },
1789 ),
1790 bit_size: 8,
1791 array: None,
1792 enumm: None,
1793 },
1794 ],
1795 },
1796 ],
1797 enums: &[
1798 Enum {
1799 name: "Anamode",
1800 description: None,
1801 bit_size: 1,
1802 variants: &[
1803 EnumVariant {
1804 name: "SOURCE",
1805 description: Some(
1806 "Source",
1807 ),
1808 value: 0,
1809 },
1810 EnumVariant {
1811 name: "SINK",
1812 description: Some(
1813 "Sink",
1814 ),
1815 value: 1,
1816 },
1817 ],
1818 },
1819 Enum {
1820 name: "Ccenable",
1821 description: None,
1822 bit_size: 2,
1823 variants: &[
1824 EnumVariant {
1825 name: "DISABLED",
1826 description: Some(
1827 "Disable both PHYs",
1828 ),
1829 value: 0,
1830 },
1831 EnumVariant {
1832 name: "CC1",
1833 description: Some(
1834 "Enable CC1 PHY",
1835 ),
1836 value: 1,
1837 },
1838 EnumVariant {
1839 name: "CC2",
1840 description: Some(
1841 "Enable CC2 PHY",
1842 ),
1843 value: 2,
1844 },
1845 EnumVariant {
1846 name: "BOTH",
1847 description: Some(
1848 "Enable CC1 and CC2 PHY",
1849 ),
1850 value: 3,
1851 },
1852 ],
1853 },
1854 Enum {
1855 name: "Phyccsel",
1856 description: None,
1857 bit_size: 1,
1858 variants: &[
1859 EnumVariant {
1860 name: "CC1",
1861 description: Some(
1862 "Use CC1 IO for Power Delivery communication",
1863 ),
1864 value: 0,
1865 },
1866 EnumVariant {
1867 name: "CC2",
1868 description: Some(
1869 "Use CC2 IO for Power Delivery communication",
1870 ),
1871 value: 1,
1872 },
1873 ],
1874 },
1875 Enum {
1876 name: "PscUsbpdclk",
1877 description: None,
1878 bit_size: 3,
1879 variants: &[
1880 EnumVariant {
1881 name: "DIV1",
1882 description: Some(
1883 "1 (bypass)",
1884 ),
1885 value: 0,
1886 },
1887 EnumVariant {
1888 name: "DIV2",
1889 description: Some(
1890 "2",
1891 ),
1892 value: 1,
1893 },
1894 EnumVariant {
1895 name: "DIV4",
1896 description: Some(
1897 "4",
1898 ),
1899 value: 2,
1900 },
1901 EnumVariant {
1902 name: "DIV8",
1903 description: Some(
1904 "8",
1905 ),
1906 value: 3,
1907 },
1908 EnumVariant {
1909 name: "DIV16",
1910 description: Some(
1911 "16",
1912 ),
1913 value: 4,
1914 },
1915 ],
1916 },
1917 Enum {
1918 name: "Rxordset",
1919 description: None,
1920 bit_size: 3,
1921 variants: &[
1922 EnumVariant {
1923 name: "SOP",
1924 description: Some(
1925 "SOP code detected in receiver",
1926 ),
1927 value: 0,
1928 },
1929 EnumVariant {
1930 name: "SOP_PRIME",
1931 description: Some(
1932 "SOP' code detected in receiver",
1933 ),
1934 value: 1,
1935 },
1936 EnumVariant {
1937 name: "SOP_DOUBLE_PRIME",
1938 description: Some(
1939 "SOP'' code detected in receiver",
1940 ),
1941 value: 2,
1942 },
1943 EnumVariant {
1944 name: "SOP_PRIME_DEBUG",
1945 description: Some(
1946 "SOP'_Debug detected in receiver",
1947 ),
1948 value: 3,
1949 },
1950 EnumVariant {
1951 name: "SOP_DOUBLE_PRIME_DEBUG",
1952 description: Some(
1953 "SOP''_Debug detected in receiver",
1954 ),
1955 value: 4,
1956 },
1957 EnumVariant {
1958 name: "CABLE_RESET",
1959 description: Some(
1960 "Cable Reset detected in receiver",
1961 ),
1962 value: 5,
1963 },
1964 EnumVariant {
1965 name: "EXT1",
1966 description: Some(
1967 "SOP extension#1 detected in receiver",
1968 ),
1969 value: 6,
1970 },
1971 EnumVariant {
1972 name: "EXT2",
1973 description: Some(
1974 "SOP extension#2 detected in receiver",
1975 ),
1976 value: 7,
1977 },
1978 ],
1979 },
1980 Enum {
1981 name: "Rxsopkinvalid",
1982 description: None,
1983 bit_size: 3,
1984 variants: &[
1985 EnumVariant {
1986 name: "NONE",
1987 description: Some(
1988 "No K‑code corrupted",
1989 ),
1990 value: 0,
1991 },
1992 EnumVariant {
1993 name: "FIRST",
1994 description: Some(
1995 "First K‑code corrupted",
1996 ),
1997 value: 1,
1998 },
1999 EnumVariant {
2000 name: "SECOND",
2001 description: Some(
2002 "Second K‑code corrupted",
2003 ),
2004 value: 2,
2005 },
2006 EnumVariant {
2007 name: "THIRD",
2008 description: Some(
2009 "Third K‑code corrupted",
2010 ),
2011 value: 3,
2012 },
2013 EnumVariant {
2014 name: "FOURTH",
2015 description: Some(
2016 "Fourth K‑code corrupted",
2017 ),
2018 value: 4,
2019 },
2020 ],
2021 },
2022 Enum {
2023 name: "Txmode",
2024 description: None,
2025 bit_size: 2,
2026 variants: &[
2027 EnumVariant {
2028 name: "PACKET",
2029 description: Some(
2030 "Transmission of Tx packet previously defined in other registers",
2031 ),
2032 value: 0,
2033 },
2034 EnumVariant {
2035 name: "CABLE_RESET",
2036 description: Some(
2037 "Cable Reset sequence",
2038 ),
2039 value: 1,
2040 },
2041 EnumVariant {
2042 name: "BIST",
2043 description: Some(
2044 "BIST test sequence (BIST Carrier Mode 2)",
2045 ),
2046 value: 2,
2047 },
2048 ],
2049 },
2050 Enum {
2051 name: "TypecVstateCc",
2052 description: None,
2053 bit_size: 2,
2054 variants: &[
2055 EnumVariant {
2056 name: "LOWEST",
2057 description: Some(
2058 "Lowest",
2059 ),
2060 value: 0,
2061 },
2062 EnumVariant {
2063 name: "LOW",
2064 description: Some(
2065 "Low",
2066 ),
2067 value: 1,
2068 },
2069 EnumVariant {
2070 name: "HIGH",
2071 description: Some(
2072 "High",
2073 ),
2074 value: 2,
2075 },
2076 EnumVariant {
2077 name: "HIGHEST",
2078 description: Some(
2079 "Highest",
2080 ),
2081 value: 3,
2082 },
2083 ],
2084 },
2085 ],
2086};
2087