1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[
5 Block {
6 name: "Lpuart",
7 extends: None,
8 description: Some(
9 "Low-power Universal synchronous asynchronous receiver transmitter",
10 ),
11 items: &[
12 BlockItem {
13 name: "cr1",
14 description: Some(
15 "Control register 1",
16 ),
17 array: None,
18 byte_offset: 0x0,
19 inner: BlockItemInner::Register(
20 Register {
21 access: Access::ReadWrite,
22 bit_size: 32,
23 fieldset: Some(
24 "Cr1",
25 ),
26 },
27 ),
28 },
29 BlockItem {
30 name: "cr2",
31 description: Some(
32 "Control register 2",
33 ),
34 array: None,
35 byte_offset: 0x4,
36 inner: BlockItemInner::Register(
37 Register {
38 access: Access::ReadWrite,
39 bit_size: 32,
40 fieldset: Some(
41 "Cr2",
42 ),
43 },
44 ),
45 },
46 BlockItem {
47 name: "cr3",
48 description: Some(
49 "Control register 3",
50 ),
51 array: None,
52 byte_offset: 0x8,
53 inner: BlockItemInner::Register(
54 Register {
55 access: Access::ReadWrite,
56 bit_size: 32,
57 fieldset: Some(
58 "Cr3",
59 ),
60 },
61 ),
62 },
63 BlockItem {
64 name: "brr",
65 description: Some(
66 "Baud rate register",
67 ),
68 array: None,
69 byte_offset: 0xc,
70 inner: BlockItemInner::Register(
71 Register {
72 access: Access::ReadWrite,
73 bit_size: 32,
74 fieldset: Some(
75 "Brr",
76 ),
77 },
78 ),
79 },
80 BlockItem {
81 name: "rqr",
82 description: Some(
83 "Request register",
84 ),
85 array: None,
86 byte_offset: 0x18,
87 inner: BlockItemInner::Register(
88 Register {
89 access: Access::Write,
90 bit_size: 32,
91 fieldset: Some(
92 "Rqr",
93 ),
94 },
95 ),
96 },
97 BlockItem {
98 name: "isr",
99 description: Some(
100 "Interrupt & status register",
101 ),
102 array: None,
103 byte_offset: 0x1c,
104 inner: BlockItemInner::Register(
105 Register {
106 access: Access::Read,
107 bit_size: 32,
108 fieldset: Some(
109 "Isr",
110 ),
111 },
112 ),
113 },
114 BlockItem {
115 name: "icr",
116 description: Some(
117 "Interrupt flag clear register",
118 ),
119 array: None,
120 byte_offset: 0x20,
121 inner: BlockItemInner::Register(
122 Register {
123 access: Access::Write,
124 bit_size: 32,
125 fieldset: Some(
126 "Icr",
127 ),
128 },
129 ),
130 },
131 BlockItem {
132 name: "rdr",
133 description: Some(
134 "Receive data register",
135 ),
136 array: None,
137 byte_offset: 0x24,
138 inner: BlockItemInner::Register(
139 Register {
140 access: Access::Read,
141 bit_size: 32,
142 fieldset: Some(
143 "Dr",
144 ),
145 },
146 ),
147 },
148 BlockItem {
149 name: "tdr",
150 description: Some(
151 "Transmit data register",
152 ),
153 array: None,
154 byte_offset: 0x28,
155 inner: BlockItemInner::Register(
156 Register {
157 access: Access::Write,
158 bit_size: 32,
159 fieldset: Some(
160 "Dr",
161 ),
162 },
163 ),
164 },
165 BlockItem {
166 name: "presc",
167 description: Some(
168 "Prescaler register",
169 ),
170 array: None,
171 byte_offset: 0x2c,
172 inner: BlockItemInner::Register(
173 Register {
174 access: Access::ReadWrite,
175 bit_size: 32,
176 fieldset: Some(
177 "Presc",
178 ),
179 },
180 ),
181 },
182 ],
183 },
184 Block {
185 name: "Usart",
186 extends: None,
187 description: Some(
188 "Universal synchronous asynchronous receiver transmitter",
189 ),
190 items: &[
191 BlockItem {
192 name: "cr1",
193 description: Some(
194 "Control register 1",
195 ),
196 array: None,
197 byte_offset: 0x0,
198 inner: BlockItemInner::Register(
199 Register {
200 access: Access::ReadWrite,
201 bit_size: 32,
202 fieldset: Some(
203 "Cr1",
204 ),
205 },
206 ),
207 },
208 BlockItem {
209 name: "cr2",
210 description: Some(
211 "Control register 2",
212 ),
213 array: None,
214 byte_offset: 0x4,
215 inner: BlockItemInner::Register(
216 Register {
217 access: Access::ReadWrite,
218 bit_size: 32,
219 fieldset: Some(
220 "Cr2",
221 ),
222 },
223 ),
224 },
225 BlockItem {
226 name: "cr3",
227 description: Some(
228 "Control register 3",
229 ),
230 array: None,
231 byte_offset: 0x8,
232 inner: BlockItemInner::Register(
233 Register {
234 access: Access::ReadWrite,
235 bit_size: 32,
236 fieldset: Some(
237 "Cr3",
238 ),
239 },
240 ),
241 },
242 BlockItem {
243 name: "brr",
244 description: Some(
245 "Baud rate register",
246 ),
247 array: None,
248 byte_offset: 0xc,
249 inner: BlockItemInner::Register(
250 Register {
251 access: Access::ReadWrite,
252 bit_size: 32,
253 fieldset: Some(
254 "Brr",
255 ),
256 },
257 ),
258 },
259 BlockItem {
260 name: "gtpr",
261 description: Some(
262 "Guard time and prescaler register",
263 ),
264 array: None,
265 byte_offset: 0x10,
266 inner: BlockItemInner::Register(
267 Register {
268 access: Access::ReadWrite,
269 bit_size: 32,
270 fieldset: Some(
271 "Gtpr",
272 ),
273 },
274 ),
275 },
276 BlockItem {
277 name: "rtor",
278 description: Some(
279 "Receiver timeout register",
280 ),
281 array: None,
282 byte_offset: 0x14,
283 inner: BlockItemInner::Register(
284 Register {
285 access: Access::ReadWrite,
286 bit_size: 32,
287 fieldset: Some(
288 "Rtor",
289 ),
290 },
291 ),
292 },
293 BlockItem {
294 name: "rqr",
295 description: Some(
296 "Request register",
297 ),
298 array: None,
299 byte_offset: 0x18,
300 inner: BlockItemInner::Register(
301 Register {
302 access: Access::Write,
303 bit_size: 32,
304 fieldset: Some(
305 "Rqr",
306 ),
307 },
308 ),
309 },
310 BlockItem {
311 name: "isr",
312 description: Some(
313 "Interrupt & status register",
314 ),
315 array: None,
316 byte_offset: 0x1c,
317 inner: BlockItemInner::Register(
318 Register {
319 access: Access::Read,
320 bit_size: 32,
321 fieldset: Some(
322 "Isr",
323 ),
324 },
325 ),
326 },
327 BlockItem {
328 name: "icr",
329 description: Some(
330 "Interrupt flag clear register",
331 ),
332 array: None,
333 byte_offset: 0x20,
334 inner: BlockItemInner::Register(
335 Register {
336 access: Access::Write,
337 bit_size: 32,
338 fieldset: Some(
339 "Icr",
340 ),
341 },
342 ),
343 },
344 BlockItem {
345 name: "rdr",
346 description: Some(
347 "Receive data register",
348 ),
349 array: None,
350 byte_offset: 0x24,
351 inner: BlockItemInner::Register(
352 Register {
353 access: Access::Read,
354 bit_size: 32,
355 fieldset: Some(
356 "Dr",
357 ),
358 },
359 ),
360 },
361 BlockItem {
362 name: "tdr",
363 description: Some(
364 "Transmit data register",
365 ),
366 array: None,
367 byte_offset: 0x28,
368 inner: BlockItemInner::Register(
369 Register {
370 access: Access::Write,
371 bit_size: 32,
372 fieldset: Some(
373 "Dr",
374 ),
375 },
376 ),
377 },
378 BlockItem {
379 name: "presc",
380 description: Some(
381 "Prescaler register",
382 ),
383 array: None,
384 byte_offset: 0x2c,
385 inner: BlockItemInner::Register(
386 Register {
387 access: Access::ReadWrite,
388 bit_size: 32,
389 fieldset: Some(
390 "Presc",
391 ),
392 },
393 ),
394 },
395 ],
396 },
397 ],
398 fieldsets: &[
399 FieldSet {
400 name: "Brr",
401 extends: None,
402 description: Some(
403 "Baud rate register",
404 ),
405 bit_size: 32,
406 fields: &[
407 Field {
408 name: "brr",
409 description: Some(
410 "USARTDIV",
411 ),
412 bit_offset: BitOffset::Regular(
413 RegularBitOffset {
414 offset: 0,
415 },
416 ),
417 bit_size: 16,
418 array: None,
419 enumm: None,
420 },
421 ],
422 },
423 FieldSet {
424 name: "Cr1",
425 extends: None,
426 description: Some(
427 "Control register 1",
428 ),
429 bit_size: 32,
430 fields: &[
431 Field {
432 name: "ue",
433 description: Some(
434 "USART enable",
435 ),
436 bit_offset: BitOffset::Regular(
437 RegularBitOffset {
438 offset: 0,
439 },
440 ),
441 bit_size: 1,
442 array: None,
443 enumm: None,
444 },
445 Field {
446 name: "uesm",
447 description: Some(
448 "USART enable in Stop mode",
449 ),
450 bit_offset: BitOffset::Regular(
451 RegularBitOffset {
452 offset: 1,
453 },
454 ),
455 bit_size: 1,
456 array: None,
457 enumm: None,
458 },
459 Field {
460 name: "re",
461 description: Some(
462 "Receiver enable",
463 ),
464 bit_offset: BitOffset::Regular(
465 RegularBitOffset {
466 offset: 2,
467 },
468 ),
469 bit_size: 1,
470 array: None,
471 enumm: None,
472 },
473 Field {
474 name: "te",
475 description: Some(
476 "Transmitter enable",
477 ),
478 bit_offset: BitOffset::Regular(
479 RegularBitOffset {
480 offset: 3,
481 },
482 ),
483 bit_size: 1,
484 array: None,
485 enumm: None,
486 },
487 Field {
488 name: "idleie",
489 description: Some(
490 "IDLE interrupt enable",
491 ),
492 bit_offset: BitOffset::Regular(
493 RegularBitOffset {
494 offset: 4,
495 },
496 ),
497 bit_size: 1,
498 array: None,
499 enumm: None,
500 },
501 Field {
502 name: "rxneie",
503 description: Some(
504 "RXNE interrupt enable",
505 ),
506 bit_offset: BitOffset::Regular(
507 RegularBitOffset {
508 offset: 5,
509 },
510 ),
511 bit_size: 1,
512 array: None,
513 enumm: None,
514 },
515 Field {
516 name: "tcie",
517 description: Some(
518 "Transmission complete interrupt enable",
519 ),
520 bit_offset: BitOffset::Regular(
521 RegularBitOffset {
522 offset: 6,
523 },
524 ),
525 bit_size: 1,
526 array: None,
527 enumm: None,
528 },
529 Field {
530 name: "txeie",
531 description: Some(
532 "TXE interrupt enable",
533 ),
534 bit_offset: BitOffset::Regular(
535 RegularBitOffset {
536 offset: 7,
537 },
538 ),
539 bit_size: 1,
540 array: None,
541 enumm: None,
542 },
543 Field {
544 name: "peie",
545 description: Some(
546 "PE interrupt enable",
547 ),
548 bit_offset: BitOffset::Regular(
549 RegularBitOffset {
550 offset: 8,
551 },
552 ),
553 bit_size: 1,
554 array: None,
555 enumm: None,
556 },
557 Field {
558 name: "ps",
559 description: Some(
560 "Parity selection",
561 ),
562 bit_offset: BitOffset::Regular(
563 RegularBitOffset {
564 offset: 9,
565 },
566 ),
567 bit_size: 1,
568 array: None,
569 enumm: Some(
570 "Ps",
571 ),
572 },
573 Field {
574 name: "pce",
575 description: Some(
576 "Parity control enable",
577 ),
578 bit_offset: BitOffset::Regular(
579 RegularBitOffset {
580 offset: 10,
581 },
582 ),
583 bit_size: 1,
584 array: None,
585 enumm: None,
586 },
587 Field {
588 name: "wake",
589 description: Some(
590 "Receiver wakeup method",
591 ),
592 bit_offset: BitOffset::Regular(
593 RegularBitOffset {
594 offset: 11,
595 },
596 ),
597 bit_size: 1,
598 array: None,
599 enumm: Some(
600 "Wake",
601 ),
602 },
603 Field {
604 name: "m0",
605 description: Some(
606 "Word length",
607 ),
608 bit_offset: BitOffset::Regular(
609 RegularBitOffset {
610 offset: 12,
611 },
612 ),
613 bit_size: 1,
614 array: None,
615 enumm: Some(
616 "M0",
617 ),
618 },
619 Field {
620 name: "mme",
621 description: Some(
622 "Mute mode enable",
623 ),
624 bit_offset: BitOffset::Regular(
625 RegularBitOffset {
626 offset: 13,
627 },
628 ),
629 bit_size: 1,
630 array: None,
631 enumm: None,
632 },
633 Field {
634 name: "cmie",
635 description: Some(
636 "Character match interrupt enable",
637 ),
638 bit_offset: BitOffset::Regular(
639 RegularBitOffset {
640 offset: 14,
641 },
642 ),
643 bit_size: 1,
644 array: None,
645 enumm: None,
646 },
647 Field {
648 name: "over8",
649 description: Some(
650 "Oversampling mode",
651 ),
652 bit_offset: BitOffset::Regular(
653 RegularBitOffset {
654 offset: 15,
655 },
656 ),
657 bit_size: 1,
658 array: None,
659 enumm: Some(
660 "Over8",
661 ),
662 },
663 Field {
664 name: "dedt",
665 description: Some(
666 "Driver Enable deassertion time",
667 ),
668 bit_offset: BitOffset::Regular(
669 RegularBitOffset {
670 offset: 16,
671 },
672 ),
673 bit_size: 5,
674 array: None,
675 enumm: None,
676 },
677 Field {
678 name: "deat",
679 description: Some(
680 "Driver Enable assertion time",
681 ),
682 bit_offset: BitOffset::Regular(
683 RegularBitOffset {
684 offset: 21,
685 },
686 ),
687 bit_size: 5,
688 array: None,
689 enumm: None,
690 },
691 Field {
692 name: "rtoie",
693 description: Some(
694 "Receiver timeout interrupt enable",
695 ),
696 bit_offset: BitOffset::Regular(
697 RegularBitOffset {
698 offset: 26,
699 },
700 ),
701 bit_size: 1,
702 array: None,
703 enumm: None,
704 },
705 Field {
706 name: "eobie",
707 description: Some(
708 "End of Block interrupt enable",
709 ),
710 bit_offset: BitOffset::Regular(
711 RegularBitOffset {
712 offset: 27,
713 },
714 ),
715 bit_size: 1,
716 array: None,
717 enumm: None,
718 },
719 Field {
720 name: "m1",
721 description: Some(
722 "Word length",
723 ),
724 bit_offset: BitOffset::Regular(
725 RegularBitOffset {
726 offset: 28,
727 },
728 ),
729 bit_size: 1,
730 array: None,
731 enumm: Some(
732 "M1",
733 ),
734 },
735 Field {
736 name: "fifoen",
737 description: Some(
738 "FIFO mode enable",
739 ),
740 bit_offset: BitOffset::Regular(
741 RegularBitOffset {
742 offset: 29,
743 },
744 ),
745 bit_size: 1,
746 array: None,
747 enumm: None,
748 },
749 Field {
750 name: "txfeie",
751 description: Some(
752 "TXFIFO empty interrupt enable",
753 ),
754 bit_offset: BitOffset::Regular(
755 RegularBitOffset {
756 offset: 30,
757 },
758 ),
759 bit_size: 1,
760 array: None,
761 enumm: None,
762 },
763 Field {
764 name: "rxffie",
765 description: Some(
766 "RXFIFO Full interrupt enable",
767 ),
768 bit_offset: BitOffset::Regular(
769 RegularBitOffset {
770 offset: 31,
771 },
772 ),
773 bit_size: 1,
774 array: None,
775 enumm: None,
776 },
777 ],
778 },
779 FieldSet {
780 name: "Cr2",
781 extends: None,
782 description: Some(
783 "Control register 2",
784 ),
785 bit_size: 32,
786 fields: &[
787 Field {
788 name: "addm",
789 description: Some(
790 "7-bit Address Detection/4-bit Address Detection",
791 ),
792 bit_offset: BitOffset::Regular(
793 RegularBitOffset {
794 offset: 4,
795 },
796 ),
797 bit_size: 1,
798 array: None,
799 enumm: Some(
800 "Addm",
801 ),
802 },
803 Field {
804 name: "lbdl",
805 description: Some(
806 "Line break detection length",
807 ),
808 bit_offset: BitOffset::Regular(
809 RegularBitOffset {
810 offset: 5,
811 },
812 ),
813 bit_size: 1,
814 array: None,
815 enumm: Some(
816 "Lbdl",
817 ),
818 },
819 Field {
820 name: "lbdie",
821 description: Some(
822 "LIN break detection interrupt enable",
823 ),
824 bit_offset: BitOffset::Regular(
825 RegularBitOffset {
826 offset: 6,
827 },
828 ),
829 bit_size: 1,
830 array: None,
831 enumm: None,
832 },
833 Field {
834 name: "lbcl",
835 description: Some(
836 "Last bit clock pulse",
837 ),
838 bit_offset: BitOffset::Regular(
839 RegularBitOffset {
840 offset: 8,
841 },
842 ),
843 bit_size: 1,
844 array: None,
845 enumm: None,
846 },
847 Field {
848 name: "cpha",
849 description: Some(
850 "Clock phase",
851 ),
852 bit_offset: BitOffset::Regular(
853 RegularBitOffset {
854 offset: 9,
855 },
856 ),
857 bit_size: 1,
858 array: None,
859 enumm: Some(
860 "Cpha",
861 ),
862 },
863 Field {
864 name: "cpol",
865 description: Some(
866 "Clock polarity",
867 ),
868 bit_offset: BitOffset::Regular(
869 RegularBitOffset {
870 offset: 10,
871 },
872 ),
873 bit_size: 1,
874 array: None,
875 enumm: Some(
876 "Cpol",
877 ),
878 },
879 Field {
880 name: "clken",
881 description: Some(
882 "Clock enable",
883 ),
884 bit_offset: BitOffset::Regular(
885 RegularBitOffset {
886 offset: 11,
887 },
888 ),
889 bit_size: 1,
890 array: None,
891 enumm: None,
892 },
893 Field {
894 name: "stop",
895 description: Some(
896 "STOP bits",
897 ),
898 bit_offset: BitOffset::Regular(
899 RegularBitOffset {
900 offset: 12,
901 },
902 ),
903 bit_size: 2,
904 array: None,
905 enumm: Some(
906 "Stop",
907 ),
908 },
909 Field {
910 name: "linen",
911 description: Some(
912 "LIN mode enable",
913 ),
914 bit_offset: BitOffset::Regular(
915 RegularBitOffset {
916 offset: 14,
917 },
918 ),
919 bit_size: 1,
920 array: None,
921 enumm: None,
922 },
923 Field {
924 name: "swap",
925 description: Some(
926 "Swap TX/RX pins",
927 ),
928 bit_offset: BitOffset::Regular(
929 RegularBitOffset {
930 offset: 15,
931 },
932 ),
933 bit_size: 1,
934 array: None,
935 enumm: None,
936 },
937 Field {
938 name: "rxinv",
939 description: Some(
940 "RX pin active level inversion",
941 ),
942 bit_offset: BitOffset::Regular(
943 RegularBitOffset {
944 offset: 16,
945 },
946 ),
947 bit_size: 1,
948 array: None,
949 enumm: None,
950 },
951 Field {
952 name: "txinv",
953 description: Some(
954 "TX pin active level inversion",
955 ),
956 bit_offset: BitOffset::Regular(
957 RegularBitOffset {
958 offset: 17,
959 },
960 ),
961 bit_size: 1,
962 array: None,
963 enumm: None,
964 },
965 Field {
966 name: "datainv",
967 description: Some(
968 "Binary data inversion",
969 ),
970 bit_offset: BitOffset::Regular(
971 RegularBitOffset {
972 offset: 18,
973 },
974 ),
975 bit_size: 1,
976 array: None,
977 enumm: None,
978 },
979 Field {
980 name: "msbfirst",
981 description: Some(
982 "Most significant bit first",
983 ),
984 bit_offset: BitOffset::Regular(
985 RegularBitOffset {
986 offset: 19,
987 },
988 ),
989 bit_size: 1,
990 array: None,
991 enumm: Some(
992 "Msbfirst",
993 ),
994 },
995 Field {
996 name: "abren",
997 description: Some(
998 "Auto baud rate enable",
999 ),
1000 bit_offset: BitOffset::Regular(
1001 RegularBitOffset {
1002 offset: 20,
1003 },
1004 ),
1005 bit_size: 1,
1006 array: None,
1007 enumm: None,
1008 },
1009 Field {
1010 name: "abrmod",
1011 description: Some(
1012 "Auto baud rate mode",
1013 ),
1014 bit_offset: BitOffset::Regular(
1015 RegularBitOffset {
1016 offset: 21,
1017 },
1018 ),
1019 bit_size: 2,
1020 array: None,
1021 enumm: Some(
1022 "Abrmod",
1023 ),
1024 },
1025 Field {
1026 name: "rtoen",
1027 description: Some(
1028 "Receiver timeout enable",
1029 ),
1030 bit_offset: BitOffset::Regular(
1031 RegularBitOffset {
1032 offset: 23,
1033 },
1034 ),
1035 bit_size: 1,
1036 array: None,
1037 enumm: None,
1038 },
1039 Field {
1040 name: "add",
1041 description: Some(
1042 "Address of the USART node",
1043 ),
1044 bit_offset: BitOffset::Regular(
1045 RegularBitOffset {
1046 offset: 24,
1047 },
1048 ),
1049 bit_size: 8,
1050 array: None,
1051 enumm: None,
1052 },
1053 ],
1054 },
1055 FieldSet {
1056 name: "Cr3",
1057 extends: None,
1058 description: Some(
1059 "Control register 3",
1060 ),
1061 bit_size: 32,
1062 fields: &[
1063 Field {
1064 name: "eie",
1065 description: Some(
1066 "Error interrupt enable",
1067 ),
1068 bit_offset: BitOffset::Regular(
1069 RegularBitOffset {
1070 offset: 0,
1071 },
1072 ),
1073 bit_size: 1,
1074 array: None,
1075 enumm: None,
1076 },
1077 Field {
1078 name: "iren",
1079 description: Some(
1080 "IrDA mode enable",
1081 ),
1082 bit_offset: BitOffset::Regular(
1083 RegularBitOffset {
1084 offset: 1,
1085 },
1086 ),
1087 bit_size: 1,
1088 array: None,
1089 enumm: None,
1090 },
1091 Field {
1092 name: "irlp",
1093 description: Some(
1094 "IrDA low-power",
1095 ),
1096 bit_offset: BitOffset::Regular(
1097 RegularBitOffset {
1098 offset: 2,
1099 },
1100 ),
1101 bit_size: 1,
1102 array: None,
1103 enumm: Some(
1104 "Irlp",
1105 ),
1106 },
1107 Field {
1108 name: "hdsel",
1109 description: Some(
1110 "Half-duplex selection",
1111 ),
1112 bit_offset: BitOffset::Regular(
1113 RegularBitOffset {
1114 offset: 3,
1115 },
1116 ),
1117 bit_size: 1,
1118 array: None,
1119 enumm: None,
1120 },
1121 Field {
1122 name: "nack",
1123 description: Some(
1124 "Smartcard NACK enable",
1125 ),
1126 bit_offset: BitOffset::Regular(
1127 RegularBitOffset {
1128 offset: 4,
1129 },
1130 ),
1131 bit_size: 1,
1132 array: None,
1133 enumm: None,
1134 },
1135 Field {
1136 name: "scen",
1137 description: Some(
1138 "Smartcard mode enable",
1139 ),
1140 bit_offset: BitOffset::Regular(
1141 RegularBitOffset {
1142 offset: 5,
1143 },
1144 ),
1145 bit_size: 1,
1146 array: None,
1147 enumm: None,
1148 },
1149 Field {
1150 name: "dmar",
1151 description: Some(
1152 "DMA enable receiver",
1153 ),
1154 bit_offset: BitOffset::Regular(
1155 RegularBitOffset {
1156 offset: 6,
1157 },
1158 ),
1159 bit_size: 1,
1160 array: None,
1161 enumm: None,
1162 },
1163 Field {
1164 name: "dmat",
1165 description: Some(
1166 "DMA enable transmitter",
1167 ),
1168 bit_offset: BitOffset::Regular(
1169 RegularBitOffset {
1170 offset: 7,
1171 },
1172 ),
1173 bit_size: 1,
1174 array: None,
1175 enumm: None,
1176 },
1177 Field {
1178 name: "rtse",
1179 description: Some(
1180 "RTS enable",
1181 ),
1182 bit_offset: BitOffset::Regular(
1183 RegularBitOffset {
1184 offset: 8,
1185 },
1186 ),
1187 bit_size: 1,
1188 array: None,
1189 enumm: None,
1190 },
1191 Field {
1192 name: "ctse",
1193 description: Some(
1194 "CTS enable",
1195 ),
1196 bit_offset: BitOffset::Regular(
1197 RegularBitOffset {
1198 offset: 9,
1199 },
1200 ),
1201 bit_size: 1,
1202 array: None,
1203 enumm: None,
1204 },
1205 Field {
1206 name: "ctsie",
1207 description: Some(
1208 "CTS interrupt enable",
1209 ),
1210 bit_offset: BitOffset::Regular(
1211 RegularBitOffset {
1212 offset: 10,
1213 },
1214 ),
1215 bit_size: 1,
1216 array: None,
1217 enumm: None,
1218 },
1219 Field {
1220 name: "onebit",
1221 description: Some(
1222 "One sample bit method enable",
1223 ),
1224 bit_offset: BitOffset::Regular(
1225 RegularBitOffset {
1226 offset: 11,
1227 },
1228 ),
1229 bit_size: 1,
1230 array: None,
1231 enumm: None,
1232 },
1233 Field {
1234 name: "ovrdis",
1235 description: Some(
1236 "Overrun Disable",
1237 ),
1238 bit_offset: BitOffset::Regular(
1239 RegularBitOffset {
1240 offset: 12,
1241 },
1242 ),
1243 bit_size: 1,
1244 array: None,
1245 enumm: None,
1246 },
1247 Field {
1248 name: "ddre",
1249 description: Some(
1250 "DMA Disable on Reception Error",
1251 ),
1252 bit_offset: BitOffset::Regular(
1253 RegularBitOffset {
1254 offset: 13,
1255 },
1256 ),
1257 bit_size: 1,
1258 array: None,
1259 enumm: None,
1260 },
1261 Field {
1262 name: "dem",
1263 description: Some(
1264 "Driver enable mode",
1265 ),
1266 bit_offset: BitOffset::Regular(
1267 RegularBitOffset {
1268 offset: 14,
1269 },
1270 ),
1271 bit_size: 1,
1272 array: None,
1273 enumm: None,
1274 },
1275 Field {
1276 name: "dep",
1277 description: Some(
1278 "Driver enable polarity selection",
1279 ),
1280 bit_offset: BitOffset::Regular(
1281 RegularBitOffset {
1282 offset: 15,
1283 },
1284 ),
1285 bit_size: 1,
1286 array: None,
1287 enumm: Some(
1288 "Dep",
1289 ),
1290 },
1291 Field {
1292 name: "scarcnt",
1293 description: Some(
1294 "Smartcard auto-retry count",
1295 ),
1296 bit_offset: BitOffset::Regular(
1297 RegularBitOffset {
1298 offset: 17,
1299 },
1300 ),
1301 bit_size: 3,
1302 array: None,
1303 enumm: None,
1304 },
1305 Field {
1306 name: "wus",
1307 description: Some(
1308 "Wakeup from Stop mode interrupt flag selection",
1309 ),
1310 bit_offset: BitOffset::Regular(
1311 RegularBitOffset {
1312 offset: 20,
1313 },
1314 ),
1315 bit_size: 2,
1316 array: None,
1317 enumm: Some(
1318 "Wus",
1319 ),
1320 },
1321 Field {
1322 name: "wufie",
1323 description: Some(
1324 "Wakeup from Stop mode interrupt enable",
1325 ),
1326 bit_offset: BitOffset::Regular(
1327 RegularBitOffset {
1328 offset: 22,
1329 },
1330 ),
1331 bit_size: 1,
1332 array: None,
1333 enumm: None,
1334 },
1335 Field {
1336 name: "txftie",
1337 description: Some(
1338 "TXFIFO threshold interrupt enable",
1339 ),
1340 bit_offset: BitOffset::Regular(
1341 RegularBitOffset {
1342 offset: 23,
1343 },
1344 ),
1345 bit_size: 1,
1346 array: None,
1347 enumm: None,
1348 },
1349 Field {
1350 name: "rxftcfg",
1351 description: Some(
1352 "Receive FIFO threshold configuration",
1353 ),
1354 bit_offset: BitOffset::Regular(
1355 RegularBitOffset {
1356 offset: 25,
1357 },
1358 ),
1359 bit_size: 3,
1360 array: None,
1361 enumm: None,
1362 },
1363 Field {
1364 name: "rxftie",
1365 description: Some(
1366 "RXFIFO threshold interrupt enable",
1367 ),
1368 bit_offset: BitOffset::Regular(
1369 RegularBitOffset {
1370 offset: 28,
1371 },
1372 ),
1373 bit_size: 1,
1374 array: None,
1375 enumm: None,
1376 },
1377 Field {
1378 name: "txftcfg",
1379 description: Some(
1380 "TXFIFO threshold configuration",
1381 ),
1382 bit_offset: BitOffset::Regular(
1383 RegularBitOffset {
1384 offset: 29,
1385 },
1386 ),
1387 bit_size: 3,
1388 array: None,
1389 enumm: None,
1390 },
1391 ],
1392 },
1393 FieldSet {
1394 name: "Dr",
1395 extends: None,
1396 description: Some(
1397 "Data register",
1398 ),
1399 bit_size: 32,
1400 fields: &[
1401 Field {
1402 name: "dr",
1403 description: Some(
1404 "Data value",
1405 ),
1406 bit_offset: BitOffset::Regular(
1407 RegularBitOffset {
1408 offset: 0,
1409 },
1410 ),
1411 bit_size: 9,
1412 array: None,
1413 enumm: None,
1414 },
1415 ],
1416 },
1417 FieldSet {
1418 name: "Gtpr",
1419 extends: None,
1420 description: Some(
1421 "Guard time and prescaler register",
1422 ),
1423 bit_size: 32,
1424 fields: &[
1425 Field {
1426 name: "psc",
1427 description: Some(
1428 "Prescaler value",
1429 ),
1430 bit_offset: BitOffset::Regular(
1431 RegularBitOffset {
1432 offset: 0,
1433 },
1434 ),
1435 bit_size: 8,
1436 array: None,
1437 enumm: None,
1438 },
1439 Field {
1440 name: "gt",
1441 description: Some(
1442 "Guard time value",
1443 ),
1444 bit_offset: BitOffset::Regular(
1445 RegularBitOffset {
1446 offset: 8,
1447 },
1448 ),
1449 bit_size: 8,
1450 array: None,
1451 enumm: None,
1452 },
1453 ],
1454 },
1455 FieldSet {
1456 name: "Icr",
1457 extends: None,
1458 description: Some(
1459 "Interrupt flag clear register",
1460 ),
1461 bit_size: 32,
1462 fields: &[
1463 Field {
1464 name: "pe",
1465 description: Some(
1466 "Parity error clear flag",
1467 ),
1468 bit_offset: BitOffset::Regular(
1469 RegularBitOffset {
1470 offset: 0,
1471 },
1472 ),
1473 bit_size: 1,
1474 array: None,
1475 enumm: None,
1476 },
1477 Field {
1478 name: "fe",
1479 description: Some(
1480 "Framing error clear flag",
1481 ),
1482 bit_offset: BitOffset::Regular(
1483 RegularBitOffset {
1484 offset: 1,
1485 },
1486 ),
1487 bit_size: 1,
1488 array: None,
1489 enumm: None,
1490 },
1491 Field {
1492 name: "ne",
1493 description: Some(
1494 "Noise error clear flag",
1495 ),
1496 bit_offset: BitOffset::Regular(
1497 RegularBitOffset {
1498 offset: 2,
1499 },
1500 ),
1501 bit_size: 1,
1502 array: None,
1503 enumm: None,
1504 },
1505 Field {
1506 name: "ore",
1507 description: Some(
1508 "Overrun error clear flag",
1509 ),
1510 bit_offset: BitOffset::Regular(
1511 RegularBitOffset {
1512 offset: 3,
1513 },
1514 ),
1515 bit_size: 1,
1516 array: None,
1517 enumm: None,
1518 },
1519 Field {
1520 name: "idle",
1521 description: Some(
1522 "Idle line detected clear flag",
1523 ),
1524 bit_offset: BitOffset::Regular(
1525 RegularBitOffset {
1526 offset: 4,
1527 },
1528 ),
1529 bit_size: 1,
1530 array: None,
1531 enumm: None,
1532 },
1533 Field {
1534 name: "tc",
1535 description: Some(
1536 "Transmission complete clear flag",
1537 ),
1538 bit_offset: BitOffset::Regular(
1539 RegularBitOffset {
1540 offset: 6,
1541 },
1542 ),
1543 bit_size: 1,
1544 array: None,
1545 enumm: None,
1546 },
1547 Field {
1548 name: "lbd",
1549 description: Some(
1550 "LIN break detection clear flag",
1551 ),
1552 bit_offset: BitOffset::Regular(
1553 RegularBitOffset {
1554 offset: 8,
1555 },
1556 ),
1557 bit_size: 1,
1558 array: None,
1559 enumm: None,
1560 },
1561 Field {
1562 name: "cts",
1563 description: Some(
1564 "CTS clear flag",
1565 ),
1566 bit_offset: BitOffset::Regular(
1567 RegularBitOffset {
1568 offset: 9,
1569 },
1570 ),
1571 bit_size: 1,
1572 array: None,
1573 enumm: None,
1574 },
1575 Field {
1576 name: "rtof",
1577 description: Some(
1578 "Receiver timeout clear flag",
1579 ),
1580 bit_offset: BitOffset::Regular(
1581 RegularBitOffset {
1582 offset: 11,
1583 },
1584 ),
1585 bit_size: 1,
1586 array: None,
1587 enumm: None,
1588 },
1589 Field {
1590 name: "eobf",
1591 description: Some(
1592 "End of block clear flag",
1593 ),
1594 bit_offset: BitOffset::Regular(
1595 RegularBitOffset {
1596 offset: 12,
1597 },
1598 ),
1599 bit_size: 1,
1600 array: None,
1601 enumm: None,
1602 },
1603 Field {
1604 name: "cmf",
1605 description: Some(
1606 "Character match clear flag",
1607 ),
1608 bit_offset: BitOffset::Regular(
1609 RegularBitOffset {
1610 offset: 17,
1611 },
1612 ),
1613 bit_size: 1,
1614 array: None,
1615 enumm: None,
1616 },
1617 Field {
1618 name: "wuf",
1619 description: Some(
1620 "Wakeup from Stop mode clear flag",
1621 ),
1622 bit_offset: BitOffset::Regular(
1623 RegularBitOffset {
1624 offset: 20,
1625 },
1626 ),
1627 bit_size: 1,
1628 array: None,
1629 enumm: None,
1630 },
1631 ],
1632 },
1633 FieldSet {
1634 name: "Isr",
1635 extends: None,
1636 description: Some(
1637 "Interrupt & status register",
1638 ),
1639 bit_size: 32,
1640 fields: &[
1641 Field {
1642 name: "pe",
1643 description: Some(
1644 "Parity error",
1645 ),
1646 bit_offset: BitOffset::Regular(
1647 RegularBitOffset {
1648 offset: 0,
1649 },
1650 ),
1651 bit_size: 1,
1652 array: None,
1653 enumm: None,
1654 },
1655 Field {
1656 name: "fe",
1657 description: Some(
1658 "Framing error",
1659 ),
1660 bit_offset: BitOffset::Regular(
1661 RegularBitOffset {
1662 offset: 1,
1663 },
1664 ),
1665 bit_size: 1,
1666 array: None,
1667 enumm: None,
1668 },
1669 Field {
1670 name: "ne",
1671 description: Some(
1672 "Noise error flag",
1673 ),
1674 bit_offset: BitOffset::Regular(
1675 RegularBitOffset {
1676 offset: 2,
1677 },
1678 ),
1679 bit_size: 1,
1680 array: None,
1681 enumm: None,
1682 },
1683 Field {
1684 name: "ore",
1685 description: Some(
1686 "Overrun error",
1687 ),
1688 bit_offset: BitOffset::Regular(
1689 RegularBitOffset {
1690 offset: 3,
1691 },
1692 ),
1693 bit_size: 1,
1694 array: None,
1695 enumm: None,
1696 },
1697 Field {
1698 name: "idle",
1699 description: Some(
1700 "Idle line detected",
1701 ),
1702 bit_offset: BitOffset::Regular(
1703 RegularBitOffset {
1704 offset: 4,
1705 },
1706 ),
1707 bit_size: 1,
1708 array: None,
1709 enumm: None,
1710 },
1711 Field {
1712 name: "rxne",
1713 description: Some(
1714 "Read data register not empty",
1715 ),
1716 bit_offset: BitOffset::Regular(
1717 RegularBitOffset {
1718 offset: 5,
1719 },
1720 ),
1721 bit_size: 1,
1722 array: None,
1723 enumm: None,
1724 },
1725 Field {
1726 name: "tc",
1727 description: Some(
1728 "Transmission complete",
1729 ),
1730 bit_offset: BitOffset::Regular(
1731 RegularBitOffset {
1732 offset: 6,
1733 },
1734 ),
1735 bit_size: 1,
1736 array: None,
1737 enumm: None,
1738 },
1739 Field {
1740 name: "txe",
1741 description: Some(
1742 "Transmit data register empty",
1743 ),
1744 bit_offset: BitOffset::Regular(
1745 RegularBitOffset {
1746 offset: 7,
1747 },
1748 ),
1749 bit_size: 1,
1750 array: None,
1751 enumm: None,
1752 },
1753 Field {
1754 name: "lbd",
1755 description: Some(
1756 "LIN break detection flag",
1757 ),
1758 bit_offset: BitOffset::Regular(
1759 RegularBitOffset {
1760 offset: 8,
1761 },
1762 ),
1763 bit_size: 1,
1764 array: None,
1765 enumm: None,
1766 },
1767 Field {
1768 name: "ctsif",
1769 description: Some(
1770 "CTS interrupt flag",
1771 ),
1772 bit_offset: BitOffset::Regular(
1773 RegularBitOffset {
1774 offset: 9,
1775 },
1776 ),
1777 bit_size: 1,
1778 array: None,
1779 enumm: None,
1780 },
1781 Field {
1782 name: "cts",
1783 description: Some(
1784 "CTS flag",
1785 ),
1786 bit_offset: BitOffset::Regular(
1787 RegularBitOffset {
1788 offset: 10,
1789 },
1790 ),
1791 bit_size: 1,
1792 array: None,
1793 enumm: None,
1794 },
1795 Field {
1796 name: "rtof",
1797 description: Some(
1798 "Receiver timeout",
1799 ),
1800 bit_offset: BitOffset::Regular(
1801 RegularBitOffset {
1802 offset: 11,
1803 },
1804 ),
1805 bit_size: 1,
1806 array: None,
1807 enumm: None,
1808 },
1809 Field {
1810 name: "eobf",
1811 description: Some(
1812 "End of block flag",
1813 ),
1814 bit_offset: BitOffset::Regular(
1815 RegularBitOffset {
1816 offset: 12,
1817 },
1818 ),
1819 bit_size: 1,
1820 array: None,
1821 enumm: None,
1822 },
1823 Field {
1824 name: "abre",
1825 description: Some(
1826 "Auto baud rate error",
1827 ),
1828 bit_offset: BitOffset::Regular(
1829 RegularBitOffset {
1830 offset: 14,
1831 },
1832 ),
1833 bit_size: 1,
1834 array: None,
1835 enumm: None,
1836 },
1837 Field {
1838 name: "abrf",
1839 description: Some(
1840 "Auto baud rate flag",
1841 ),
1842 bit_offset: BitOffset::Regular(
1843 RegularBitOffset {
1844 offset: 15,
1845 },
1846 ),
1847 bit_size: 1,
1848 array: None,
1849 enumm: None,
1850 },
1851 Field {
1852 name: "busy",
1853 description: Some(
1854 "Busy flag",
1855 ),
1856 bit_offset: BitOffset::Regular(
1857 RegularBitOffset {
1858 offset: 16,
1859 },
1860 ),
1861 bit_size: 1,
1862 array: None,
1863 enumm: None,
1864 },
1865 Field {
1866 name: "cmf",
1867 description: Some(
1868 "character match flag",
1869 ),
1870 bit_offset: BitOffset::Regular(
1871 RegularBitOffset {
1872 offset: 17,
1873 },
1874 ),
1875 bit_size: 1,
1876 array: None,
1877 enumm: None,
1878 },
1879 Field {
1880 name: "sbkf",
1881 description: Some(
1882 "Send break flag",
1883 ),
1884 bit_offset: BitOffset::Regular(
1885 RegularBitOffset {
1886 offset: 18,
1887 },
1888 ),
1889 bit_size: 1,
1890 array: None,
1891 enumm: None,
1892 },
1893 Field {
1894 name: "rwu",
1895 description: Some(
1896 "Receiver wakeup from Mute mode",
1897 ),
1898 bit_offset: BitOffset::Regular(
1899 RegularBitOffset {
1900 offset: 19,
1901 },
1902 ),
1903 bit_size: 1,
1904 array: None,
1905 enumm: Some(
1906 "Rwu",
1907 ),
1908 },
1909 Field {
1910 name: "wuf",
1911 description: Some(
1912 "Wakeup from Stop mode flag",
1913 ),
1914 bit_offset: BitOffset::Regular(
1915 RegularBitOffset {
1916 offset: 20,
1917 },
1918 ),
1919 bit_size: 1,
1920 array: None,
1921 enumm: None,
1922 },
1923 Field {
1924 name: "teack",
1925 description: Some(
1926 "Transmit enable acknowledge flag",
1927 ),
1928 bit_offset: BitOffset::Regular(
1929 RegularBitOffset {
1930 offset: 21,
1931 },
1932 ),
1933 bit_size: 1,
1934 array: None,
1935 enumm: None,
1936 },
1937 Field {
1938 name: "reack",
1939 description: Some(
1940 "Receive enable acknowledge flag",
1941 ),
1942 bit_offset: BitOffset::Regular(
1943 RegularBitOffset {
1944 offset: 22,
1945 },
1946 ),
1947 bit_size: 1,
1948 array: None,
1949 enumm: None,
1950 },
1951 Field {
1952 name: "txfe",
1953 description: Some(
1954 "TXFIFO Empty",
1955 ),
1956 bit_offset: BitOffset::Regular(
1957 RegularBitOffset {
1958 offset: 23,
1959 },
1960 ),
1961 bit_size: 1,
1962 array: None,
1963 enumm: None,
1964 },
1965 Field {
1966 name: "rxff",
1967 description: Some(
1968 "RXFIFO Full",
1969 ),
1970 bit_offset: BitOffset::Regular(
1971 RegularBitOffset {
1972 offset: 24,
1973 },
1974 ),
1975 bit_size: 1,
1976 array: None,
1977 enumm: None,
1978 },
1979 Field {
1980 name: "rxft",
1981 description: Some(
1982 "RXFIFO threshold flag",
1983 ),
1984 bit_offset: BitOffset::Regular(
1985 RegularBitOffset {
1986 offset: 26,
1987 },
1988 ),
1989 bit_size: 1,
1990 array: None,
1991 enumm: None,
1992 },
1993 Field {
1994 name: "txft",
1995 description: Some(
1996 "TXFIFO threshold flag",
1997 ),
1998 bit_offset: BitOffset::Regular(
1999 RegularBitOffset {
2000 offset: 27,
2001 },
2002 ),
2003 bit_size: 1,
2004 array: None,
2005 enumm: None,
2006 },
2007 ],
2008 },
2009 FieldSet {
2010 name: "Presc",
2011 extends: None,
2012 description: Some(
2013 "Prescaler register",
2014 ),
2015 bit_size: 32,
2016 fields: &[
2017 Field {
2018 name: "prescaler",
2019 description: Some(
2020 "Clock prescaler",
2021 ),
2022 bit_offset: BitOffset::Regular(
2023 RegularBitOffset {
2024 offset: 0,
2025 },
2026 ),
2027 bit_size: 4,
2028 array: None,
2029 enumm: Some(
2030 "Presc",
2031 ),
2032 },
2033 ],
2034 },
2035 FieldSet {
2036 name: "Rqr",
2037 extends: None,
2038 description: Some(
2039 "Request register",
2040 ),
2041 bit_size: 32,
2042 fields: &[
2043 Field {
2044 name: "abrrq",
2045 description: Some(
2046 "Auto baud rate request. Resets the ABRF flag in the USART_ISR and request an automatic baud rate measurement on the next received data frame.",
2047 ),
2048 bit_offset: BitOffset::Regular(
2049 RegularBitOffset {
2050 offset: 0,
2051 },
2052 ),
2053 bit_size: 1,
2054 array: None,
2055 enumm: None,
2056 },
2057 Field {
2058 name: "sbkrq",
2059 description: Some(
2060 "Send break request. Sets the SBKF flag and request to send a BREAK on the line, as soon as the transmit machine is available",
2061 ),
2062 bit_offset: BitOffset::Regular(
2063 RegularBitOffset {
2064 offset: 1,
2065 },
2066 ),
2067 bit_size: 1,
2068 array: None,
2069 enumm: None,
2070 },
2071 Field {
2072 name: "mmrq",
2073 description: Some(
2074 "Mute mode request. Puts the USART in mute mode and sets the RWU flag.",
2075 ),
2076 bit_offset: BitOffset::Regular(
2077 RegularBitOffset {
2078 offset: 2,
2079 },
2080 ),
2081 bit_size: 1,
2082 array: None,
2083 enumm: None,
2084 },
2085 Field {
2086 name: "rxfrq",
2087 description: Some(
2088 "Receive data flush request. Clears the RXNE flag. This allows to discard the received data without reading it, and avoid an overrun condition",
2089 ),
2090 bit_offset: BitOffset::Regular(
2091 RegularBitOffset {
2092 offset: 3,
2093 },
2094 ),
2095 bit_size: 1,
2096 array: None,
2097 enumm: None,
2098 },
2099 Field {
2100 name: "txfrq",
2101 description: Some(
2102 "Transmit data flush request. Sets the TXE flags. This allows to discard the transmit data.",
2103 ),
2104 bit_offset: BitOffset::Regular(
2105 RegularBitOffset {
2106 offset: 4,
2107 },
2108 ),
2109 bit_size: 1,
2110 array: None,
2111 enumm: None,
2112 },
2113 ],
2114 },
2115 FieldSet {
2116 name: "Rtor",
2117 extends: None,
2118 description: Some(
2119 "Receiver timeout register",
2120 ),
2121 bit_size: 32,
2122 fields: &[
2123 Field {
2124 name: "rto",
2125 description: Some(
2126 "Receiver timeout value",
2127 ),
2128 bit_offset: BitOffset::Regular(
2129 RegularBitOffset {
2130 offset: 0,
2131 },
2132 ),
2133 bit_size: 24,
2134 array: None,
2135 enumm: None,
2136 },
2137 Field {
2138 name: "blen",
2139 description: Some(
2140 "Block Length",
2141 ),
2142 bit_offset: BitOffset::Regular(
2143 RegularBitOffset {
2144 offset: 24,
2145 },
2146 ),
2147 bit_size: 8,
2148 array: None,
2149 enumm: None,
2150 },
2151 ],
2152 },
2153 ],
2154 enums: &[
2155 Enum {
2156 name: "Abrmod",
2157 description: None,
2158 bit_size: 2,
2159 variants: &[
2160 EnumVariant {
2161 name: "START",
2162 description: Some(
2163 "Measurement of the start bit is used to detect the baud rate",
2164 ),
2165 value: 0,
2166 },
2167 EnumVariant {
2168 name: "EDGE",
2169 description: Some(
2170 "Falling edge to falling edge measurement",
2171 ),
2172 value: 1,
2173 },
2174 EnumVariant {
2175 name: "FRAME7F",
2176 description: Some(
2177 "0x7F frame detection",
2178 ),
2179 value: 2,
2180 },
2181 EnumVariant {
2182 name: "FRAME55",
2183 description: Some(
2184 "0x55 frame detection",
2185 ),
2186 value: 3,
2187 },
2188 ],
2189 },
2190 Enum {
2191 name: "Addm",
2192 description: None,
2193 bit_size: 1,
2194 variants: &[
2195 EnumVariant {
2196 name: "BIT4",
2197 description: Some(
2198 "4-bit address detection",
2199 ),
2200 value: 0,
2201 },
2202 EnumVariant {
2203 name: "BIT7",
2204 description: Some(
2205 "7-bit address detection",
2206 ),
2207 value: 1,
2208 },
2209 ],
2210 },
2211 Enum {
2212 name: "Cpha",
2213 description: None,
2214 bit_size: 1,
2215 variants: &[
2216 EnumVariant {
2217 name: "FIRST",
2218 description: Some(
2219 "The first clock transition is the first data capture edge",
2220 ),
2221 value: 0,
2222 },
2223 EnumVariant {
2224 name: "SECOND",
2225 description: Some(
2226 "The second clock transition is the first data capture edge",
2227 ),
2228 value: 1,
2229 },
2230 ],
2231 },
2232 Enum {
2233 name: "Cpol",
2234 description: None,
2235 bit_size: 1,
2236 variants: &[
2237 EnumVariant {
2238 name: "LOW",
2239 description: Some(
2240 "Steady low value on CK pin outside transmission window",
2241 ),
2242 value: 0,
2243 },
2244 EnumVariant {
2245 name: "HIGH",
2246 description: Some(
2247 "Steady high value on CK pin outside transmission window",
2248 ),
2249 value: 1,
2250 },
2251 ],
2252 },
2253 Enum {
2254 name: "Dep",
2255 description: None,
2256 bit_size: 1,
2257 variants: &[
2258 EnumVariant {
2259 name: "HIGH",
2260 description: Some(
2261 "DE signal is active high",
2262 ),
2263 value: 0,
2264 },
2265 EnumVariant {
2266 name: "LOW",
2267 description: Some(
2268 "DE signal is active low",
2269 ),
2270 value: 1,
2271 },
2272 ],
2273 },
2274 Enum {
2275 name: "Irlp",
2276 description: None,
2277 bit_size: 1,
2278 variants: &[
2279 EnumVariant {
2280 name: "NORMAL",
2281 description: Some(
2282 "Normal mode",
2283 ),
2284 value: 0,
2285 },
2286 EnumVariant {
2287 name: "LOW_POWER",
2288 description: Some(
2289 "Low-power mode",
2290 ),
2291 value: 1,
2292 },
2293 ],
2294 },
2295 Enum {
2296 name: "Lbdl",
2297 description: None,
2298 bit_size: 1,
2299 variants: &[
2300 EnumVariant {
2301 name: "BIT10",
2302 description: Some(
2303 "10-bit break detection",
2304 ),
2305 value: 0,
2306 },
2307 EnumVariant {
2308 name: "BIT11",
2309 description: Some(
2310 "11-bit break detection",
2311 ),
2312 value: 1,
2313 },
2314 ],
2315 },
2316 Enum {
2317 name: "M0",
2318 description: None,
2319 bit_size: 1,
2320 variants: &[
2321 EnumVariant {
2322 name: "BIT8",
2323 description: Some(
2324 "1 start bit, 8 data bits, n stop bits",
2325 ),
2326 value: 0,
2327 },
2328 EnumVariant {
2329 name: "BIT9",
2330 description: Some(
2331 "1 start bit, 9 data bits, n stop bits",
2332 ),
2333 value: 1,
2334 },
2335 ],
2336 },
2337 Enum {
2338 name: "M1",
2339 description: None,
2340 bit_size: 1,
2341 variants: &[
2342 EnumVariant {
2343 name: "M0",
2344 description: Some(
2345 "Use M0 to set the data bits",
2346 ),
2347 value: 0,
2348 },
2349 EnumVariant {
2350 name: "BIT7",
2351 description: Some(
2352 "1 start bit, 7 data bits, n stop bits",
2353 ),
2354 value: 1,
2355 },
2356 ],
2357 },
2358 Enum {
2359 name: "Msbfirst",
2360 description: None,
2361 bit_size: 1,
2362 variants: &[
2363 EnumVariant {
2364 name: "LSB",
2365 description: Some(
2366 "data is transmitted/received with data bit 0 first, following the start bit",
2367 ),
2368 value: 0,
2369 },
2370 EnumVariant {
2371 name: "MSB",
2372 description: Some(
2373 "data is transmitted/received with MSB (bit 7/8/9) first, following the start bit",
2374 ),
2375 value: 1,
2376 },
2377 ],
2378 },
2379 Enum {
2380 name: "Over8",
2381 description: None,
2382 bit_size: 1,
2383 variants: &[
2384 EnumVariant {
2385 name: "OVERSAMPLING16",
2386 description: Some(
2387 "Oversampling by 16",
2388 ),
2389 value: 0,
2390 },
2391 EnumVariant {
2392 name: "OVERSAMPLING8",
2393 description: Some(
2394 "Oversampling by 8",
2395 ),
2396 value: 1,
2397 },
2398 ],
2399 },
2400 Enum {
2401 name: "Presc",
2402 description: None,
2403 bit_size: 4,
2404 variants: &[
2405 EnumVariant {
2406 name: "DIV1",
2407 description: Some(
2408 "input clock not divided",
2409 ),
2410 value: 0,
2411 },
2412 EnumVariant {
2413 name: "DIV2",
2414 description: Some(
2415 "input clock divided by 2",
2416 ),
2417 value: 1,
2418 },
2419 EnumVariant {
2420 name: "DIV4",
2421 description: Some(
2422 "input clock divided by 4",
2423 ),
2424 value: 2,
2425 },
2426 EnumVariant {
2427 name: "DIV6",
2428 description: Some(
2429 "input clock divided by 6",
2430 ),
2431 value: 3,
2432 },
2433 EnumVariant {
2434 name: "DIV8",
2435 description: Some(
2436 "input clock divided by 8",
2437 ),
2438 value: 4,
2439 },
2440 EnumVariant {
2441 name: "DIV10",
2442 description: Some(
2443 "input clock divided by 10",
2444 ),
2445 value: 5,
2446 },
2447 EnumVariant {
2448 name: "DIV12",
2449 description: Some(
2450 "input clock divided by 12",
2451 ),
2452 value: 6,
2453 },
2454 EnumVariant {
2455 name: "DIV16",
2456 description: Some(
2457 "input clock divided by 16",
2458 ),
2459 value: 7,
2460 },
2461 EnumVariant {
2462 name: "DIV32",
2463 description: Some(
2464 "input clock divided by 32",
2465 ),
2466 value: 8,
2467 },
2468 EnumVariant {
2469 name: "DIV64",
2470 description: Some(
2471 "input clock divided by 64",
2472 ),
2473 value: 9,
2474 },
2475 EnumVariant {
2476 name: "DIV128",
2477 description: Some(
2478 "input clock divided by 128",
2479 ),
2480 value: 10,
2481 },
2482 EnumVariant {
2483 name: "DIV256",
2484 description: Some(
2485 "input clock divided by 256",
2486 ),
2487 value: 11,
2488 },
2489 ],
2490 },
2491 Enum {
2492 name: "Ps",
2493 description: None,
2494 bit_size: 1,
2495 variants: &[
2496 EnumVariant {
2497 name: "EVEN",
2498 description: Some(
2499 "Even parity",
2500 ),
2501 value: 0,
2502 },
2503 EnumVariant {
2504 name: "ODD",
2505 description: Some(
2506 "Odd parity",
2507 ),
2508 value: 1,
2509 },
2510 ],
2511 },
2512 Enum {
2513 name: "Rwu",
2514 description: None,
2515 bit_size: 1,
2516 variants: &[
2517 EnumVariant {
2518 name: "ACTIVE",
2519 description: Some(
2520 "Receiver in active mode",
2521 ),
2522 value: 0,
2523 },
2524 EnumVariant {
2525 name: "MUTE",
2526 description: Some(
2527 "Receiver in mute mode",
2528 ),
2529 value: 1,
2530 },
2531 ],
2532 },
2533 Enum {
2534 name: "Stop",
2535 description: None,
2536 bit_size: 2,
2537 variants: &[
2538 EnumVariant {
2539 name: "STOP1",
2540 description: Some(
2541 "1 stop bit",
2542 ),
2543 value: 0,
2544 },
2545 EnumVariant {
2546 name: "STOP0P5",
2547 description: Some(
2548 "0.5 stop bits",
2549 ),
2550 value: 1,
2551 },
2552 EnumVariant {
2553 name: "STOP2",
2554 description: Some(
2555 "2 stop bits",
2556 ),
2557 value: 2,
2558 },
2559 EnumVariant {
2560 name: "STOP1P5",
2561 description: Some(
2562 "1.5 stop bits",
2563 ),
2564 value: 3,
2565 },
2566 ],
2567 },
2568 Enum {
2569 name: "Wake",
2570 description: None,
2571 bit_size: 1,
2572 variants: &[
2573 EnumVariant {
2574 name: "IDLE_LINE",
2575 description: Some(
2576 "USART wakeup on idle line",
2577 ),
2578 value: 0,
2579 },
2580 EnumVariant {
2581 name: "ADDRESS_MARK",
2582 description: Some(
2583 "USART wakeup on address mark",
2584 ),
2585 value: 1,
2586 },
2587 ],
2588 },
2589 Enum {
2590 name: "Wus",
2591 description: None,
2592 bit_size: 2,
2593 variants: &[
2594 EnumVariant {
2595 name: "ADDRESS",
2596 description: Some(
2597 "WUF active on address match",
2598 ),
2599 value: 0,
2600 },
2601 EnumVariant {
2602 name: "START",
2603 description: Some(
2604 "WuF active on Start bit detection",
2605 ),
2606 value: 2,
2607 },
2608 EnumVariant {
2609 name: "RXNE",
2610 description: Some(
2611 "WUF active on RXNE",
2612 ),
2613 value: 3,
2614 },
2615 ],
2616 },
2617 ],
2618};
2619