| 1 | |
| 2 | use crate::metadata::ir::*; |
| 3 | pub(crate) static REGISTERS: IR = IR { |
| 4 | blocks: &[ |
| 5 | Block { |
| 6 | name: "Vrefbuf" , |
| 7 | extends: None, |
| 8 | description: Some( |
| 9 | "Voltage reference buffer." , |
| 10 | ), |
| 11 | items: &[ |
| 12 | BlockItem { |
| 13 | name: "csr" , |
| 14 | description: Some( |
| 15 | "VREFBUF control and status register." , |
| 16 | ), |
| 17 | array: None, |
| 18 | byte_offset: 0x0, |
| 19 | inner: BlockItemInner::Register( |
| 20 | Register { |
| 21 | access: Access::ReadWrite, |
| 22 | bit_size: 32, |
| 23 | fieldset: Some( |
| 24 | "Csr" , |
| 25 | ), |
| 26 | }, |
| 27 | ), |
| 28 | }, |
| 29 | BlockItem { |
| 30 | name: "ccr" , |
| 31 | description: Some( |
| 32 | "VREFBUF calibration control register." , |
| 33 | ), |
| 34 | array: None, |
| 35 | byte_offset: 0x4, |
| 36 | inner: BlockItemInner::Register( |
| 37 | Register { |
| 38 | access: Access::ReadWrite, |
| 39 | bit_size: 32, |
| 40 | fieldset: Some( |
| 41 | "Ccr" , |
| 42 | ), |
| 43 | }, |
| 44 | ), |
| 45 | }, |
| 46 | ], |
| 47 | }, |
| 48 | ], |
| 49 | fieldsets: &[ |
| 50 | FieldSet { |
| 51 | name: "Ccr" , |
| 52 | extends: None, |
| 53 | description: Some( |
| 54 | "VREFBUF calibration control register." , |
| 55 | ), |
| 56 | bit_size: 32, |
| 57 | fields: &[ |
| 58 | Field { |
| 59 | name: "trim" , |
| 60 | description: Some( |
| 61 | "Trimming code The TRIM code is a 6-bit unsigned data (minimum 000000, maximum 111111) that is set and updated according the mechanism described below. Reset: TRIM[5:0] is automatically initialized with the VRS = 0 trimming value stored in the Flash memory during the production test. VRS change: TRIM[5:0] is automatically initialized with the trimming value (corresponding to VRS setting) stored in the Flash memory during the production test. Write in TRIM[5:0]: User can modify the TRIM[5:0] with an arbitrary value. This is permanently disabling the control of the trimming value with VRS (until the device is reset). Note: If the user application performs the trimming, the trimming code must start from 000000 to 111111 in ascending order." , |
| 62 | ), |
| 63 | bit_offset: BitOffset::Regular( |
| 64 | RegularBitOffset { |
| 65 | offset: 0, |
| 66 | }, |
| 67 | ), |
| 68 | bit_size: 6, |
| 69 | array: None, |
| 70 | enumm: None, |
| 71 | }, |
| 72 | ], |
| 73 | }, |
| 74 | FieldSet { |
| 75 | name: "Csr" , |
| 76 | extends: None, |
| 77 | description: Some( |
| 78 | "VREFBUF control and status register." , |
| 79 | ), |
| 80 | bit_size: 32, |
| 81 | fields: &[ |
| 82 | Field { |
| 83 | name: "envr" , |
| 84 | description: Some( |
| 85 | "Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode." , |
| 86 | ), |
| 87 | bit_offset: BitOffset::Regular( |
| 88 | RegularBitOffset { |
| 89 | offset: 0, |
| 90 | }, |
| 91 | ), |
| 92 | bit_size: 1, |
| 93 | array: None, |
| 94 | enumm: None, |
| 95 | }, |
| 96 | Field { |
| 97 | name: "hiz" , |
| 98 | description: Some( |
| 99 | "High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to for the mode descriptions depending on ENVR bit configuration." , |
| 100 | ), |
| 101 | bit_offset: BitOffset::Regular( |
| 102 | RegularBitOffset { |
| 103 | offset: 1, |
| 104 | }, |
| 105 | ), |
| 106 | bit_size: 1, |
| 107 | array: None, |
| 108 | enumm: Some( |
| 109 | "Hiz" , |
| 110 | ), |
| 111 | }, |
| 112 | Field { |
| 113 | name: "vrr" , |
| 114 | description: Some( |
| 115 | "Voltage reference buffer ready." , |
| 116 | ), |
| 117 | bit_offset: BitOffset::Regular( |
| 118 | RegularBitOffset { |
| 119 | offset: 3, |
| 120 | }, |
| 121 | ), |
| 122 | bit_size: 1, |
| 123 | array: None, |
| 124 | enumm: None, |
| 125 | }, |
| 126 | Field { |
| 127 | name: "vrs" , |
| 128 | description: Some( |
| 129 | "Voltage reference scale These bits select the value generated by the voltage reference buffer. VRS = 000: VREFBUF0 voltage selected. VRS = 001: VREFBUF1 voltage selected. VRS = 010: VREFBUF2 voltage selected. VRS = 011: VREFBUF3 voltage selected. Others: Reserved Note: Refer to the product datasheet for each VREFBUFx voltage setting value. The software can program this bitfield only when the VREFBUF is disabled (ENVR=0)." , |
| 130 | ), |
| 131 | bit_offset: BitOffset::Regular( |
| 132 | RegularBitOffset { |
| 133 | offset: 4, |
| 134 | }, |
| 135 | ), |
| 136 | bit_size: 3, |
| 137 | array: None, |
| 138 | enumm: Some( |
| 139 | "Vrs" , |
| 140 | ), |
| 141 | }, |
| 142 | ], |
| 143 | }, |
| 144 | ], |
| 145 | enums: &[ |
| 146 | Enum { |
| 147 | name: "Hiz" , |
| 148 | description: None, |
| 149 | bit_size: 1, |
| 150 | variants: &[ |
| 151 | EnumVariant { |
| 152 | name: "CONNECTED" , |
| 153 | description: Some( |
| 154 | "VREF+ pin is internally connected to the voltage reference buffer output." , |
| 155 | ), |
| 156 | value: 0, |
| 157 | }, |
| 158 | EnumVariant { |
| 159 | name: "HIGH_Z" , |
| 160 | description: Some( |
| 161 | "VREF+ pin is high impedance." , |
| 162 | ), |
| 163 | value: 1, |
| 164 | }, |
| 165 | ], |
| 166 | }, |
| 167 | Enum { |
| 168 | name: "Vrs" , |
| 169 | description: None, |
| 170 | bit_size: 3, |
| 171 | variants: &[ |
| 172 | EnumVariant { |
| 173 | name: "VREF0" , |
| 174 | description: Some( |
| 175 | "Voltage reference set to around 2.5 V." , |
| 176 | ), |
| 177 | value: 0, |
| 178 | }, |
| 179 | EnumVariant { |
| 180 | name: "VREF1" , |
| 181 | description: Some( |
| 182 | "Voltage reference set to around 2.048 V." , |
| 183 | ), |
| 184 | value: 1, |
| 185 | }, |
| 186 | EnumVariant { |
| 187 | name: "VREF2" , |
| 188 | description: Some( |
| 189 | "Voltage reference set to around 1.8 V." , |
| 190 | ), |
| 191 | value: 2, |
| 192 | }, |
| 193 | EnumVariant { |
| 194 | name: "VREF3" , |
| 195 | description: Some( |
| 196 | "Voltage reference set to around 1.5 V (ADC, DAC are not compatible with this setting)." , |
| 197 | ), |
| 198 | value: 3, |
| 199 | }, |
| 200 | ], |
| 201 | }, |
| 202 | ], |
| 203 | }; |
| 204 | |