1
2use crate::metadata::ir::*;
3pub(crate) static REGISTERS: IR = IR {
4 blocks: &[Block {
5 name: "Wwdg",
6 extends: None,
7 description: Some("Window watchdog"),
8 items: &[
9 BlockItem {
10 name: "cr",
11 description: Some("Control register"),
12 array: None,
13 byte_offset: 0x0,
14 inner: BlockItemInner::Register(Register {
15 access: Access::ReadWrite,
16 bit_size: 32,
17 fieldset: Some("Cr"),
18 }),
19 },
20 BlockItem {
21 name: "cfr",
22 description: Some("Configuration register"),
23 array: None,
24 byte_offset: 0x4,
25 inner: BlockItemInner::Register(Register {
26 access: Access::ReadWrite,
27 bit_size: 32,
28 fieldset: Some("Cfr"),
29 }),
30 },
31 BlockItem {
32 name: "sr",
33 description: Some("Status register"),
34 array: None,
35 byte_offset: 0x8,
36 inner: BlockItemInner::Register(Register {
37 access: Access::ReadWrite,
38 bit_size: 32,
39 fieldset: Some("Sr"),
40 }),
41 },
42 ],
43 }],
44 fieldsets: &[
45 FieldSet {
46 name: "Cfr",
47 extends: None,
48 description: Some("Configuration register"),
49 bit_size: 32,
50 fields: &[
51 Field {
52 name: "w",
53 description: Some("7-bit window value"),
54 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
55 bit_size: 7,
56 array: None,
57 enumm: None,
58 },
59 Field {
60 name: "ewi",
61 description: Some("Early wakeup interrupt"),
62 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 9 }),
63 bit_size: 1,
64 array: None,
65 enumm: None,
66 },
67 Field {
68 name: "wdgtb",
69 description: Some("Timer base"),
70 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 11 }),
71 bit_size: 3,
72 array: None,
73 enumm: Some("Wdgtb"),
74 },
75 ],
76 },
77 FieldSet {
78 name: "Cr",
79 extends: None,
80 description: Some("Control register"),
81 bit_size: 32,
82 fields: &[
83 Field {
84 name: "t",
85 description: Some("7-bit counter (MSB to LSB)"),
86 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
87 bit_size: 7,
88 array: None,
89 enumm: None,
90 },
91 Field {
92 name: "wdga",
93 description: Some("Activation bit (true is enabled, false is disabled)"),
94 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 7 }),
95 bit_size: 1,
96 array: None,
97 enumm: None,
98 },
99 ],
100 },
101 FieldSet {
102 name: "Sr",
103 extends: None,
104 description: Some("Status register"),
105 bit_size: 32,
106 fields: &[Field {
107 name: "ewif",
108 description: Some("Early wakeup interrupt flag"),
109 bit_offset: BitOffset::Regular(RegularBitOffset { offset: 0 }),
110 bit_size: 1,
111 array: None,
112 enumm: None,
113 }],
114 },
115 ],
116 enums: &[Enum {
117 name: "Wdgtb",
118 description: None,
119 bit_size: 3,
120 variants: &[
121 EnumVariant {
122 name: "DIV1",
123 description: Some("Counter clock (PCLK1 div 4096) div 1"),
124 value: 0,
125 },
126 EnumVariant {
127 name: "DIV2",
128 description: Some("Counter clock (PCLK1 div 4096) div 2"),
129 value: 1,
130 },
131 EnumVariant {
132 name: "DIV4",
133 description: Some("Counter clock (PCLK1 div 4096) div 4"),
134 value: 2,
135 },
136 EnumVariant {
137 name: "DIV8",
138 description: Some("Counter clock (PCLK1 div 4096) div 8"),
139 value: 3,
140 },
141 EnumVariant {
142 name: "DIV16",
143 description: Some("Counter clock (PCLK1 div 4096) div 16"),
144 value: 4,
145 },
146 EnumVariant {
147 name: "DIV32",
148 description: Some("Counter clock (PCLK1 div 4096) div 32"),
149 value: 5,
150 },
151 EnumVariant {
152 name: "DIV64",
153 description: Some("Counter clock (PCLK1 div 4096) div 64"),
154 value: 6,
155 },
156 EnumVariant {
157 name: "DIV128",
158 description: Some("Counter clock (PCLK1 div 4096) div 128"),
159 value: 7,
160 },
161 ],
162 }],
163};
164