1// note from the spec:
2// When the context record field is larger than the register being stored in it, the upper bits of the
3// context record field are unused and ignored
4/// Universal EFI_SYSTEM_CONTEXT definition
5/// This is passed to debug callbacks
6#[repr(C)]
7pub union SystemContext {
8 ebc: *mut SystemContextEBC,
9 riscv_32: *mut SystemContextRiscV32,
10 riscv_64: *mut SystemContextRiscV64,
11 riscv_128: *mut SystemContextRiscV128,
12 ia32: *mut SystemContextIA32,
13 x64: *mut SystemContextX64,
14 ipf: *mut SystemContextIPF,
15 arm: *mut SystemContextARM,
16 aarch64: *mut SystemContextAARCH64,
17}
18
19/// System context for virtual EBC processors
20#[repr(C)]
21#[derive(Debug, Clone, Copy)]
22pub struct SystemContextEBC {
23 r0: u64,
24 r1: u64,
25 r2: u64,
26 r3: u64,
27 r4: u64,
28 r5: u64,
29 r6: u64,
30 r7: u64,
31 flags: u64,
32 control_flags: u64,
33 ip: u64,
34}
35
36#[repr(C)]
37#[derive(Debug, Clone, Copy)]
38pub struct SystemContextRiscV32 {
39 // Integer registers
40 zero: u32,
41 ra: u32,
42 sp: u32,
43 gp: u32,
44 tp: u32,
45 t0: u32,
46 t1: u32,
47 t2: u32,
48 s0fp: u32,
49 s1: u32,
50 a0: u32,
51 a1: u32,
52 a2: u32,
53 a3: u32,
54 a4: u32,
55 a5: u32,
56 a6: u32,
57 a7: u32,
58 s2: u32,
59 s3: u32,
60 s4: u32,
61 s5: u32,
62 s6: u32,
63 s7: u32,
64 s8: u32,
65 s9: u32,
66 s10: u32,
67 s11: u32,
68 t3: u32,
69 t4: u32,
70 t5: u32,
71 t6: u32,
72 // Float registers for F, D, and Q Standard Extensions
73 ft0: u128,
74 ft1: u128,
75 ft2: u128,
76 ft3: u128,
77 ft4: u128,
78 ft5: u128,
79 ft6: u128,
80 ft7: u128,
81 fs0: u128,
82 fs1: u128,
83 fa0: u128,
84 fa1: u128,
85 fa2: u128,
86 fa3: u128,
87 fa4: u128,
88 fa5: u128,
89 fa6: u128,
90 fa7: u128,
91 fs2: u128,
92 fs3: u128,
93 fs4: u128,
94 fs5: u128,
95 fs6: u128,
96 fs7: u128,
97 fs8: u128,
98 fs9: u128,
99 fs10: u128,
100 fs11: u128,
101 ft8: u128,
102 ft9: u128,
103 ft10: u128,
104 ft11: u128,
105}
106
107#[repr(C)]
108#[derive(Debug, Clone, Copy)]
109pub struct SystemContextRiscV64 {
110 // Integer registers
111 zero: u64,
112 ra: u64,
113 sp: u64,
114 gp: u64,
115 tp: u64,
116 t0: u64,
117 t1: u64,
118 t2: u64,
119 s0fp: u64,
120 s1: u64,
121 a0: u64,
122 a1: u64,
123 a2: u64,
124 a3: u64,
125 a4: u64,
126 a5: u64,
127 a6: u64,
128 a7: u64,
129 s2: u64,
130 s3: u64,
131 s4: u64,
132 s5: u64,
133 s6: u64,
134 s7: u64,
135 s8: u64,
136 s9: u64,
137 s10: u64,
138 s11: u64,
139 t3: u64,
140 t4: u64,
141 t5: u64,
142 t6: u64,
143 // Floating registers for F, D, and Q Standard Extensions
144 ft0: u128,
145 ft1: u128,
146 ft2: u128,
147 ft3: u128,
148 ft4: u128,
149 ft5: u128,
150 ft6: u128,
151 ft7: u128,
152 fs0: u128,
153 fs1: u128,
154 fa0: u128,
155 fa1: u128,
156 fa2: u128,
157 fa3: u128,
158 fa4: u128,
159 fa5: u128,
160 fa6: u128,
161 fa7: u128,
162 fs2: u128,
163 fs3: u128,
164 fs4: u128,
165 fs5: u128,
166 fs6: u128,
167 fs7: u128,
168 fs8: u128,
169 fs9: u128,
170 fs10: u128,
171 fs11: u128,
172 ft8: u128,
173 ft9: u128,
174 ft10: u128,
175 ft11: u128,
176}
177
178#[repr(C)]
179#[derive(Debug, Clone, Copy)]
180pub struct SystemContextRiscV128 {
181 // Integer registers
182 zero: u128,
183 ra: u128,
184 sp: u128,
185 gp: u128,
186 tp: u128,
187 t0: u128,
188 t1: u128,
189 t2: u128,
190 s0fp: u128,
191 s1: u128,
192 a0: u128,
193 a1: u128,
194 a2: u128,
195 a3: u128,
196 a4: u128,
197 a5: u128,
198 a6: u128,
199 a7: u128,
200 s2: u128,
201 s3: u128,
202 s4: u128,
203 s5: u128,
204 s6: u128,
205 s7: u128,
206 s8: u128,
207 s9: u128,
208 s10: u128,
209 s11: u128,
210 t3: u128,
211 t4: u128,
212 t5: u128,
213 t6: u128,
214 // Floating registers for F, D, and Q Standard Extensions
215 ft0: u128,
216 ft1: u128,
217 ft2: u128,
218 ft3: u128,
219 ft4: u128,
220 ft5: u128,
221 ft6: u128,
222 ft7: u128,
223 fs0: u128,
224 fs1: u128,
225 fa0: u128,
226 fa1: u128,
227 fa2: u128,
228 fa3: u128,
229 fa4: u128,
230 fa5: u128,
231 fa6: u128,
232 fa7: u128,
233 fs2: u128,
234 fs3: u128,
235 fs4: u128,
236 fs5: u128,
237 fs6: u128,
238 fs7: u128,
239 fs8: u128,
240 fs9: u128,
241 fs10: u128,
242 fs11: u128,
243 ft8: u128,
244 ft9: u128,
245 ft10: u128,
246 ft11: u128,
247}
248
249/// System context for IA-32 processors (x86)
250#[repr(C)]
251#[derive(Debug, Clone, Copy)]
252pub struct SystemContextIA32 {
253 exception_data: u32, // additional data pushed on the stack by some types of exceptions
254 fx_save_state: FxSaveStateIA32,
255 dr0: u32,
256 dr1: u32,
257 dr2: u32,
258 dr3: u32,
259 dr6: u32,
260 dr7: u32,
261 cr0: u32,
262 cr1: u32, // Noted as "Reserved" in the UEFI Specification
263 cr2: u32,
264 cr3: u32,
265 cr4: u32,
266 eflags: u32,
267 ldtr: u32,
268 tr: u32,
269 gdtr: [u32; 2],
270 idtr: [u32; 2],
271 eip: u32,
272 gs: u32,
273 fs: u32,
274 es: u32,
275 ds: u32,
276 cs: u32,
277 ss: u32,
278 edi: u32,
279 esi: u32,
280 ebp: u32,
281 esp: u32,
282 ebx: u32,
283 edx: u32,
284 ecx: u32,
285 eax: u32,
286}
287
288/// FP / MMX / XMM registers for IA-32
289#[repr(C)]
290#[derive(Debug, Clone, Copy)]
291pub struct FxSaveStateIA32 {
292 fcw: u16,
293 fsw: u16,
294 ftw: u16,
295 opcode: u16,
296 eip: u32,
297 cs: u16,
298 reserved_1: u16,
299 data_offset: u32,
300 ds: u16,
301 reserved_2: [u8; 10],
302 st0mm0: [u8; 10],
303 reserved_3: [u8; 6],
304 st1mm1: [u8; 10],
305 reserved_4: [u8; 6],
306 st2mm2: [u8; 10],
307 reserved_5: [u8; 6],
308 st3mm3: [u8; 10],
309 reserved_6: [u8; 6],
310 st4mm4: [u8; 10],
311 reserved_7: [u8; 6],
312 st5mm5: [u8; 10],
313 reserved_8: [u8; 6],
314 st6mm6: [u8; 10],
315 reserved_9: [u8; 6],
316 st7mm7: [u8; 10],
317 reserved_10: [u8; 6],
318 xmm0: [u8; 16],
319 xmm1: [u8; 16],
320 xmm2: [u8; 16],
321 xmm3: [u8; 16],
322 xmm4: [u8; 16],
323 xmm5: [u8; 16],
324 xmm6: [u8; 16],
325 xmm7: [u8; 16],
326 reserved_11: [u8; 14 * 16],
327}
328
329/// System context for x64 processors
330#[repr(C)]
331#[derive(Debug, Clone, Copy)]
332pub struct SystemContextX64 {
333 exception_data: u64, // additional data pushed on the stack by some types of exceptions
334 fx_save_state: FxSaveStateX64,
335 dr0: u64,
336 dr1: u64,
337 dr2: u64,
338 dr3: u64,
339 dr6: u64,
340 dr7: u64,
341 cr0: u64,
342 cr1: u64, // Noted as "Reserved" in the UEFI Specification
343 cr2: u64,
344 cr3: u64,
345 cr4: u64,
346 cr8: u64,
347 rflags: u64,
348 ldtr: u64,
349 tr: u64,
350 gdtr: [u64; 2],
351 idtr: [u64; 2],
352 rip: u64,
353 gs: u64,
354 fs: u64,
355 es: u64,
356 ds: u64,
357 cs: u64,
358 ss: u64,
359 rdi: u64,
360 rsi: u64,
361 rbp: u64,
362 rsp: u64,
363 rbx: u64,
364 rdx: u64,
365 rcx: u64,
366 rax: u64,
367 r8: u64,
368 r9: u64,
369 r10: u64,
370 r11: u64,
371 r12: u64,
372 r13: u64,
373 r14: u64,
374 r15: u64,
375}
376
377/// FP / MMX / XMM registers for X64
378#[repr(C)]
379#[derive(Debug, Clone, Copy)]
380pub struct FxSaveStateX64 {
381 fcw: u16,
382 fsw: u16,
383 ftw: u16,
384 opcode: u16,
385 rip: u64,
386 data_offset: u64,
387 reserved_1: [u8; 8],
388 st0mm0: [u8; 10],
389 reserved_2: [u8; 6],
390 st1mm1: [u8; 10],
391 reserved_3: [u8; 6],
392 st2mm2: [u8; 10],
393 reserved_4: [u8; 6],
394 st3mm3: [u8; 10],
395 reserved_5: [u8; 6],
396 st4mm4: [u8; 10],
397 reserved_6: [u8; 6],
398 st5mm5: [u8; 10],
399 reserved_7: [u8; 6],
400 st6mm6: [u8; 10],
401 reserved_8: [u8; 6],
402 st7mm7: [u8; 10],
403 reserved_9: [u8; 6],
404 xmm0: [u8; 16],
405 xmm1: [u8; 16],
406 xmm2: [u8; 16],
407 xmm3: [u8; 16],
408 xmm4: [u8; 16],
409 xmm5: [u8; 16],
410 xmm6: [u8; 16],
411 xmm7: [u8; 16],
412 reserved_11: [u8; 14 * 16], // spec goes right from `Reserved9` to `Reserved11`
413}
414
415#[repr(C)]
416#[derive(Debug, Clone, Copy)]
417pub struct SystemContextIPF {
418 reserved: u64,
419 r1: u64,
420 r2: u64,
421 r3: u64,
422 r4: u64,
423 r5: u64,
424 r6: u64,
425 r7: u64,
426 r8: u64,
427 r9: u64,
428 r10: u64,
429 r11: u64,
430 r12: u64,
431 r13: u64,
432 r14: u64,
433 r15: u64,
434 r16: u64,
435 r17: u64,
436 r18: u64,
437 r19: u64,
438 r20: u64,
439 r21: u64,
440 r22: u64,
441 r23: u64,
442 r24: u64,
443 r25: u64,
444 r26: u64,
445 r27: u64,
446 r28: u64,
447 r29: u64,
448 r30: u64,
449 r31: u64,
450 f2: [u64; 2],
451 f3: [u64; 2],
452 f4: [u64; 2],
453 f5: [u64; 2],
454 f6: [u64; 2],
455 f7: [u64; 2],
456 f8: [u64; 2],
457 f9: [u64; 2],
458 f10: [u64; 2],
459 f11: [u64; 2],
460 f12: [u64; 2],
461 f13: [u64; 2],
462 f14: [u64; 2],
463 f15: [u64; 2],
464 f16: [u64; 2],
465 f17: [u64; 2],
466 f18: [u64; 2],
467 f19: [u64; 2],
468 f20: [u64; 2],
469 f21: [u64; 2],
470 f22: [u64; 2],
471 f23: [u64; 2],
472 f24: [u64; 2],
473 f25: [u64; 2],
474 f26: [u64; 2],
475 f27: [u64; 2],
476 f28: [u64; 2],
477 f29: [u64; 2],
478 f30: [u64; 2],
479 f31: [u64; 2],
480 pr: u64,
481 b0: u64,
482 b1: u64,
483 b2: u64,
484 b3: u64,
485 b4: u64,
486 b5: u64,
487 b6: u64,
488 b7: u64,
489 // application registers
490 ar_rsc: u64,
491 ar_bsp: u64,
492 ar_bspstore: u64,
493 ar_rnat: u64,
494 ar_fcr: u64,
495 ar_eflag: u64,
496 ar_csd: u64,
497 ar_ssd: u64,
498 ar_cflg: u64,
499 ar_fsr: u64,
500 ar_fir: u64,
501 ar_fdr: u64,
502 ar_ccv: u64,
503 ar_unat: u64,
504 ar_fpsr: u64,
505 ar_pfs: u64,
506 ar_lc: u64,
507 ar_ec: u64,
508 // control registers
509 cr_dcr: u64,
510 cr_itm: u64,
511 cr_iva: u64,
512 cr_pta: u64,
513 cr_ipsr: u64,
514 cr_isr: u64,
515 cr_iip: u64,
516 cr_ifa: u64,
517 cr_itir: u64,
518 cr_iipa: u64,
519 cr_ifs: u64,
520 cr_iim: u64,
521 cr_iha: u64,
522 // debug registers
523 dbr0: u64,
524 dbr1: u64,
525 dbr2: u64,
526 dbr3: u64,
527 dbr4: u64,
528 dbr5: u64,
529 dbr6: u64,
530 dbr7: u64,
531 ibr0: u64,
532 ibr1: u64,
533 ibr2: u64,
534 ibr3: u64,
535 ibr4: u64,
536 ibr5: u64,
537 ibr6: u64,
538 ibr7: u64,
539 // virtual Registers
540 int_nat: u64, // nat bits for r1-r31
541}
542
543/// System context for ARM processors
544#[repr(C)]
545#[derive(Debug, Clone, Copy)]
546pub struct SystemContextARM {
547 r0: u32,
548 r1: u32,
549 r2: u32,
550 r3: u32,
551 r4: u32,
552 r5: u32,
553 r6: u32,
554 r7: u32,
555 r8: u32,
556 r9: u32,
557 r10: u32,
558 r11: u32,
559 r12: u32,
560 sp: u32,
561 lr: u32,
562 pc: u32,
563 cpsr: u32,
564 dfsr: u32,
565 dfar: u32,
566 ifsr: u32,
567}
568
569/// System context for AARCH64 processors
570#[repr(C)]
571#[derive(Debug, Clone, Copy)]
572pub struct SystemContextAARCH64 {
573 // General Purpose Registers
574 x0: u64,
575 x1: u64,
576 x2: u64,
577 x3: u64,
578 x4: u64,
579 x5: u64,
580 x6: u64,
581 x7: u64,
582 x8: u64,
583 x9: u64,
584 x10: u64,
585 x11: u64,
586 x12: u64,
587 x13: u64,
588 x14: u64,
589 x15: u64,
590 x16: u64,
591 x17: u64,
592 x18: u64,
593 x19: u64,
594 x20: u64,
595 x21: u64,
596 x22: u64,
597 x23: u64,
598 x24: u64,
599 x25: u64,
600 x26: u64,
601 x27: u64,
602 x28: u64,
603 fp: u64, // x29 - Frame Pointer
604 lr: u64, // x30 - Link Register
605 sp: u64, // x31 - Stack Pointer
606 // FP/SIMD Registers
607 v0: [u64; 2],
608 v1: [u64; 2],
609 v2: [u64; 2],
610 v3: [u64; 2],
611 v4: [u64; 2],
612 v5: [u64; 2],
613 v6: [u64; 2],
614 v7: [u64; 2],
615 v8: [u64; 2],
616 v9: [u64; 2],
617 v10: [u64; 2],
618 v11: [u64; 2],
619 v12: [u64; 2],
620 v13: [u64; 2],
621 v14: [u64; 2],
622 v15: [u64; 2],
623 v16: [u64; 2],
624 v17: [u64; 2],
625 v18: [u64; 2],
626 v19: [u64; 2],
627 v20: [u64; 2],
628 v21: [u64; 2],
629 v22: [u64; 2],
630 v23: [u64; 2],
631 v24: [u64; 2],
632 v25: [u64; 2],
633 v26: [u64; 2],
634 v27: [u64; 2],
635 v28: [u64; 2],
636 v29: [u64; 2],
637 v30: [u64; 2],
638 v31: [u64; 2],
639 elr: u64, // Exception Link Register
640 spsr: u64, // Saved Processor Status Register
641 fpsr: u64, // Floating Point Status Register
642 esr: u64, // Exception Syndrome Register
643 far: u64, // Fault Address Register
644}
645