1 | /// Represents supported CPU exceptions. |
2 | #[repr (C)] |
3 | pub struct ExceptionType(isize); |
4 | |
5 | impl ExceptionType { |
6 | /// Undefined Exception |
7 | pub const EXCEPT_EBC_UNDEFINED: ExceptionType = ExceptionType(0); |
8 | /// Divide-by-zero Error |
9 | pub const EXCEPT_EBC_DIVIDE_ERROR: ExceptionType = ExceptionType(1); |
10 | /// Debug Exception |
11 | pub const EXCEPT_EBC_DEBUG: ExceptionType = ExceptionType(2); |
12 | /// Breakpoint |
13 | pub const EXCEPT_EBC_BREAKPOINT: ExceptionType = ExceptionType(3); |
14 | /// Overflow |
15 | pub const EXCEPT_EBC_OVERFLOW: ExceptionType = ExceptionType(4); |
16 | /// Invalid Opcode |
17 | pub const EXCEPT_EBC_INVALID_OPCODE: ExceptionType = ExceptionType(5); |
18 | /// Stack-Segment Fault |
19 | pub const EXCEPT_EBC_STACK_FAULT: ExceptionType = ExceptionType(6); |
20 | /// Alignment Check |
21 | pub const EXCEPT_EBC_ALIGNMENT_CHECK: ExceptionType = ExceptionType(7); |
22 | /// Instruction Encoding Exception |
23 | pub const EXCEPT_EBC_INSTRUCTION_ENCODING: ExceptionType = ExceptionType(8); |
24 | /// Bad Breakpoint Exception |
25 | pub const EXCEPT_EBC_BAD_BREAK: ExceptionType = ExceptionType(9); |
26 | /// Single Step Exception |
27 | pub const EXCEPT_EBC_SINGLE_STEP: ExceptionType = ExceptionType(10); |
28 | } |
29 | |
30 | #[cfg (target_arch = "x86" )] |
31 | impl ExceptionType { |
32 | /// Divide-by-zero Error |
33 | pub const EXCEPT_IA32_DIVIDE_ERROR: ExceptionType = ExceptionType(0); |
34 | /// Debug Exception |
35 | pub const EXCEPT_IA32_DEBUG: ExceptionType = ExceptionType(1); |
36 | /// Non-maskable Interrupt |
37 | pub const EXCEPT_IA32_NMI: ExceptionType = ExceptionType(2); |
38 | /// Breakpoint |
39 | pub const EXCEPT_IA32_BREAKPOINT: ExceptionType = ExceptionType(3); |
40 | /// Overflow |
41 | pub const EXCEPT_IA32_OVERFLOW: ExceptionType = ExceptionType(4); |
42 | /// Bound Range Exceeded |
43 | pub const EXCEPT_IA32_BOUND: ExceptionType = ExceptionType(5); |
44 | /// Invalid Opcode |
45 | pub const EXCEPT_IA32_INVALID_OPCODE: ExceptionType = ExceptionType(6); |
46 | /// Double Fault |
47 | pub const EXCEPT_IA32_DOUBLE_FAULT: ExceptionType = ExceptionType(8); |
48 | /// Invalid TSS |
49 | pub const EXCEPT_IA32_INVALID_TSS: ExceptionType = ExceptionType(10); |
50 | /// Segment Not Present |
51 | pub const EXCEPT_IA32_SEG_NOT_PRESENT: ExceptionType = ExceptionType(11); |
52 | /// Stack-Segment Fault |
53 | pub const EXCEPT_IA32_STACK_FAULT: ExceptionType = ExceptionType(12); |
54 | /// General Protection Fault |
55 | pub const EXCEPT_IA32_GP_FAULT: ExceptionType = ExceptionType(13); |
56 | /// Page Fault |
57 | pub const EXCEPT_IA32_PAGE_FAULT: ExceptionType = ExceptionType(14); |
58 | /// x87 Floating-Point Exception |
59 | pub const EXCEPT_IA32_FP_ERROR: ExceptionType = ExceptionType(16); |
60 | /// Alignment Check |
61 | pub const EXCEPT_IA32_ALIGNMENT_CHECK: ExceptionType = ExceptionType(17); |
62 | /// Machine Check |
63 | pub const EXCEPT_IA32_MACHINE_CHECK: ExceptionType = ExceptionType(18); |
64 | /// SIMD Floating-Point Exception |
65 | pub const EXCEPT_IA32_SIMD: ExceptionType = ExceptionType(19); |
66 | } |
67 | |
68 | #[cfg (target_arch = "x86_64" )] |
69 | impl ExceptionType { |
70 | /// Divide-by-zero Error |
71 | pub const EXCEPT_X64_DIVIDE_ERROR: ExceptionType = ExceptionType(0); |
72 | /// Debug Exception |
73 | pub const EXCEPT_X64_DEBUG: ExceptionType = ExceptionType(1); |
74 | /// Non-maskable Interrupt |
75 | pub const EXCEPT_X64_NMI: ExceptionType = ExceptionType(2); |
76 | /// Breakpoint |
77 | pub const EXCEPT_X64_BREAKPOINT: ExceptionType = ExceptionType(3); |
78 | /// Overflow |
79 | pub const EXCEPT_X64_OVERFLOW: ExceptionType = ExceptionType(4); |
80 | /// Bound Range Exceeded |
81 | pub const EXCEPT_X64_BOUND: ExceptionType = ExceptionType(5); |
82 | /// Invalid Opcode |
83 | pub const EXCEPT_X64_INVALID_OPCODE: ExceptionType = ExceptionType(6); |
84 | /// Double Fault |
85 | pub const EXCEPT_X64_DOUBLE_FAULT: ExceptionType = ExceptionType(8); |
86 | /// Invalid TSS |
87 | pub const EXCEPT_X64_INVALID_TSS: ExceptionType = ExceptionType(10); |
88 | /// Segment Not Present |
89 | pub const EXCEPT_X64_SEG_NOT_PRESENT: ExceptionType = ExceptionType(11); |
90 | /// Stack-Segment Fault |
91 | pub const EXCEPT_X64_STACK_FAULT: ExceptionType = ExceptionType(12); |
92 | /// General Protection Fault |
93 | pub const EXCEPT_X64_GP_FAULT: ExceptionType = ExceptionType(13); |
94 | /// Page Fault |
95 | pub const EXCEPT_X64_PAGE_FAULT: ExceptionType = ExceptionType(14); |
96 | /// x87 Floating-Point Exception |
97 | pub const EXCEPT_X64_FP_ERROR: ExceptionType = ExceptionType(16); |
98 | /// Alignment Check |
99 | pub const EXCEPT_X64_ALIGNMENT_CHECK: ExceptionType = ExceptionType(17); |
100 | /// Machine Check |
101 | pub const EXCEPT_X64_MACHINE_CHECK: ExceptionType = ExceptionType(18); |
102 | /// SIMD Floating-Point Exception |
103 | pub const EXCEPT_X64_SIMD: ExceptionType = ExceptionType(19); |
104 | } |
105 | |
106 | #[cfg (target_arch = "arm" )] |
107 | impl ExceptionType { |
108 | /// Processor reset |
109 | pub const EXCEPT_ARM_RESET: ExceptionType = ExceptionType(0); |
110 | /// Undefined instruction |
111 | pub const EXCEPT_ARM_UNDEFINED_INSTRUCTION: ExceptionType = ExceptionType(1); |
112 | /// Software Interrupt |
113 | pub const EXCEPT_ARM_SOFTWARE_INTERRUPT: ExceptionType = ExceptionType(2); |
114 | /// Prefetch aborted |
115 | pub const EXCEPT_ARM_PREFETCH_ABORT: ExceptionType = ExceptionType(3); |
116 | /// Data access memory abort |
117 | pub const EXCEPT_ARM_DATA_ABORT: ExceptionType = ExceptionType(4); |
118 | /// Reserved |
119 | pub const EXCEPT_ARM_RESERVED: ExceptionType = ExceptionType(5); |
120 | /// Normal interrupt |
121 | pub const EXCEPT_ARM_IRQ: ExceptionType = ExceptionType(6); |
122 | /// Fast interrupt |
123 | pub const EXCEPT_ARM_FIQ: ExceptionType = ExceptionType(7); |
124 | /// In the UEFI spec for "convenience", unsure if we'll need it. Set to `EXCEPT_ARM_FIQ` |
125 | pub const MAX_ARM_EXCEPTION: ExceptionType = ExceptionType::EXCEPT_ARM_FIQ; |
126 | } |
127 | |
128 | #[cfg (target_arch = "aarch64" )] |
129 | impl ExceptionType { |
130 | /// Synchronous exception, such as attempting to execute an invalid instruction |
131 | pub const EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS: ExceptionType = ExceptionType(0); |
132 | /// Normal interrupt |
133 | pub const EXCEPT_AARCH64_IRQ: ExceptionType = ExceptionType(1); |
134 | /// Fast interrupt |
135 | pub const EXCEPT_AARCH64_FIQ: ExceptionType = ExceptionType(2); |
136 | /// System Error |
137 | pub const EXCEPT_AARCH64_SERROR: ExceptionType = ExceptionType(3); |
138 | /// In the UEFI spec for "convenience", unsure if we'll need it. Set to `EXCEPT_AARCH64_SERROR` |
139 | pub const MAX_AARCH64_EXCEPTION: ExceptionType = ExceptionType::EXCEPT_AARCH64_SERROR; |
140 | } |
141 | |
142 | #[cfg (target_arch = "riscv" )] |
143 | impl ExceptionType { |
144 | /// Instruction misaligned |
145 | pub const EXCEPT_RISCV_INST_MISALIGNED: ExceptionType = ExceptionType(0); |
146 | /// Instruction access fault |
147 | pub const EXCEPT_RISCV_INST_ACCESS_FAULT: ExceptionType = ExceptionType(1); |
148 | /// Illegal instruction |
149 | pub const EXCEPT_RISCV_ILLEGAL_INST: ExceptionType = ExceptionType(2); |
150 | /// Breakpoint |
151 | pub const EXCEPT_RISCV_BREAKPOINT: ExceptionType = ExceptionType(3); |
152 | /// Load address misaligned |
153 | pub const EXCEPT_RISCV_LOAD_ADDRESS_MISALIGNED: ExceptionType = ExceptionType(4); |
154 | /// Load accept fault |
155 | pub const EXCEPT_RISCV_LOAD_ACCESS_FAULT: ExceptionType = ExceptionType(5); |
156 | /// Store AMO address misaligned |
157 | pub const EXCEPT_RISCV_STORE_AMO_ADDRESS_MISALIGNED: ExceptionType = ExceptionType(6); |
158 | /// Store AMO access fault |
159 | pub const EXCEPT_RISCV_STORE_AMO_ACCESS_FAULT: ExceptionType = ExceptionType(7); |
160 | /// ECALL from User mode |
161 | pub const EXCEPT_RISCV_ENV_CALL_FROM_UMODE: ExceptionType = ExceptionType(8); |
162 | /// ECALL from Supervisor mode |
163 | pub const EXCEPT_RISCV_ENV_CALL_FROM_SMODE: ExceptionType = ExceptionType(9); |
164 | /// ECALL from Machine mode |
165 | pub const EXCEPT_RISCV_ENV_CALL_FROM_MMODE: ExceptionType = ExceptionType(11); |
166 | /// Instruction page fault |
167 | pub const EXCEPT_RISCV_INST_PAGE_FAULT: ExceptionType = ExceptionType(12); |
168 | /// Load page fault |
169 | pub const EXCEPT_RISCV_LOAD_PAGE_FAULT: ExceptionType = ExceptionType(13); |
170 | /// Store AMO page fault |
171 | pub const EXCEPT_RISCV_STORE_AMO_PAGE_FAULT: ExceptionType = ExceptionType(15); |
172 | // RISC-V interrupt types |
173 | /// Supervisor software interrupt |
174 | pub const EXCEPT_RISCV_SUPERVISOR_SOFTWARE_INT: ExceptionType = ExceptionType(1); |
175 | /// Machine software interrupt |
176 | pub const EXCEPT_RISCV_MACHINE_SOFTWARE_INT: ExceptionType = ExceptionType(3); |
177 | /// Supervisor timer interrupt |
178 | pub const EXCEPT_RISCV_SUPERVISOR_TIMER_INT: ExceptionType = ExceptionType(5); |
179 | /// Machine timer interrupt |
180 | pub const EXCEPT_RISCV_MACHINE_TIMER_INT: ExceptionType = ExceptionType(7); |
181 | /// Supervisor external interrupt |
182 | pub const EXCEPT_RISCV_SUPERVISOR_EXTERNAL_INT: ExceptionType = ExceptionType(9); |
183 | /// Machine external interrupt |
184 | pub const EXCEPT_RISCV_MACHINE_EXTERNAL_INT: ExceptionType = ExceptionType(11); |
185 | } |
186 | |