1 | /* Target instruction definitions. |
2 | Copyright (C) 2015-2023 Free Software Foundation, Inc. |
3 | |
4 | This program is free software; you can redistribute it and/or modify it |
5 | under the terms of the GNU General Public License as published by the |
6 | Free Software Foundation; either version 3, or (at your option) any |
7 | later version. |
8 | |
9 | This program is distributed in the hope that it will be useful, |
10 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
12 | GNU General Public License for more details. |
13 | |
14 | You should have received a copy of the GNU General Public License |
15 | along with this program; see the file COPYING3. If not see |
16 | <http://www.gnu.org/licenses/>. */ |
17 | |
18 | /* This file has one entry for each public pattern name that the target |
19 | can provide. It is only used if no distinction between operand modes |
20 | is necessary. If separate patterns are needed for different modes |
21 | (so as to distinguish addition of QImode values from addition of |
22 | HImode values, for example) then an optab should be used instead. |
23 | |
24 | Each entry has the form: |
25 | |
26 | DEF_TARGET_INSN (name, prototype) |
27 | |
28 | where NAME is the name of the pattern and PROTOTYPE is its C prototype. |
29 | The prototype should use parameter names of the form "x0", "x1", etc. |
30 | for the operands that the .md pattern is required to have, followed by |
31 | parameter names of the form "optN" for operands that the .md pattern |
32 | may choose to ignore. Patterns that never take operands should have |
33 | a prototype "(void)". |
34 | |
35 | Pattern names should be documented in md.texi rather than here. */ |
36 | DEF_TARGET_INSN (allocate_stack, (rtx x0, rtx x1)) |
37 | DEF_TARGET_INSN (atomic_test_and_set, (rtx x0, rtx x1, rtx x2)) |
38 | DEF_TARGET_INSN (builtin_longjmp, (rtx x0)) |
39 | DEF_TARGET_INSN (builtin_setjmp_receiver, (rtx x0)) |
40 | DEF_TARGET_INSN (builtin_setjmp_setup, (rtx x0)) |
41 | DEF_TARGET_INSN (canonicalize_funcptr_for_compare, (rtx x0, rtx x1)) |
42 | DEF_TARGET_INSN (call, (rtx x0, rtx opt1, rtx opt2, rtx opt3)) |
43 | DEF_TARGET_INSN (call_pop, (rtx x0, rtx opt1, rtx opt2, rtx opt3)) |
44 | DEF_TARGET_INSN (call_value, (rtx x0, rtx x1, rtx opt2, rtx opt3, rtx opt4)) |
45 | DEF_TARGET_INSN (call_value_pop, (rtx x0, rtx x1, rtx opt2, rtx opt3, |
46 | rtx opt4)) |
47 | DEF_TARGET_INSN (casesi, (rtx x0, rtx x1, rtx x2, rtx x3, rtx x4)) |
48 | DEF_TARGET_INSN (check_stack, (rtx x0)) |
49 | DEF_TARGET_INSN (clear_cache, (rtx x0, rtx x1)) |
50 | DEF_TARGET_INSN (doloop_begin, (rtx x0, rtx x1)) |
51 | DEF_TARGET_INSN (doloop_end, (rtx x0, rtx x1)) |
52 | DEF_TARGET_INSN (eh_return, (rtx x0)) |
53 | DEF_TARGET_INSN (epilogue, (void)) |
54 | DEF_TARGET_INSN (exception_receiver, (void)) |
55 | DEF_TARGET_INSN (extv, (rtx x0, rtx x1, rtx x2, rtx x3)) |
56 | DEF_TARGET_INSN (extzv, (rtx x0, rtx x1, rtx x2, rtx x3)) |
57 | DEF_TARGET_INSN (indirect_jump, (rtx x0)) |
58 | DEF_TARGET_INSN (insv, (rtx x0, rtx x1, rtx x2, rtx x3)) |
59 | DEF_TARGET_INSN (jump, (rtx x0)) |
60 | DEF_TARGET_INSN (load_multiple, (rtx x0, rtx x1, rtx x2)) |
61 | DEF_TARGET_INSN (mem_thread_fence, (rtx x0)) |
62 | DEF_TARGET_INSN (memory_barrier, (void)) |
63 | DEF_TARGET_INSN (memory_blockage, (void)) |
64 | DEF_TARGET_INSN (movstr, (rtx x0, rtx x1, rtx x2)) |
65 | DEF_TARGET_INSN (nonlocal_goto, (rtx x0, rtx x1, rtx x2, rtx x3)) |
66 | DEF_TARGET_INSN (nonlocal_goto_receiver, (void)) |
67 | DEF_TARGET_INSN (oacc_dim_pos, (rtx x0, rtx x1)) |
68 | DEF_TARGET_INSN (oacc_dim_size, (rtx x0, rtx x1)) |
69 | DEF_TARGET_INSN (oacc_fork, (rtx x0, rtx x1, rtx x2)) |
70 | DEF_TARGET_INSN (oacc_join, (rtx x0, rtx x1, rtx x2)) |
71 | DEF_TARGET_INSN (omp_simt_enter, (rtx x0, rtx x1, rtx x2)) |
72 | DEF_TARGET_INSN (omp_simt_exit, (rtx x0)) |
73 | DEF_TARGET_INSN (omp_simt_lane, (rtx x0)) |
74 | DEF_TARGET_INSN (omp_simt_last_lane, (rtx x0, rtx x1)) |
75 | DEF_TARGET_INSN (omp_simt_ordered, (rtx x0, rtx x1)) |
76 | DEF_TARGET_INSN (omp_simt_vote_any, (rtx x0, rtx x1)) |
77 | DEF_TARGET_INSN (omp_simt_xchg_bfly, (rtx x0, rtx x1, rtx x2)) |
78 | DEF_TARGET_INSN (omp_simt_xchg_idx, (rtx x0, rtx x1, rtx x2)) |
79 | DEF_TARGET_INSN (prefetch, (rtx x0, rtx x1, rtx x2)) |
80 | DEF_TARGET_INSN (probe_stack, (rtx x0)) |
81 | DEF_TARGET_INSN (probe_stack_address, (rtx x0)) |
82 | DEF_TARGET_INSN (prologue, (void)) |
83 | DEF_TARGET_INSN (ptr_extend, (rtx x0, rtx x1)) |
84 | DEF_TARGET_INSN (reload_load_address, (rtx x0, rtx x1)) |
85 | DEF_TARGET_INSN (restore_stack_block, (rtx x0, rtx x1)) |
86 | DEF_TARGET_INSN (restore_stack_function, (rtx x0, rtx x1)) |
87 | DEF_TARGET_INSN (restore_stack_nonlocal, (rtx x0, rtx x1)) |
88 | DEF_TARGET_INSN (return, (void)) |
89 | DEF_TARGET_INSN (save_stack_block, (rtx x0, rtx x1)) |
90 | DEF_TARGET_INSN (save_stack_function, (rtx x0, rtx x1)) |
91 | DEF_TARGET_INSN (save_stack_nonlocal, (rtx x0, rtx x1)) |
92 | DEF_TARGET_INSN (sibcall, (rtx x0, rtx opt1, rtx opt2, rtx opt3)) |
93 | DEF_TARGET_INSN (sibcall_epilogue, (void)) |
94 | DEF_TARGET_INSN (sibcall_value, (rtx x0, rtx x1, rtx opt2, rtx opt3, |
95 | rtx opt4)) |
96 | DEF_TARGET_INSN (simple_return, (void)) |
97 | DEF_TARGET_INSN (split_stack_prologue, (void)) |
98 | DEF_TARGET_INSN (split_stack_space_check, (rtx x0, rtx x1)) |
99 | DEF_TARGET_INSN (stack_protect_combined_set, (rtx x0, rtx x1)) |
100 | DEF_TARGET_INSN (stack_protect_set, (rtx x0, rtx x1)) |
101 | DEF_TARGET_INSN (stack_protect_combined_test, (rtx x0, rtx x1, rtx x2)) |
102 | DEF_TARGET_INSN (stack_protect_test, (rtx x0, rtx x1, rtx x2)) |
103 | DEF_TARGET_INSN (store_multiple, (rtx x0, rtx x1, rtx x2)) |
104 | DEF_TARGET_INSN (tablejump, (rtx x0, rtx x1)) |
105 | DEF_TARGET_INSN (trap, (void)) |
106 | DEF_TARGET_INSN (unique, (void)) |
107 | DEF_TARGET_INSN (untyped_call, (rtx x0, rtx x1, rtx x2)) |
108 | DEF_TARGET_INSN (untyped_return, (rtx x0, rtx x1)) |
109 | |