1 | /* Double-precision vector (Advanced SIMD) sin function. |
2 | |
3 | Copyright (C) 2023-2024 Free Software Foundation, Inc. |
4 | This file is part of the GNU C Library. |
5 | |
6 | The GNU C Library is free software; you can redistribute it and/or |
7 | modify it under the terms of the GNU Lesser General Public |
8 | License as published by the Free Software Foundation; either |
9 | version 2.1 of the License, or (at your option) any later version. |
10 | |
11 | The GNU C Library is distributed in the hope that it will be useful, |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
14 | Lesser General Public License for more details. |
15 | |
16 | You should have received a copy of the GNU Lesser General Public |
17 | License along with the GNU C Library; if not, see |
18 | <https://www.gnu.org/licenses/>. */ |
19 | |
20 | #include "v_math.h" |
21 | |
22 | static const struct data |
23 | { |
24 | float64x2_t poly[7]; |
25 | float64x2_t range_val, inv_pi, shift, pi_1, pi_2, pi_3; |
26 | } data = { |
27 | .poly = { V2 (-0x1.555555555547bp-3), V2 (0x1.1111111108a4dp-7), |
28 | V2 (-0x1.a01a019936f27p-13), V2 (0x1.71de37a97d93ep-19), |
29 | V2 (-0x1.ae633919987c6p-26), V2 (0x1.60e277ae07cecp-33), |
30 | V2 (-0x1.9e9540300a1p-41) }, |
31 | |
32 | .range_val = V2 (0x1p23), |
33 | .inv_pi = V2 (0x1.45f306dc9c883p-2), |
34 | .pi_1 = V2 (0x1.921fb54442d18p+1), |
35 | .pi_2 = V2 (0x1.1a62633145c06p-53), |
36 | .pi_3 = V2 (0x1.c1cd129024e09p-106), |
37 | .shift = V2 (0x1.8p52), |
38 | }; |
39 | |
40 | #if WANT_SIMD_EXCEPT |
41 | # define TinyBound v_u64 (0x3000000000000000) /* asuint64 (0x1p-255). */ |
42 | # define Thresh v_u64 (0x1160000000000000) /* RangeVal - TinyBound. */ |
43 | #endif |
44 | |
45 | #define C(i) d->poly[i] |
46 | |
47 | static float64x2_t VPCS_ATTR NOINLINE |
48 | special_case (float64x2_t x, float64x2_t y, uint64x2_t odd, uint64x2_t cmp) |
49 | { |
50 | y = vreinterpretq_f64_u64 (veorq_u64 (vreinterpretq_u64_f64 (y), odd)); |
51 | return v_call_f64 (sin, x, y, cmp); |
52 | } |
53 | |
54 | /* Vector (AdvSIMD) sin approximation. |
55 | Maximum observed error in [-pi/2, pi/2], where argument is not reduced, |
56 | is 2.87 ULP: |
57 | _ZGVnN2v_sin (0x1.921d5c6a07142p+0) got 0x1.fffffffa7dc02p-1 |
58 | want 0x1.fffffffa7dc05p-1 |
59 | Maximum observed error in the entire non-special domain ([-2^23, 2^23]) |
60 | is 3.22 ULP: |
61 | _ZGVnN2v_sin (0x1.5702447b6f17bp+22) got 0x1.ffdcd125c84fbp-3 |
62 | want 0x1.ffdcd125c84f8p-3. */ |
63 | float64x2_t VPCS_ATTR V_NAME_D1 (sin) (float64x2_t x) |
64 | { |
65 | const struct data *d = ptr_barrier (&data); |
66 | float64x2_t n, r, r2, r3, r4, y, t1, t2, t3; |
67 | uint64x2_t odd, cmp; |
68 | |
69 | #if WANT_SIMD_EXCEPT |
70 | /* Detect |x| <= TinyBound or |x| >= RangeVal. If fenv exceptions are to be |
71 | triggered correctly, set any special lanes to 1 (which is neutral w.r.t. |
72 | fenv). These lanes will be fixed by special-case handler later. */ |
73 | uint64x2_t ir = vreinterpretq_u64_f64 (vabsq_f64 (x)); |
74 | cmp = vcgeq_u64 (vsubq_u64 (ir, TinyBound), Thresh); |
75 | r = vbslq_f64 (cmp, vreinterpretq_f64_u64 (cmp), x); |
76 | #else |
77 | r = x; |
78 | cmp = vcageq_f64 (x, d->range_val); |
79 | #endif |
80 | |
81 | /* n = rint(|x|/pi). */ |
82 | n = vfmaq_f64 (d->shift, d->inv_pi, r); |
83 | odd = vshlq_n_u64 (vreinterpretq_u64_f64 (n), 63); |
84 | n = vsubq_f64 (n, d->shift); |
85 | |
86 | /* r = |x| - n*pi (range reduction into -pi/2 .. pi/2). */ |
87 | r = vfmsq_f64 (r, d->pi_1, n); |
88 | r = vfmsq_f64 (r, d->pi_2, n); |
89 | r = vfmsq_f64 (r, d->pi_3, n); |
90 | |
91 | /* sin(r) poly approx. */ |
92 | r2 = vmulq_f64 (r, r); |
93 | r3 = vmulq_f64 (r2, r); |
94 | r4 = vmulq_f64 (r2, r2); |
95 | |
96 | t1 = vfmaq_f64 (C (4), C (5), r2); |
97 | t2 = vfmaq_f64 (C (2), C (3), r2); |
98 | t3 = vfmaq_f64 (C (0), C (1), r2); |
99 | |
100 | y = vfmaq_f64 (t1, C (6), r4); |
101 | y = vfmaq_f64 (t2, y, r4); |
102 | y = vfmaq_f64 (t3, y, r4); |
103 | y = vfmaq_f64 (r, y, r3); |
104 | |
105 | if (__glibc_unlikely (v_any_u64 (cmp))) |
106 | return special_case (x, y, odd, cmp); |
107 | return vreinterpretq_f64_u64 (veorq_u64 (vreinterpretq_u64_f64 (y), odd)); |
108 | } |
109 | |