1/* Initialize CPU feature data. AArch64 version.
2 This file is part of the GNU C Library.
3 Copyright (C) 2017-2024 Free Software Foundation, Inc.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library; if not, see
17 <https://www.gnu.org/licenses/>. */
18
19#include <array_length.h>
20#include <cpu-features.h>
21#include <sys/auxv.h>
22#include <elf/dl-hwcaps.h>
23#include <sys/prctl.h>
24#include <sys/utsname.h>
25#include <dl-tunables-parse.h>
26#include <dl-symbol-redir-ifunc.h>
27
28#define DCZID_DZP_MASK (1 << 4)
29#define DCZID_BS_MASK (0xf)
30
31/* The maximal set of permitted tags that the MTE random tag generation
32 instruction may use. We exclude tag 0 because a) we want to reserve
33 that for the libc heap structures and b) because it makes it easier
34 to see when pointer have been correctly tagged. */
35#define MTE_ALLOWED_TAGS (0xfffe << PR_MTE_TAG_SHIFT)
36
37struct cpu_list
38{
39 const char *name;
40 size_t len;
41 uint64_t midr;
42};
43
44static const struct cpu_list cpu_list[] =
45{
46#define CPU_LIST_ENTRY(__str, __num) { __str, sizeof (__str) - 1, __num }
47 CPU_LIST_ENTRY ("thunderxt88", 0x430F0A10),
48 CPU_LIST_ENTRY ("thunderx2t99", 0x431F0AF0),
49 CPU_LIST_ENTRY ("thunderx2t99p1", 0x420F5160),
50 CPU_LIST_ENTRY ("ares", 0x411FD0C0),
51 CPU_LIST_ENTRY ("emag", 0x503F0001),
52 CPU_LIST_ENTRY ("kunpeng920", 0x481FD010),
53 CPU_LIST_ENTRY ("a64fx", 0x460F0010),
54 CPU_LIST_ENTRY ("generic", 0x0),
55};
56
57static uint64_t
58get_midr_from_mcpu (const struct tunable_str_t *mcpu)
59{
60 for (int i = 0; i < array_length (cpu_list); i++)
61 if (tunable_strcmp (strval: mcpu, str: cpu_list[i].name, len: cpu_list[i].len))
62 return cpu_list[i].midr;
63
64 return UINT64_MAX;
65}
66
67#if __LINUX_KERNEL_VERSION < 0x060200
68
69/* Return true if we prefer using SVE in string ifuncs. Old kernels disable
70 SVE after every system call which results in unnecessary traps if memcpy
71 uses SVE. This is true for kernels between 4.15.0 and before 6.2.0, except
72 for 5.14.0 which was patched. For these versions return false to avoid using
73 SVE ifuncs.
74 Parse the kernel version into a 24-bit kernel.major.minor value without
75 calling any library functions. If uname() is not supported or if the version
76 format is not recognized, assume the kernel is modern and return true. */
77
78static inline bool
79prefer_sve_ifuncs (void)
80{
81 struct utsname buf;
82 const char *p = &buf.release[0];
83 int kernel = 0;
84 int val;
85
86 if (__uname (&buf) < 0)
87 return true;
88
89 for (int shift = 16; shift >= 0; shift -= 8)
90 {
91 for (val = 0; *p >= '0' && *p <= '9'; p++)
92 val = val * 10 + *p - '0';
93 kernel |= (val & 255) << shift;
94 if (*p++ != '.')
95 break;
96 }
97
98 if (kernel >= 0x060200 || kernel == 0x050e00)
99 return true;
100 if (kernel >= 0x040f00)
101 return false;
102 return true;
103}
104
105#endif
106
107static inline void
108init_cpu_features (struct cpu_features *cpu_features)
109{
110 register uint64_t midr = UINT64_MAX;
111
112 /* Get the tunable override. */
113 const struct tunable_str_t *mcpu = TUNABLE_GET (glibc, cpu, name,
114 struct tunable_str_t *,
115 NULL);
116 if (mcpu != NULL)
117 midr = get_midr_from_mcpu (mcpu);
118
119 /* If there was no useful tunable override, query the MIDR if the kernel
120 allows it. */
121 if (midr == UINT64_MAX)
122 {
123 if (GLRO (dl_hwcap) & HWCAP_CPUID)
124 asm volatile ("mrs %0, midr_el1" : "=r"(midr));
125 else
126 midr = 0;
127 }
128
129 cpu_features->midr_el1 = midr;
130
131 /* Check if ZVA is enabled. */
132 unsigned dczid;
133 asm volatile ("mrs %0, dczid_el0" : "=r"(dczid));
134
135 if ((dczid & DCZID_DZP_MASK) == 0)
136 cpu_features->zva_size = 4 << (dczid & DCZID_BS_MASK);
137
138 /* Check if BTI is supported. */
139 cpu_features->bti = GLRO (dl_hwcap2) & HWCAP2_BTI;
140
141 /* Setup memory tagging support if the HW and kernel support it, and if
142 the user has requested it. */
143 cpu_features->mte_state = 0;
144
145#ifdef USE_MTAG
146 int mte_state = TUNABLE_GET (glibc, mem, tagging, unsigned, 0);
147 cpu_features->mte_state = (GLRO (dl_hwcap2) & HWCAP2_MTE) ? mte_state : 0;
148 /* If we lack the MTE feature, disable the tunable, since it will
149 otherwise cause instructions that won't run on this CPU to be used. */
150 TUNABLE_SET (glibc, mem, tagging, cpu_features->mte_state);
151
152 if (cpu_features->mte_state & 4)
153 /* Enable choosing system-preferred faulting mode. */
154 __prctl (PR_SET_TAGGED_ADDR_CTRL,
155 (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC
156 | MTE_ALLOWED_TAGS),
157 0, 0, 0);
158 else if (cpu_features->mte_state & 2)
159 __prctl (PR_SET_TAGGED_ADDR_CTRL,
160 (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | MTE_ALLOWED_TAGS),
161 0, 0, 0);
162 else if (cpu_features->mte_state)
163 __prctl (PR_SET_TAGGED_ADDR_CTRL,
164 (PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_ASYNC | MTE_ALLOWED_TAGS),
165 0, 0, 0);
166#endif
167
168 /* Check if SVE is supported. */
169 cpu_features->sve = GLRO (dl_hwcap) & HWCAP_SVE;
170
171 cpu_features->prefer_sve_ifuncs = cpu_features->sve;
172
173#if __LINUX_KERNEL_VERSION < 0x060200
174 if (cpu_features->sve)
175 cpu_features->prefer_sve_ifuncs = prefer_sve_ifuncs ();
176#endif
177
178 /* Check if MOPS is supported. */
179 cpu_features->mops = GLRO (dl_hwcap2) & HWCAP2_MOPS;
180}
181

source code of glibc/sysdeps/unix/sysv/linux/aarch64/cpu-features.c