1/* Header defining the minimum x86 ISA level
2 Copyright (C) 2022-2024 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 In addition to the permissions in the GNU Lesser General Public
11 License, the Free Software Foundation gives you unlimited
12 permission to link the compiled version of this file with other
13 programs, and to distribute those programs without any restriction
14 coming from the use of this file. (The Lesser General Public
15 License restrictions do apply in other respects; for example, they
16 cover modification of the file, and distribution when not linked
17 into another program.)
18
19 The GNU C Library is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
22 Lesser General Public License for more details.
23
24 You should have received a copy of the GNU Lesser General Public
25 License along with the GNU C Library; if not, see
26 <https://www.gnu.org/licenses/>. */
27
28#ifndef _ISA_LEVEL_H
29#define _ISA_LEVEL_H
30
31#if defined __SSE__ && defined __SSE2__
32/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */
33# define __X86_ISA_V1 1
34#else
35# define __X86_ISA_V1 0
36#endif
37
38#ifdef __x86_64__
39# ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
40# define __GCC_HAVE_SYNC_COMPARE_AND_SWAP
41# endif
42#else
43# ifdef __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
44# define __GCC_HAVE_SYNC_COMPARE_AND_SWAP
45# endif
46#endif
47
48#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP \
49 && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \
50 && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__
51/* NB: ISAs in x86-64 ISA level v2 are used. */
52# define __X86_ISA_V2 1
53#else
54# define __X86_ISA_V2 0
55#endif
56
57#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \
58 && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \
59 && defined __BMI__ && defined __BMI2__
60/* NB: ISAs in x86-64 ISA level v3 are used. */
61# define __X86_ISA_V3 1
62#else
63# define __X86_ISA_V3 0
64#endif
65
66#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \
67 && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__
68/* NB: ISAs in x86-64 ISA level v4 are used. */
69# define __X86_ISA_V4 1
70#else
71# define __X86_ISA_V4 0
72#endif
73
74#ifndef MINIMUM_X86_ISA_LEVEL
75# define MINIMUM_X86_ISA_LEVEL \
76 (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4)
77#endif
78
79/* Depending on the minimum ISA level, a feature check result can be a
80 compile-time constant.. */
81
82
83/* For CPU_FEATURE_USABLE_P. */
84
85/* ISA level >= 4 guaranteed includes. */
86#define AVX512F_X86_ISA_LEVEL 4
87#define AVX512VL_X86_ISA_LEVEL 4
88#define AVX512BW_X86_ISA_LEVEL 4
89#define AVX512DQ_X86_ISA_LEVEL 4
90
91/* ISA level >= 3 guaranteed includes. */
92#define AVX_X86_ISA_LEVEL 3
93#define AVX2_X86_ISA_LEVEL 3
94#define BMI1_X86_ISA_LEVEL 3
95#define BMI2_X86_ISA_LEVEL 3
96#define LZCNT_X86_ISA_LEVEL 3
97#define MOVBE_X86_ISA_LEVEL 3
98
99/* ISA level >= 2 guaranteed includes. */
100#define SSE4_2_X86_ISA_LEVEL 2
101#define SSE4_1_X86_ISA_LEVEL 2
102#define SSSE3_X86_ISA_LEVEL 2
103
104
105/* For X86_ISA_CPU_FEATURES_ARCH_P. */
106
107/* NB: This feature is enabled when ISA level >= 3, which was disabled
108 for the following CPUs:
109 - AMD Excavator
110 when ISA level < 3. */
111#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3
112
113/* NB: This feature is disabled when ISA level >= 3, which was enabled
114 for the following CPUs:
115 - Intel KNL
116 when ISA level < 3. */
117#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3
118
119/* NB: This feature is disable when ISA level >= 3. All CPUs with
120 this feature don't run on glibc built with ISA level >= 3. */
121#define Slow_SSE42_X86_ISA_LEVEL 3
122
123/* Feature(s) enabled when ISA level >= 2. */
124#define Fast_Unaligned_Load_X86_ISA_LEVEL 2
125
126/* NB: This feature is disable when ISA level >= 2, which was enabled
127 for the early Atom CPUs. */
128#define Slow_BSF_X86_ISA_LEVEL 2
129
130
131/* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P
132 macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P
133 runtime checks. They differ in two ways.
134
135 1. The USABLE_P version is evaluated to true when the feature
136 is enabled.
137
138 2. The ARCH_P version has a third argument `not`. The `not`
139 argument can either be `!` or empty. If the feature is
140 enabled above an ISA level, the third argument should be empty
141 and the expression is evaluated to true when the feature is
142 enabled. If the feature is disabled above an ISA level, the
143 third argument should be `!` and the expression is evaluated
144 to true when the feature is disabled.
145 */
146
147#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \
148 (((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL) \
149 || CPU_FEATURE_USABLE_P (ptr, name))
150
151#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name, not) \
152 (((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL) \
153 || not CPU_FEATURES_ARCH_P (ptr, name))
154
155#define ISA_SHOULD_BUILD(isa_build_level) \
156 (MINIMUM_X86_ISA_LEVEL <= (isa_build_level) && IS_IN (libc)) \
157 || defined ISA_DEFAULT_IMPL
158
159#endif
160

source code of glibc/sysdeps/x86/isa-level.h