1 | /* Header defining the minimum x86 ISA level |
2 | Copyright (C) 2022-2024 Free Software Foundation, Inc. |
3 | This file is part of the GNU C Library. |
4 | |
5 | The GNU C Library is free software; you can redistribute it and/or |
6 | modify it under the terms of the GNU Lesser General Public |
7 | License as published by the Free Software Foundation; either |
8 | version 2.1 of the License, or (at your option) any later version. |
9 | |
10 | In addition to the permissions in the GNU Lesser General Public |
11 | License, the Free Software Foundation gives you unlimited |
12 | permission to link the compiled version of this file with other |
13 | programs, and to distribute those programs without any restriction |
14 | coming from the use of this file. (The Lesser General Public |
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16 | cover modification of the file, and distribution when not linked |
17 | into another program.) |
18 | |
19 | The GNU C Library is distributed in the hope that it will be useful, |
20 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
21 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
22 | Lesser General Public License for more details. |
23 | |
24 | You should have received a copy of the GNU Lesser General Public |
25 | License along with the GNU C Library; if not, see |
26 | <https://www.gnu.org/licenses/>. */ |
27 | |
28 | #ifndef _ISA_LEVEL_H |
29 | #define _ISA_LEVEL_H |
30 | |
31 | #if defined __SSE__ && defined __SSE2__ |
32 | /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */ |
33 | # define __X86_ISA_V1 1 |
34 | #else |
35 | # define __X86_ISA_V1 0 |
36 | #endif |
37 | |
38 | #if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \ |
39 | && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \ |
40 | && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__ |
41 | /* NB: ISAs in x86-64 ISA level v2 are used. */ |
42 | # define __X86_ISA_V2 1 |
43 | #else |
44 | # define __X86_ISA_V2 0 |
45 | #endif |
46 | |
47 | #if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \ |
48 | && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \ |
49 | && defined __BMI__ && defined __BMI2__ |
50 | /* NB: ISAs in x86-64 ISA level v3 are used. */ |
51 | # define __X86_ISA_V3 1 |
52 | #else |
53 | # define __X86_ISA_V3 0 |
54 | #endif |
55 | |
56 | #if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \ |
57 | && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__ |
58 | /* NB: ISAs in x86-64 ISA level v4 are used. */ |
59 | # define __X86_ISA_V4 1 |
60 | #else |
61 | # define __X86_ISA_V4 0 |
62 | #endif |
63 | |
64 | #define MINIMUM_X86_ISA_LEVEL \ |
65 | (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4) |
66 | |
67 | /* Depending on the minimum ISA level, a feature check result can be a |
68 | compile-time constant.. */ |
69 | |
70 | |
71 | /* For CPU_FEATURE_USABLE_P. */ |
72 | |
73 | /* ISA level >= 4 guaranteed includes. */ |
74 | #define AVX512F_X86_ISA_LEVEL 4 |
75 | #define AVX512VL_X86_ISA_LEVEL 4 |
76 | #define AVX512BW_X86_ISA_LEVEL 4 |
77 | #define AVX512DQ_X86_ISA_LEVEL 4 |
78 | |
79 | /* ISA level >= 3 guaranteed includes. */ |
80 | #define AVX_X86_ISA_LEVEL 3 |
81 | #define AVX2_X86_ISA_LEVEL 3 |
82 | #define BMI1_X86_ISA_LEVEL 3 |
83 | #define BMI2_X86_ISA_LEVEL 3 |
84 | #define LZCNT_X86_ISA_LEVEL 3 |
85 | #define MOVBE_X86_ISA_LEVEL 3 |
86 | |
87 | /* ISA level >= 2 guaranteed includes. */ |
88 | #define SSE4_2_X86_ISA_LEVEL 2 |
89 | #define SSE4_1_X86_ISA_LEVEL 2 |
90 | #define SSSE3_X86_ISA_LEVEL 2 |
91 | |
92 | |
93 | /* For X86_ISA_CPU_FEATURES_ARCH_P. */ |
94 | |
95 | /* NB: This feature is enabled when ISA level >= 3, which was disabled |
96 | for the following CPUs: |
97 | - AMD Excavator |
98 | when ISA level < 3. */ |
99 | #define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3 |
100 | |
101 | /* NB: This feature is disabled when ISA level >= 3, which was enabled |
102 | for the following CPUs: |
103 | - Intel KNL |
104 | when ISA level < 3. */ |
105 | #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 |
106 | |
107 | /* NB: This feature is disable when ISA level >= 3. All CPUs with |
108 | this feature don't run on glibc built with ISA level >= 3. */ |
109 | #define Slow_SSE42_X86_ISA_LEVEL 3 |
110 | |
111 | /* Feature(s) enabled when ISA level >= 2. */ |
112 | #define Fast_Unaligned_Load_X86_ISA_LEVEL 2 |
113 | |
114 | /* NB: This feature is disable when ISA level >= 2, which was enabled |
115 | for the early Atom CPUs. */ |
116 | #define Slow_BSF_X86_ISA_LEVEL 2 |
117 | |
118 | |
119 | /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P |
120 | macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P |
121 | runtime checks. They differ in two ways. |
122 | |
123 | 1. The USABLE_P version is evaluated to true when the feature |
124 | is enabled. |
125 | |
126 | 2. The ARCH_P version has a third argument `not`. The `not` |
127 | argument can either be `!` or empty. If the feature is |
128 | enabled above an ISA level, the third argument should be empty |
129 | and the expression is evaluated to true when the feature is |
130 | enabled. If the feature is disabled above an ISA level, the |
131 | third argument should be `!` and the expression is evaluated |
132 | to true when the feature is disabled. |
133 | */ |
134 | |
135 | #define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \ |
136 | (((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL) \ |
137 | || CPU_FEATURE_USABLE_P (ptr, name)) |
138 | |
139 | #define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name, not) \ |
140 | (((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL) \ |
141 | || not CPU_FEATURES_ARCH_P (ptr, name)) |
142 | |
143 | #define ISA_SHOULD_BUILD(isa_build_level) \ |
144 | (MINIMUM_X86_ISA_LEVEL <= (isa_build_level) && IS_IN (libc)) \ |
145 | || defined ISA_DEFAULT_IMPL |
146 | |
147 | #endif |
148 | |