1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * linux/arch/arm/boot/compressed/head-sa1100.S |
4 | * |
5 | * Copyright (C) 1999 Nicolas Pitre <nico@fluxnic.net> |
6 | * |
7 | * SA1100 specific tweaks. This is merged into head.S by the linker. |
8 | * |
9 | */ |
10 | |
11 | #include <linux/linkage.h> |
12 | #include <asm/mach-types.h> |
13 | |
14 | .section ".start" , "ax" |
15 | .arch armv4 |
16 | |
17 | __SA1100_start: |
18 | |
19 | @ Preserve r8/r7 i.e. kernel entry values |
20 | #ifdef CONFIG_SA1100_COLLIE |
21 | mov r7, #MACH_TYPE_COLLIE |
22 | #endif |
23 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
24 | ands r0, r0, #0x0d |
25 | beq 99f |
26 | |
27 | @ Data cache might be active. |
28 | @ Be sure to flush kernel binary out of the cache, |
29 | @ whatever state it is, before it is turned off. |
30 | @ This is done by fetching through currently executed |
31 | @ memory to be sure we hit the same cache. |
32 | bic r2, pc, #0x1f |
33 | add r3, r2, #0x4000 @ 16 kb is quite enough... |
34 | 1: ldr r0, [r2], #32 |
35 | teq r2, r3 |
36 | bne 1b |
37 | mcr p15, 0, r0, c7, c10, 4 @ drain WB |
38 | mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches |
39 | |
40 | @ disabling MMU and caches |
41 | mrc p15, 0, r0, c1, c0, 0 @ read control reg |
42 | bic r0, r0, #0x0d @ clear WB, DC, MMU |
43 | bic r0, r0, #0x1000 @ clear Icache |
44 | mcr p15, 0, r0, c1, c0, 0 |
45 | 99: |
46 | |