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| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
|---|---|
| 2 | /* |
| 3 | * arch/arm/include/asm/hardware/cache-l2x0.h |
| 4 | * |
| 5 | * Copyright (C) 2007 ARM Limited |
| 6 | */ |
| 7 | |
| 8 | #ifndef __ASM_ARM_HARDWARE_L2X0_H |
| 9 | #define __ASM_ARM_HARDWARE_L2X0_H |
| 10 | |
| 11 | #include <linux/errno.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/types.h> |
| 14 | |
| 15 | #define L2X0_CACHE_ID 0x000 |
| 16 | #define L2X0_CACHE_TYPE 0x004 |
| 17 | #define L2X0_CTRL 0x100 |
| 18 | #define L2X0_AUX_CTRL 0x104 |
| 19 | #define L310_TAG_LATENCY_CTRL 0x108 |
| 20 | #define L310_DATA_LATENCY_CTRL 0x10C |
| 21 | #define L2X0_EVENT_CNT_CTRL 0x200 |
| 22 | #define L2X0_EVENT_CNT1_CFG 0x204 |
| 23 | #define L2X0_EVENT_CNT0_CFG 0x208 |
| 24 | #define L2X0_EVENT_CNT1_VAL 0x20C |
| 25 | #define L2X0_EVENT_CNT0_VAL 0x210 |
| 26 | #define L2X0_INTR_MASK 0x214 |
| 27 | #define L2X0_MASKED_INTR_STAT 0x218 |
| 28 | #define L2X0_RAW_INTR_STAT 0x21C |
| 29 | #define L2X0_INTR_CLEAR 0x220 |
| 30 | #define L2X0_CACHE_SYNC 0x730 |
| 31 | #define L2X0_DUMMY_REG 0x740 |
| 32 | #define L2X0_INV_LINE_PA 0x770 |
| 33 | #define L2X0_INV_WAY 0x77C |
| 34 | #define L2X0_CLEAN_LINE_PA 0x7B0 |
| 35 | #define L2X0_CLEAN_LINE_IDX 0x7B8 |
| 36 | #define L2X0_CLEAN_WAY 0x7BC |
| 37 | #define L2X0_CLEAN_INV_LINE_PA 0x7F0 |
| 38 | #define L2X0_CLEAN_INV_LINE_IDX 0x7F8 |
| 39 | #define L2X0_CLEAN_INV_WAY 0x7FC |
| 40 | /* |
| 41 | * The lockdown registers repeat 8 times for L310, the L210 has only one |
| 42 | * D and one I lockdown register at 0x0900 and 0x0904. |
| 43 | */ |
| 44 | #define L2X0_LOCKDOWN_WAY_D_BASE 0x900 |
| 45 | #define L2X0_LOCKDOWN_WAY_I_BASE 0x904 |
| 46 | #define L2X0_LOCKDOWN_STRIDE 0x08 |
| 47 | #define L310_ADDR_FILTER_START 0xC00 |
| 48 | #define L310_ADDR_FILTER_END 0xC04 |
| 49 | #define L2X0_TEST_OPERATION 0xF00 |
| 50 | #define L2X0_LINE_DATA 0xF10 |
| 51 | #define L2X0_LINE_TAG 0xF30 |
| 52 | #define L2X0_DEBUG_CTRL 0xF40 |
| 53 | #define L310_PREFETCH_CTRL 0xF60 |
| 54 | #define L310_POWER_CTRL 0xF80 |
| 55 | #define L310_DYNAMIC_CLK_GATING_EN (1 << 1) |
| 56 | #define L310_STNDBY_MODE_EN (1 << 0) |
| 57 | |
| 58 | /* Registers shifts and masks */ |
| 59 | #define L2X0_CACHE_ID_PART_MASK (0xf << 6) |
| 60 | #define L2X0_CACHE_ID_PART_L210 (1 << 6) |
| 61 | #define L2X0_CACHE_ID_PART_L220 (2 << 6) |
| 62 | #define L2X0_CACHE_ID_PART_L310 (3 << 6) |
| 63 | #define L2X0_CACHE_ID_RTL_MASK 0x3f |
| 64 | #define L210_CACHE_ID_RTL_R0P2_02 0x00 |
| 65 | #define L210_CACHE_ID_RTL_R0P1 0x01 |
| 66 | #define L210_CACHE_ID_RTL_R0P2_01 0x02 |
| 67 | #define L210_CACHE_ID_RTL_R0P3 0x03 |
| 68 | #define L210_CACHE_ID_RTL_R0P4 0x0b |
| 69 | #define L210_CACHE_ID_RTL_R0P5 0x0f |
| 70 | #define L220_CACHE_ID_RTL_R1P7_01REL0 0x06 |
| 71 | #define L310_CACHE_ID_RTL_R0P0 0x00 |
| 72 | #define L310_CACHE_ID_RTL_R1P0 0x02 |
| 73 | #define L310_CACHE_ID_RTL_R2P0 0x04 |
| 74 | #define L310_CACHE_ID_RTL_R3P0 0x05 |
| 75 | #define L310_CACHE_ID_RTL_R3P1 0x06 |
| 76 | #define L310_CACHE_ID_RTL_R3P1_50REL0 0x07 |
| 77 | #define L310_CACHE_ID_RTL_R3P2 0x08 |
| 78 | #define L310_CACHE_ID_RTL_R3P3 0x09 |
| 79 | |
| 80 | #define L2X0_EVENT_CNT_CTRL_ENABLE BIT(0) |
| 81 | |
| 82 | #define L2X0_EVENT_CNT_CFG_SRC_SHIFT 2 |
| 83 | #define L2X0_EVENT_CNT_CFG_SRC_MASK 0xf |
| 84 | #define L2X0_EVENT_CNT_CFG_SRC_DISABLED 0 |
| 85 | #define L2X0_EVENT_CNT_CFG_INT_DISABLED 0 |
| 86 | #define L2X0_EVENT_CNT_CFG_INT_INCR 1 |
| 87 | #define L2X0_EVENT_CNT_CFG_INT_OVERFLOW 2 |
| 88 | |
| 89 | /* L2C auxiliary control register - bits common to L2C-210/220/310 */ |
| 90 | #define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17 |
| 91 | #define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17) |
| 92 | #define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17) |
| 93 | #define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20) |
| 94 | #define L2C_AUX_CTRL_PARITY_ENABLE BIT(21) |
| 95 | #define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22) |
| 96 | /* L2C-210/220 common bits */ |
| 97 | #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0 |
| 98 | #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0) |
| 99 | #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3 |
| 100 | #define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3) |
| 101 | #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6 |
| 102 | #define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6) |
| 103 | #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9 |
| 104 | #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9) |
| 105 | #define L2X0_AUX_CTRL_ASSOC_SHIFT 13 |
| 106 | #define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13) |
| 107 | /* L2C-210 specific bits */ |
| 108 | #define L210_AUX_CTRL_WRAP_DISABLE BIT(12) |
| 109 | #define L210_AUX_CTRL_WA_OVERRIDE BIT(23) |
| 110 | #define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24) |
| 111 | /* L2C-220 specific bits */ |
| 112 | #define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) |
| 113 | #define L220_AUX_CTRL_FWA_SHIFT 23 |
| 114 | #define L220_AUX_CTRL_FWA_MASK (3 << 23) |
| 115 | #define L220_AUX_CTRL_NS_LOCKDOWN BIT(26) |
| 116 | #define L220_AUX_CTRL_NS_INT_CTRL BIT(27) |
| 117 | /* L2C-310 specific bits */ |
| 118 | #define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */ |
| 119 | #define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */ |
| 120 | #define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */ |
| 121 | #define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12) |
| 122 | #define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16) |
| 123 | #define L310_AUX_CTRL_FWA_SHIFT 23 |
| 124 | #define L310_AUX_CTRL_FWA_MASK (3 << 23) |
| 125 | #define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */ |
| 126 | #define L310_AUX_CTRL_NS_LOCKDOWN BIT(26) |
| 127 | #define L310_AUX_CTRL_NS_INT_CTRL BIT(27) |
| 128 | #define L310_AUX_CTRL_DATA_PREFETCH BIT(28) |
| 129 | #define L310_AUX_CTRL_INSTR_PREFETCH BIT(29) |
| 130 | #define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */ |
| 131 | |
| 132 | #define L310_LATENCY_CTRL_SETUP(n) ((n) << 0) |
| 133 | #define L310_LATENCY_CTRL_RD(n) ((n) << 4) |
| 134 | #define L310_LATENCY_CTRL_WR(n) ((n) << 8) |
| 135 | |
| 136 | #define L310_ADDR_FILTER_EN 1 |
| 137 | |
| 138 | #define L310_PREFETCH_CTRL_OFFSET_MASK 0x1f |
| 139 | #define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR BIT(23) |
| 140 | #define L310_PREFETCH_CTRL_PREFETCH_DROP BIT(24) |
| 141 | #define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP BIT(27) |
| 142 | #define L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28) |
| 143 | #define L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29) |
| 144 | #define L310_PREFETCH_CTRL_DBL_LINEFILL BIT(30) |
| 145 | |
| 146 | #define L2X0_CTRL_EN 1 |
| 147 | |
| 148 | #define L2X0_WAY_SIZE_SHIFT 3 |
| 149 | |
| 150 | #ifndef __ASSEMBLY__ |
| 151 | extern void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask); |
| 152 | #if defined(CONFIG_CACHE_L2X0) && defined(CONFIG_OF) |
| 153 | extern int l2x0_of_init(u32 aux_val, u32 aux_mask); |
| 154 | #else |
| 155 | static inline int l2x0_of_init(u32 aux_val, u32 aux_mask) |
| 156 | { |
| 157 | return -ENODEV; |
| 158 | } |
| 159 | #endif |
| 160 | |
| 161 | #ifdef CONFIG_CACHE_L2X0_PMU |
| 162 | void l2x0_pmu_register(void __iomem *base, u32 part); |
| 163 | void l2x0_pmu_suspend(void); |
| 164 | void l2x0_pmu_resume(void); |
| 165 | #else |
| 166 | static inline void l2x0_pmu_register(void __iomem *base, u32 part) {} |
| 167 | static inline void l2x0_pmu_suspend(void) {} |
| 168 | static inline void l2x0_pmu_resume(void) {} |
| 169 | #endif |
| 170 | |
| 171 | struct l2x0_regs { |
| 172 | unsigned long phy_base; |
| 173 | unsigned long aux_ctrl; |
| 174 | /* |
| 175 | * Whether the following registers need to be saved/restored |
| 176 | * depends on platform |
| 177 | */ |
| 178 | unsigned long tag_latency; |
| 179 | unsigned long data_latency; |
| 180 | unsigned long filter_start; |
| 181 | unsigned long filter_end; |
| 182 | unsigned long prefetch_ctrl; |
| 183 | unsigned long pwr_ctrl; |
| 184 | unsigned long ctrl; |
| 185 | unsigned long aux2_ctrl; |
| 186 | }; |
| 187 | |
| 188 | extern struct l2x0_regs l2x0_saved_regs; |
| 189 | |
| 190 | #endif /* __ASSEMBLY__ */ |
| 191 | |
| 192 | #endif |
| 193 |
Warning: This file is not a C or C++ file. It does not have highlighting.