| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Debugging macro include header |
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| 4 | * |
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| 5 | * Copyright (C) 2011 Xilinx |
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| 6 | */ |
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| 7 | #define UART_CR_OFFSET 0x00 /* Control Register [8:0] */ |
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| 8 | #define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */ |
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| 9 | #define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */ |
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| 10 | |
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| 11 | #define UART_SR_TXFULL 0x00000010 /* TX FIFO full */ |
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| 12 | #define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */ |
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| 13 | |
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| 14 | #define UART0_PHYS 0xE0000000 |
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| 15 | #define UART0_VIRT 0xF0800000 |
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| 16 | #define UART1_PHYS 0xE0001000 |
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| 17 | #define UART1_VIRT 0xF0801000 |
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| 18 | |
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| 19 | #if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1) |
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| 20 | # define LL_UART_PADDR UART1_PHYS |
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| 21 | # define LL_UART_VADDR UART1_VIRT |
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| 22 | #else |
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| 23 | # define LL_UART_PADDR UART0_PHYS |
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| 24 | # define LL_UART_VADDR UART0_VIRT |
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| 25 | #endif |
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| 26 | |
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| 27 | .macro addruart, rp, rv, tmp |
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| 28 | ldr \rp, =LL_UART_PADDR @ physical |
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| 29 | ldr \rv, =LL_UART_VADDR @ virtual |
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| 30 | .endm |
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| 31 | |
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| 32 | .macro senduart,rd,rx |
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| 33 | strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA |
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| 34 | .endm |
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| 35 | |
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| 36 | .macro waituartcts,rd,rx |
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| 37 | .endm |
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| 38 | |
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| 39 | .macro waituarttxrdy,rd,rx |
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| 40 | 1001: ldr \rd, [\rx, #UART_SR_OFFSET] |
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| 41 | ARM_BE8( rev \rd, \rd ) |
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| 42 | tst \rd, #UART_SR_TXEMPTY |
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| 43 | beq 1001b |
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| 44 | .endm |
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| 45 | |
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| 46 | .macro busyuart,rd,rx |
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| 47 | 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register |
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| 48 | ARM_BE8( rev \rd, \rd ) |
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| 49 | tst \rd, #UART_SR_TXFULL @ |
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| 50 | bne 1002b @ wait if FIFO is full |
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| 51 | .endm |
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| 52 | |
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