| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #include <asm/assembler.h> |
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| 3 | #include <asm/unwind.h> |
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| 4 | |
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| 5 | #if __LINUX_ARM_ARCH__ >= 6 |
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| 6 | .macro bitop, name, instr |
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| 7 | ENTRY( \name ) |
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| 8 | UNWIND( .fnstart ) |
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| 9 | ands ip, r1, #3 |
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| 10 | strbne r1, [ip] @ assert word-aligned |
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| 11 | mov r2, #1 |
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| 12 | and r3, r0, #31 @ Get bit offset |
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| 13 | mov r0, r0, lsr #5 |
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| 14 | add r1, r1, r0, lsl #2 @ Get word offset |
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| 15 | #if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) |
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| 16 | .arch_extension mp |
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| 17 | ALT_SMP(W(pldw) [r1]) |
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| 18 | ALT_UP(W(nop)) |
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| 19 | #endif |
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| 20 | mov r3, r2, lsl r3 |
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| 21 | 1: ldrex r2, [r1] |
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| 22 | \instr r2, r2, r3 |
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| 23 | strex r0, r2, [r1] |
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| 24 | cmp r0, #0 |
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| 25 | bne 1b |
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| 26 | bx lr |
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| 27 | UNWIND( .fnend ) |
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| 28 | ENDPROC(\name ) |
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| 29 | .endm |
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| 30 | |
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| 31 | .macro __testop, name, instr, store, barrier |
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| 32 | ENTRY( \name ) |
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| 33 | UNWIND( .fnstart ) |
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| 34 | ands ip, r1, #3 |
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| 35 | strbne r1, [ip] @ assert word-aligned |
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| 36 | mov r2, #1 |
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| 37 | and r3, r0, #31 @ Get bit offset |
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| 38 | mov r0, r0, lsr #5 |
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| 39 | add r1, r1, r0, lsl #2 @ Get word offset |
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| 40 | mov r3, r2, lsl r3 @ create mask |
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| 41 | \barrier |
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| 42 | #if __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP) |
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| 43 | .arch_extension mp |
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| 44 | ALT_SMP(W(pldw) [r1]) |
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| 45 | ALT_UP(W(nop)) |
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| 46 | #endif |
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| 47 | 1: ldrex r2, [r1] |
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| 48 | ands r0, r2, r3 @ save old value of bit |
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| 49 | \instr r2, r2, r3 @ toggle bit |
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| 50 | strex ip, r2, [r1] |
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| 51 | cmp ip, #0 |
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| 52 | bne 1b |
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| 53 | \barrier |
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| 54 | cmp r0, #0 |
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| 55 | movne r0, #1 |
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| 56 | 2: bx lr |
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| 57 | UNWIND( .fnend ) |
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| 58 | ENDPROC(\name ) |
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| 59 | .endm |
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| 60 | |
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| 61 | .macro testop, name, instr, store |
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| 62 | __testop \name, \instr, \store, smp_dmb |
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| 63 | .endm |
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| 64 | |
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| 65 | .macro sync_testop, name, instr, store |
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| 66 | __testop \name, \instr, \store, __smp_dmb |
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| 67 | .endm |
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| 68 | #else |
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| 69 | .macro bitop, name, instr |
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| 70 | ENTRY( \name ) |
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| 71 | UNWIND( .fnstart ) |
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| 72 | ands ip, r1, #3 |
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| 73 | strbne r1, [ip] @ assert word-aligned |
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| 74 | and r2, r0, #31 |
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| 75 | mov r0, r0, lsr #5 |
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| 76 | mov r3, #1 |
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| 77 | mov r3, r3, lsl r2 |
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| 78 | save_and_disable_irqs ip |
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| 79 | ldr r2, [r1, r0, lsl #2] |
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| 80 | \instr r2, r2, r3 |
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| 81 | str r2, [r1, r0, lsl #2] |
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| 82 | restore_irqs ip |
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| 83 | ret lr |
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| 84 | UNWIND( .fnend ) |
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| 85 | ENDPROC(\name ) |
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| 86 | .endm |
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| 87 | |
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| 88 | /** |
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| 89 | * testop - implement a test_and_xxx_bit operation. |
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| 90 | * @instr: operational instruction |
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| 91 | * @store: store instruction |
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| 92 | * |
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| 93 | * Note: we can trivially conditionalise the store instruction |
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| 94 | * to avoid dirtying the data cache. |
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| 95 | */ |
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| 96 | .macro testop, name, instr, store |
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| 97 | ENTRY( \name ) |
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| 98 | UNWIND( .fnstart ) |
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| 99 | ands ip, r1, #3 |
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| 100 | strbne r1, [ip] @ assert word-aligned |
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| 101 | and r3, r0, #31 |
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| 102 | mov r0, r0, lsr #5 |
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| 103 | save_and_disable_irqs ip |
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| 104 | ldr r2, [r1, r0, lsl #2]! |
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| 105 | mov r0, #1 |
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| 106 | tst r2, r0, lsl r3 |
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| 107 | \instr r2, r2, r0, lsl r3 |
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| 108 | \store r2, [r1] |
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| 109 | moveq r0, #0 |
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| 110 | restore_irqs ip |
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| 111 | ret lr |
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| 112 | UNWIND( .fnend ) |
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| 113 | ENDPROC(\name ) |
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| 114 | .endm |
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| 115 | #endif |
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| 116 | |
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