1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* Generic definitions for Marvell Dove 88AP510 SoC */ |
3 | |
4 | #ifndef __ASM_ARCH_DOVE_H |
5 | #define __ASM_ARCH_DOVE_H |
6 | |
7 | #include "irqs.h" |
8 | |
9 | /* |
10 | * Marvell Dove address maps. |
11 | * |
12 | * phys virt size |
13 | * c8000000 fdb00000 1M Cryptographic SRAM |
14 | * e0000000 @runtime 128M PCIe-0 Memory space |
15 | * e8000000 @runtime 128M PCIe-1 Memory space |
16 | * f1000000 fec00000 1M on-chip south-bridge registers |
17 | * f1800000 fe400000 8M on-chip north-bridge registers |
18 | * f2000000 fee00000 1M PCIe-0 I/O space |
19 | * f2100000 fef00000 1M PCIe-1 I/O space |
20 | */ |
21 | |
22 | #define DOVE_CESA_PHYS_BASE 0xc8000000 |
23 | #define DOVE_CESA_VIRT_BASE IOMEM(0xfdb00000) |
24 | #define DOVE_CESA_SIZE SZ_1M |
25 | |
26 | #define DOVE_PCIE0_MEM_PHYS_BASE 0xe0000000 |
27 | #define DOVE_PCIE0_MEM_SIZE SZ_128M |
28 | |
29 | #define DOVE_PCIE1_MEM_PHYS_BASE 0xe8000000 |
30 | #define DOVE_PCIE1_MEM_SIZE SZ_128M |
31 | |
32 | #define DOVE_BOOTROM_PHYS_BASE 0xf8000000 |
33 | #define DOVE_BOOTROM_SIZE SZ_128M |
34 | |
35 | #define DOVE_SCRATCHPAD_PHYS_BASE 0xf0000000 |
36 | #define DOVE_SCRATCHPAD_VIRT_BASE IOMEM(0xfdd00000) |
37 | #define DOVE_SCRATCHPAD_SIZE SZ_1M |
38 | |
39 | #define DOVE_SB_REGS_PHYS_BASE 0xf1000000 |
40 | #define DOVE_SB_REGS_VIRT_BASE IOMEM(0xfec00000) |
41 | #define DOVE_SB_REGS_SIZE SZ_1M |
42 | |
43 | #define DOVE_NB_REGS_PHYS_BASE 0xf1800000 |
44 | #define DOVE_NB_REGS_VIRT_BASE IOMEM(0xfe400000) |
45 | #define DOVE_NB_REGS_SIZE SZ_8M |
46 | |
47 | #define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000 |
48 | #define DOVE_PCIE0_IO_BUS_BASE 0x00000000 |
49 | #define DOVE_PCIE0_IO_SIZE SZ_64K |
50 | |
51 | #define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000 |
52 | #define DOVE_PCIE1_IO_BUS_BASE 0x00010000 |
53 | #define DOVE_PCIE1_IO_SIZE SZ_64K |
54 | |
55 | /* |
56 | * Dove Core Registers Map |
57 | */ |
58 | |
59 | /* SPI, I2C, UART */ |
60 | #define DOVE_I2C_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x11000) |
61 | #define DOVE_UART0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12000) |
62 | #define DOVE_UART0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12000) |
63 | #define DOVE_UART1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12100) |
64 | #define DOVE_UART1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12100) |
65 | #define DOVE_UART2_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12200) |
66 | #define DOVE_UART2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12200) |
67 | #define DOVE_UART3_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x12300) |
68 | #define DOVE_UART3_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x12300) |
69 | #define DOVE_SPI0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x10600) |
70 | #define DOVE_SPI1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x14600) |
71 | |
72 | /* North-South Bridge */ |
73 | #define BRIDGE_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x20000) |
74 | #define BRIDGE_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x20000) |
75 | #define BRIDGE_WINS_BASE (BRIDGE_PHYS_BASE) |
76 | #define BRIDGE_WINS_SZ (0x80) |
77 | |
78 | /* Cryptographic Engine */ |
79 | #define DOVE_CRYPT_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x30000) |
80 | |
81 | /* PCIe 0 */ |
82 | #define DOVE_PCIE0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x40000) |
83 | |
84 | /* USB */ |
85 | #define DOVE_USB0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x50000) |
86 | #define DOVE_USB1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x51000) |
87 | |
88 | /* XOR 0 Engine */ |
89 | #define DOVE_XOR0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60800) |
90 | #define DOVE_XOR0_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60800) |
91 | #define DOVE_XOR0_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60A00) |
92 | #define DOVE_XOR0_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60A00) |
93 | |
94 | /* XOR 1 Engine */ |
95 | #define DOVE_XOR1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60900) |
96 | #define DOVE_XOR1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60900) |
97 | #define DOVE_XOR1_HIGH_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x60B00) |
98 | #define DOVE_XOR1_HIGH_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x60B00) |
99 | |
100 | /* Gigabit Ethernet */ |
101 | #define DOVE_GE00_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x70000) |
102 | |
103 | /* PCIe 1 */ |
104 | #define DOVE_PCIE1_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0x80000) |
105 | |
106 | /* CAFE */ |
107 | #define DOVE_SDIO0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x92000) |
108 | #define DOVE_SDIO1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x90000) |
109 | #define DOVE_CAM_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x94000) |
110 | #define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000) |
111 | |
112 | /* SATA */ |
113 | #define DOVE_SATA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xa0000) |
114 | |
115 | /* I2S/SPDIF */ |
116 | #define DOVE_AUD0_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb0000) |
117 | #define DOVE_AUD1_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xb4000) |
118 | |
119 | /* NAND Flash Controller */ |
120 | #define DOVE_NFC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xc0000) |
121 | |
122 | /* MPP, GPIO, Reset Sampling */ |
123 | #define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0200) |
124 | #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10) |
125 | #define DOVE_RESET_SAMPLE_LO (DOVE_MPP_VIRT_BASE + 0x014) |
126 | #define DOVE_RESET_SAMPLE_HI (DOVE_MPP_VIRT_BASE + 0x018) |
127 | #define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0400) |
128 | #define DOVE_GPIO_HI_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0420) |
129 | #define DOVE_GPIO2_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe8400) |
130 | #define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe803c) |
131 | #define DOVE_AU1_SPDIFO_GPIO_EN (1 << 1) |
132 | #define DOVE_NAND_GPIO_EN (1 << 0) |
133 | #define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40) |
134 | #define DOVE_SPI_GPIO_SEL (1 << 5) |
135 | #define DOVE_UART1_GPIO_SEL (1 << 4) |
136 | #define DOVE_AU1_GPIO_SEL (1 << 3) |
137 | #define DOVE_CAM_GPIO_SEL (1 << 2) |
138 | #define DOVE_SD1_GPIO_SEL (1 << 1) |
139 | #define DOVE_SD0_GPIO_SEL (1 << 0) |
140 | |
141 | /* Power Management */ |
142 | #define DOVE_PMU_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xd0000) |
143 | #define DOVE_PMU_SIG_CTRL (DOVE_PMU_VIRT_BASE + 0x802c) |
144 | |
145 | /* Real Time Clock */ |
146 | #define DOVE_RTC_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xd8500) |
147 | |
148 | /* AC97 */ |
149 | #define DOVE_AC97_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe0000) |
150 | #define DOVE_AC97_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe0000) |
151 | |
152 | /* Peripheral DMA */ |
153 | #define DOVE_PDMA_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xe4000) |
154 | #define DOVE_PDMA_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE + 0xe4000) |
155 | |
156 | #define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE + 0xe802C) |
157 | #define DOVE_TWSI_ENABLE_OPTION1 (1 << 7) |
158 | #define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE + 0xe8030) |
159 | #define DOVE_TWSI_ENABLE_OPTION2 (1 << 20) |
160 | #define DOVE_TWSI_ENABLE_OPTION3 (1 << 21) |
161 | #define DOVE_TWSI_OPTION3_GPIO (1 << 22) |
162 | #define DOVE_SSP_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0xec000) |
163 | #define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE + 0xe8034) |
164 | #define DOVE_SSP_ON_AU1 (1 << 0) |
165 | #define DOVE_SSP_CLOCK_ENABLE (1 << 1) |
166 | #define DOVE_SSP_BPB_CLOCK_SRC_SSP (1 << 11) |
167 | /* Memory Controller */ |
168 | #define DOVE_MC_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x00000) |
169 | #define DOVE_MC_WINS_BASE (DOVE_MC_PHYS_BASE + 0x100) |
170 | #define DOVE_MC_WINS_SZ (0x8) |
171 | #define DOVE_MC_VIRT_BASE (DOVE_NB_REGS_VIRT_BASE + 0x00000) |
172 | |
173 | /* LCD Controller */ |
174 | #define DOVE_LCD_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) |
175 | #define DOVE_LCD1_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x20000) |
176 | #define DOVE_LCD2_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x10000) |
177 | #define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000) |
178 | |
179 | /* Graphic Engine */ |
180 | #define DOVE_GPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x40000) |
181 | |
182 | /* Video Engine */ |
183 | #define DOVE_VPU_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x400000) |
184 | |
185 | #endif |
186 | |