| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef __ARCH_DOVE_MPP_CODED_H |
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| 3 | #define __ARCH_DOVE_MPP_CODED_H |
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| 4 | |
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| 5 | #define MPP(_num, _sel, _in, _out) ( \ |
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| 6 | /* MPP number */ ((_num) & 0xff) | \ |
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| 7 | /* MPP select value */ (((_sel) & 0xf) << 8) | \ |
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| 8 | /* may be input signal */ ((!!(_in)) << 12) | \ |
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| 9 | /* may be output signal */ ((!!(_out)) << 13)) |
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| 10 | |
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| 11 | #define MPP0_GPIO0 MPP(0, 0x0, 1, 1) |
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| 12 | #define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0) |
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| 13 | #define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0) |
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| 14 | #define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0) |
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| 15 | |
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| 16 | #define MPP1_GPIO1 MPP(1, 0x0, 1, 1) |
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| 17 | #define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0) |
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| 18 | #define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0) |
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| 19 | #define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0) |
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| 20 | |
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| 21 | #define MPP2_GPIO2 MPP(2, 0x0, 1, 1) |
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| 22 | #define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0) |
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| 23 | #define MPP2_UA2_TXD MPP(2, 0x2, 0, 0) |
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| 24 | #define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0) |
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| 25 | #define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0) |
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| 26 | |
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| 27 | #define MPP3_GPIO3 MPP(3, 0x0, 1, 1) |
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| 28 | #define MPP3_SATA_ACT MPP(3, 0x1, 0, 0) |
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| 29 | #define MPP3_UA2_RXD MPP(3, 0x2, 0, 0) |
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| 30 | #define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0) |
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| 31 | #define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0) |
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| 32 | #define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0) |
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| 33 | |
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| 34 | #define MPP4_GPIO4 MPP(4, 0x0, 1, 1) |
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| 35 | #define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0) |
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| 36 | #define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0) |
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| 37 | #define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0) |
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| 38 | |
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| 39 | #define MPP5_GPIO5 MPP(5, 0x0, 1, 1) |
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| 40 | #define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0) |
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| 41 | #define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0) |
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| 42 | #define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0) |
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| 43 | |
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| 44 | #define MPP6_GPIO6 MPP(6, 0x0, 1, 1) |
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| 45 | #define MPP6_UA3_TXD MPP(6, 0x2, 0, 0) |
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| 46 | #define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0) |
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| 47 | #define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0) |
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| 48 | |
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| 49 | #define MPP7_GPIO7 MPP(7, 0x0, 1, 1) |
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| 50 | #define MPP7_UA3_RXD MPP(7, 0x2, 0, 0) |
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| 51 | #define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0) |
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| 52 | #define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0) |
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| 53 | |
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| 54 | #define MPP8_GPIO8 MPP(8, 0x0, 1, 1) |
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| 55 | #define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0) |
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| 56 | |
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| 57 | #define MPP9_GPIO9 MPP(9, 0x0, 1, 1) |
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| 58 | #define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0) |
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| 59 | |
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| 60 | #define MPP10_GPIO10 MPP(10, 0x0, 1, 1) |
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| 61 | #define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0) |
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| 62 | |
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| 63 | #define MPP11_GPIO11 MPP(11, 0x0, 1, 1) |
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| 64 | #define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0) |
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| 65 | #define MPP11_SATA_ACT MPP(11, 0x2, 0, 0) |
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| 66 | #define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0) |
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| 67 | #define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0) |
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| 68 | #define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0) |
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| 69 | |
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| 70 | #define MPP12_GPIO12 MPP(12, 0x0, 1, 1) |
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| 71 | #define MPP12_SATA_ACT MPP(12, 0x1, 0, 0) |
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| 72 | #define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0) |
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| 73 | #define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0) |
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| 74 | #define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0) |
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| 75 | |
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| 76 | #define MPP13_GPIO13 MPP(13, 0x0, 1, 1) |
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| 77 | #define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0) |
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| 78 | #define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0) |
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| 79 | #define MPP13_SDIO1WP MPP(13, 0x4, 0, 0) |
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| 80 | #define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0) |
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| 81 | |
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| 82 | #define MPP14_GPIO14 MPP(14, 0x0, 1, 1) |
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| 83 | #define MPP14_UA2_TXD MPP(14, 0x2, 0, 0) |
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| 84 | #define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0) |
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| 85 | #define MPP14_SSP_RXD MPP(14, 0x5, 0, 0) |
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| 86 | |
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| 87 | #define MPP15_GPIO15 MPP(15, 0x0, 1, 1) |
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| 88 | #define MPP15_UA2_RXD MPP(15, 0x2, 0, 0) |
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| 89 | #define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0) |
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| 90 | #define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0) |
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| 91 | |
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| 92 | #define MPP16_GPIO16 MPP(16, 0x0, 1, 1) |
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| 93 | #define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0) |
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| 94 | #define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0) |
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| 95 | #define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0) |
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| 96 | #define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0) |
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| 97 | |
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| 98 | #define MPP17_GPIO17 MPP(17, 0x0, 1, 1) |
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| 99 | #define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0) |
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| 100 | #define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0) |
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| 101 | #define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0) |
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| 102 | #define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0) |
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| 103 | #define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0) |
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| 104 | |
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| 105 | #define MPP18_GPIO18 MPP(18, 0x0, 1, 1) |
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| 106 | #define MPP18_UA3_TXD MPP(18, 0x2, 0, 0) |
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| 107 | #define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0) |
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| 108 | #define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0) |
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| 109 | #define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0) |
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| 110 | |
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| 111 | #define MPP19_GPIO19 MPP(19, 0x0, 1, 1) |
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| 112 | #define MPP19_UA3_RXD MPP(19, 0x2, 0, 0) |
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| 113 | #define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0) |
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| 114 | #define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0) |
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| 115 | |
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| 116 | #define MPP20_GPIO20 MPP(20, 0x0, 1, 1) |
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| 117 | #define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0) |
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| 118 | #define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0) |
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| 119 | #define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0) |
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| 120 | #define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0) |
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| 121 | #define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0) |
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| 122 | |
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| 123 | #define MPP21_GPIO21 MPP(21, 0x0, 1, 1) |
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| 124 | #define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0) |
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| 125 | #define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0) |
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| 126 | #define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0) |
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| 127 | #define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0) |
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| 128 | #define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0) |
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| 129 | #define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0) |
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| 130 | |
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| 131 | #define MPP22_GPIO22 MPP(22, 0x0, 1, 1) |
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| 132 | #define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0) |
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| 133 | #define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0) |
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| 134 | #define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0) |
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| 135 | #define MPP22_SSP_TXD MPP(22, 0x4, 0, 0) |
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| 136 | #define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0) |
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| 137 | #define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0) |
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| 138 | |
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| 139 | #define MPP23_GPIO23 MPP(23, 0x0, 1, 1) |
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| 140 | #define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0) |
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| 141 | #define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0) |
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| 142 | #define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0) |
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| 143 | #define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0) |
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| 144 | #define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0) |
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| 145 | |
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| 146 | #define MPP_MAX 23 |
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| 147 | |
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| 148 | #define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0) |
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| 149 | |
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| 150 | /* for MPP groups _num is a group index */ |
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| 151 | enum dove_mpp_grp_idx { |
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| 152 | MPP_24_39 = 2, |
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| 153 | MPP_40_45 = 0, |
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| 154 | MPP_46_51 = 1, |
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| 155 | MPP_58_61 = 5, |
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| 156 | MPP_62_63 = 4, |
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| 157 | MPP_GRP_MAX = 5, |
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| 158 | }; |
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| 159 | |
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| 160 | #define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1) |
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| 161 | #define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0) |
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| 162 | |
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| 163 | #define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1) |
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| 164 | #define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0) |
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| 165 | |
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| 166 | #define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1) |
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| 167 | #define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0) |
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| 168 | |
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| 169 | #define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1) |
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| 170 | #define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0) |
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| 171 | |
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| 172 | #define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1) |
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| 173 | #define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0) |
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| 174 | |
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| 175 | /* The MPP[64:71] control differs from other groups */ |
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| 176 | #define MPP_GRP_NFC_64_71_GPO 0x1 |
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| 177 | #define MPP_GRP_NFC_64_71_NFC 0x0 |
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| 178 | |
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| 179 | /* |
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| 180 | * The MPP[52:57] functionality is encoded by 4 bits in different |
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| 181 | * registers. The _num field in this case encodes those bits in |
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| 182 | * correspodence with Table 135 of 88AP510 Functional specification |
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| 183 | */ |
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| 184 | #define MPP_GRP_AU1_52_57_AU1 0x0 |
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| 185 | #define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2 |
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| 186 | #define MPP_GRP_AU1_52_57_GPIO 0xa |
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| 187 | #define MPP_GRP_AU1_52_57_TW_GPIO 0xb |
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| 188 | #define MPP_GRP_AU1_52_57_AU1_SSP 0xc |
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| 189 | #define MPP_GRP_AU1_52_57_SSP_GPIO 0xe |
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| 190 | #define MPP_GRP_AU1_52_57_SSP_TW 0xf |
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| 191 | |
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| 192 | void dove_mpp_conf(unsigned int *mpp_list, |
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| 193 | unsigned int *mpp_grp_list, |
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| 194 | unsigned int grp_au1_52_57, |
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| 195 | unsigned int grp_nfc_64_71); |
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| 196 | |
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| 197 | #endif /* __ARCH_DOVE_MPP_CODED_H */ |
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| 198 | |
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