| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2012 Samsung Electronics. |
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| 4 | * |
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| 5 | * Exynos - SMC Call |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __ASM_ARCH_EXYNOS_SMC_H |
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| 9 | #define __ASM_ARCH_EXYNOS_SMC_H |
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| 10 | |
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| 11 | #define SMC_CMD_INIT (-1) |
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| 12 | #define SMC_CMD_INFO (-2) |
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| 13 | /* For Power Management */ |
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| 14 | #define SMC_CMD_SLEEP (-3) |
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| 15 | #define SMC_CMD_CPU1BOOT (-4) |
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| 16 | #define SMC_CMD_CPU0AFTR (-5) |
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| 17 | #define SMC_CMD_SAVE (-6) |
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| 18 | #define SMC_CMD_SHUTDOWN (-7) |
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| 19 | /* For CP15 Access */ |
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| 20 | #define SMC_CMD_C15RESUME (-11) |
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| 21 | /* For L2 Cache Access */ |
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| 22 | #define SMC_CMD_L2X0CTRL (-21) |
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| 23 | #define SMC_CMD_L2X0SETUP1 (-22) |
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| 24 | #define SMC_CMD_L2X0SETUP2 (-23) |
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| 25 | #define SMC_CMD_L2X0INVALL (-24) |
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| 26 | #define SMC_CMD_L2X0DEBUG (-25) |
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| 27 | |
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| 28 | /* For Accessing CP15/SFR (General) */ |
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| 29 | #define SMC_CMD_REG (-101) |
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| 30 | |
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| 31 | /* defines for SMC_CMD_REG */ |
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| 32 | #define SMC_REG_CLASS_SFR_W (0x1 << 30) |
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| 33 | #define SMC_REG_ID_SFR_W(addr) (SMC_REG_CLASS_SFR_W | ((addr) >> 2)) |
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| 34 | |
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| 35 | #ifndef __ASSEMBLY__ |
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| 36 | |
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| 37 | extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3); |
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| 38 | |
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| 39 | #endif /* __ASSEMBLY__ */ |
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| 40 | |
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| 41 | /* op type for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */ |
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| 42 | #define OP_TYPE_CORE 0x0 |
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| 43 | #define OP_TYPE_CLUSTER 0x1 |
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| 44 | |
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| 45 | /* Power State required for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */ |
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| 46 | #define SMC_POWERSTATE_IDLE 0x1 |
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| 47 | |
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| 48 | #endif |
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| 49 | |
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