| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
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| 4 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef __ASM_ARCH_MXC_IIM_H__ |
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| 8 | #define __ASM_ARCH_MXC_IIM_H__ |
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| 9 | |
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| 10 | /* Register offsets */ |
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| 11 | #define MXC_IIMSTAT 0x0000 |
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| 12 | #define MXC_IIMSTATM 0x0004 |
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| 13 | #define MXC_IIMERR 0x0008 |
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| 14 | #define MXC_IIMEMASK 0x000C |
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| 15 | #define MXC_IIMFCTL 0x0010 |
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| 16 | #define MXC_IIMUA 0x0014 |
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| 17 | #define MXC_IIMLA 0x0018 |
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| 18 | #define MXC_IIMSDAT 0x001C |
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| 19 | #define MXC_IIMPREV 0x0020 |
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| 20 | #define MXC_IIMSREV 0x0024 |
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| 21 | #define MXC_IIMPRG_P 0x0028 |
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| 22 | #define MXC_IIMSCS0 0x002C |
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| 23 | #define MXC_IIMSCS1 0x0030 |
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| 24 | #define MXC_IIMSCS2 0x0034 |
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| 25 | #define MXC_IIMSCS3 0x0038 |
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| 26 | #define MXC_IIMFBAC0 0x0800 |
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| 27 | #define MXC_IIMJAC 0x0804 |
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| 28 | #define MXC_IIMHWV1 0x0808 |
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| 29 | #define MXC_IIMHWV2 0x080C |
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| 30 | #define MXC_IIMHAB0 0x0810 |
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| 31 | #define MXC_IIMHAB1 0x0814 |
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| 32 | /* Definitions for i.MX27 TO2 */ |
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| 33 | #define MXC_IIMMAC 0x0814 |
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| 34 | #define MXC_IIMPREV_FUSE 0x0818 |
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| 35 | #define MXC_IIMSREV_FUSE 0x081C |
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| 36 | #define MXC_IIMSJC_CHALL_0 0x0820 |
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| 37 | #define MXC_IIMSJC_CHALL_7 0x083C |
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| 38 | #define MXC_IIMFB0UC17 0x0840 |
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| 39 | #define MXC_IIMFB0UC255 0x0BFC |
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| 40 | #define MXC_IIMFBAC1 0x0C00 |
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| 41 | /* Definitions for i.MX27 TO2 */ |
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| 42 | #define MXC_IIMSUID 0x0C04 |
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| 43 | #define MXC_IIMKEY0 0x0C04 |
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| 44 | #define MXC_IIMKEY20 0x0C54 |
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| 45 | #define MXC_IIMSJC_RESP_0 0x0C58 |
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| 46 | #define MXC_IIMSJC_RESP_7 0x0C74 |
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| 47 | #define MXC_IIMFB1UC30 0x0C78 |
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| 48 | #define MXC_IIMFB1UC255 0x0FFC |
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| 49 | |
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| 50 | /* Bit definitions */ |
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| 51 | |
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| 52 | #define MXC_IIMHWV1_WLOCK (0x1 << 7) |
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| 53 | #define MXC_IIMHWV1_MCU_ENDIAN (0x1 << 6) |
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| 54 | #define MXC_IIMHWV1_DSP_ENDIAN (0x1 << 5) |
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| 55 | #define MXC_IIMHWV1_BOOT_INT (0x1 << 4) |
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| 56 | #define MXC_IIMHWV1_SCC_DISABLE (0x1 << 3) |
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| 57 | #define MXC_IIMHWV1_HANTRO_DISABLE (0x1 << 2) |
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| 58 | #define MXC_IIMHWV1_MEMSTICK_DIS (0x1 << 1) |
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| 59 | |
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| 60 | #define MXC_IIMHWV2_WLOCK (0x1 << 7) |
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| 61 | #define MXC_IIMHWV2_BP_SDMA (0x1 << 6) |
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| 62 | #define MXC_IIMHWV2_SCM_DCM (0x1 << 5) |
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| 63 | |
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| 64 | #endif /* __ASM_ARCH_MXC_IIM_H__ */ |
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| 65 | |
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