| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. |
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| 4 | */ |
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| 5 | |
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| 6 | |
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| 7 | #ifndef __MACH_MX3x_H__ |
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| 8 | #define __MACH_MX3x_H__ |
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| 9 | |
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| 10 | /* |
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| 11 | * MX31 memory map: |
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| 12 | * |
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| 13 | * Virt Phys Size What |
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| 14 | * --------------------------------------------------------------------------- |
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| 15 | * FC000000 43F00000 1M AIPS 1 |
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| 16 | * FC100000 50000000 1M SPBA |
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| 17 | * FC200000 53F00000 1M AIPS 2 |
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| 18 | * FC500000 60000000 128M ROMPATCH |
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| 19 | * FC400000 68000000 128M AVIC |
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| 20 | * 70000000 256M IPU (MAX M2) |
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| 21 | * 80000000 256M CSD0 SDRAM/DDR |
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| 22 | * 90000000 256M CSD1 SDRAM/DDR |
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| 23 | * A0000000 128M CS0 Flash |
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| 24 | * A8000000 128M CS1 Flash |
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| 25 | * B0000000 32M CS2 |
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| 26 | * B2000000 32M CS3 |
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| 27 | * F4000000 B4000000 32M CS4 |
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| 28 | * B6000000 32M CS5 |
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| 29 | * FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers |
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| 30 | * C0000000 64M PCMCIA/CF |
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| 31 | */ |
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| 32 | |
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| 33 | /* |
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| 34 | * L2CC |
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| 35 | */ |
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| 36 | #define MX3x_L2CC_BASE_ADDR 0x30000000 |
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| 37 | #define MX3x_L2CC_SIZE SZ_1M |
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| 38 | |
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| 39 | /* |
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| 40 | * AIPS 1 |
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| 41 | */ |
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| 42 | #define MX3x_AIPS1_BASE_ADDR 0x43f00000 |
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| 43 | #define MX3x_AIPS1_SIZE SZ_1M |
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| 44 | #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) |
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| 45 | #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) |
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| 46 | #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000) |
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| 47 | #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000) |
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| 48 | #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000) |
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| 49 | #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000) |
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| 50 | #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000) |
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| 51 | #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000) |
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| 52 | #define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000) |
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| 53 | #define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000) |
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| 54 | #define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000) |
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| 55 | #define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000) |
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| 56 | #define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000) |
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| 57 | #define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000) |
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| 58 | #define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000) |
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| 59 | #define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000) |
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| 60 | #define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000) |
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| 61 | #define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000) |
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| 62 | |
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| 63 | /* |
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| 64 | * SPBA global module enabled #0 |
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| 65 | */ |
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| 66 | #define MX3x_SPBA0_BASE_ADDR 0x50000000 |
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| 67 | #define MX3x_SPBA0_SIZE SZ_1M |
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| 68 | #define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) |
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| 69 | #define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) |
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| 70 | #define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000) |
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| 71 | #define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000) |
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| 72 | #define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000) |
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| 73 | #define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000) |
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| 74 | |
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| 75 | /* |
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| 76 | * AIPS 2 |
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| 77 | */ |
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| 78 | #define MX3x_AIPS2_BASE_ADDR 0x53f00000 |
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| 79 | #define MX3x_AIPS2_SIZE SZ_1M |
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| 80 | #define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) |
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| 81 | #define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) |
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| 82 | #define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000) |
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| 83 | #define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000) |
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| 84 | #define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000) |
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| 85 | #define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000) |
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| 86 | #define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000) |
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| 87 | #define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000) |
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| 88 | #define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000) |
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| 89 | #define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000) |
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| 90 | #define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000) |
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| 91 | #define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000) |
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| 92 | #define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000) |
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| 93 | #define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000) |
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| 94 | #define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000) |
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| 95 | #define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000) |
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| 96 | |
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| 97 | /* |
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| 98 | * ROMP and AVIC |
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| 99 | */ |
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| 100 | #define MX3x_ROMP_BASE_ADDR 0x60000000 |
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| 101 | #define MX3x_ROMP_SIZE SZ_1M |
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| 102 | |
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| 103 | #define MX3x_AVIC_BASE_ADDR 0x68000000 |
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| 104 | #define MX3x_AVIC_SIZE SZ_1M |
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| 105 | |
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| 106 | /* |
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| 107 | * Memory regions and CS |
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| 108 | */ |
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| 109 | #define MX3x_IPU_MEM_BASE_ADDR 0x70000000 |
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| 110 | #define MX3x_CSD0_BASE_ADDR 0x80000000 |
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| 111 | #define MX3x_CSD1_BASE_ADDR 0x90000000 |
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| 112 | |
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| 113 | #define MX3x_CS0_BASE_ADDR 0xa0000000 |
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| 114 | #define MX3x_CS1_BASE_ADDR 0xa8000000 |
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| 115 | #define MX3x_CS2_BASE_ADDR 0xb0000000 |
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| 116 | #define MX3x_CS3_BASE_ADDR 0xb2000000 |
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| 117 | |
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| 118 | #define MX3x_CS4_BASE_ADDR 0xb4000000 |
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| 119 | #define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000 |
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| 120 | #define MX3x_CS4_SIZE SZ_32M |
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| 121 | |
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| 122 | #define MX3x_CS5_BASE_ADDR 0xb6000000 |
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| 123 | #define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000 |
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| 124 | #define MX3x_CS5_SIZE SZ_32M |
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| 125 | |
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| 126 | /* |
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| 127 | * NAND, SDRAM, WEIM, M3IF, EMI controllers |
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| 128 | */ |
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| 129 | #define MX3x_X_MEMC_BASE_ADDR 0xb8000000 |
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| 130 | #define MX3x_X_MEMC_SIZE SZ_64K |
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| 131 | #define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) |
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| 132 | #define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) |
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| 133 | #define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000) |
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| 134 | #define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000) |
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| 135 | #define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR |
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| 136 | |
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| 137 | #define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 |
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| 138 | |
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| 139 | /* |
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| 140 | * Interrupt numbers |
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| 141 | */ |
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| 142 | #include <asm/irq.h> |
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| 143 | #define MX3x_INT_I2C3 (NR_IRQS_LEGACY + 3) |
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| 144 | #define MX3x_INT_I2C2 (NR_IRQS_LEGACY + 4) |
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| 145 | #define MX3x_INT_RTIC (NR_IRQS_LEGACY + 6) |
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| 146 | #define MX3x_INT_I2C (NR_IRQS_LEGACY + 10) |
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| 147 | #define MX3x_INT_CSPI2 (NR_IRQS_LEGACY + 13) |
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| 148 | #define MX3x_INT_CSPI1 (NR_IRQS_LEGACY + 14) |
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| 149 | #define MX3x_INT_ATA (NR_IRQS_LEGACY + 15) |
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| 150 | #define MX3x_INT_UART3 (NR_IRQS_LEGACY + 18) |
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| 151 | #define MX3x_INT_IIM (NR_IRQS_LEGACY + 19) |
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| 152 | #define MX3x_INT_RNGA (NR_IRQS_LEGACY + 22) |
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| 153 | #define MX3x_INT_EVTMON (NR_IRQS_LEGACY + 23) |
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| 154 | #define MX3x_INT_KPP (NR_IRQS_LEGACY + 24) |
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| 155 | #define MX3x_INT_RTC (NR_IRQS_LEGACY + 25) |
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| 156 | #define MX3x_INT_PWM (NR_IRQS_LEGACY + 26) |
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| 157 | #define MX3x_INT_EPIT2 (NR_IRQS_LEGACY + 27) |
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| 158 | #define MX3x_INT_EPIT1 (NR_IRQS_LEGACY + 28) |
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| 159 | #define MX3x_INT_GPT (NR_IRQS_LEGACY + 29) |
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| 160 | #define MX3x_INT_POWER_FAIL (NR_IRQS_LEGACY + 30) |
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| 161 | #define MX3x_INT_UART2 (NR_IRQS_LEGACY + 32) |
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| 162 | #define MX3x_INT_NANDFC (NR_IRQS_LEGACY + 33) |
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| 163 | #define MX3x_INT_SDMA (NR_IRQS_LEGACY + 34) |
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| 164 | #define MX3x_INT_MSHC1 (NR_IRQS_LEGACY + 39) |
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| 165 | #define MX3x_INT_IPU_ERR (NR_IRQS_LEGACY + 41) |
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| 166 | #define MX3x_INT_IPU_SYN (NR_IRQS_LEGACY + 42) |
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| 167 | #define MX3x_INT_UART1 (NR_IRQS_LEGACY + 45) |
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| 168 | #define MX3x_INT_ECT (NR_IRQS_LEGACY + 48) |
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| 169 | #define MX3x_INT_SCC_SCM (NR_IRQS_LEGACY + 49) |
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| 170 | #define MX3x_INT_SCC_SMN (NR_IRQS_LEGACY + 50) |
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| 171 | #define MX3x_INT_GPIO2 (NR_IRQS_LEGACY + 51) |
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| 172 | #define MX3x_INT_GPIO1 (NR_IRQS_LEGACY + 52) |
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| 173 | #define MX3x_INT_WDOG (NR_IRQS_LEGACY + 55) |
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| 174 | #define MX3x_INT_GPIO3 (NR_IRQS_LEGACY + 56) |
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| 175 | #define MX3x_INT_EXT_POWER (NR_IRQS_LEGACY + 58) |
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| 176 | #define MX3x_INT_EXT_TEMPER (NR_IRQS_LEGACY + 59) |
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| 177 | #define MX3x_INT_EXT_SENSOR60 (NR_IRQS_LEGACY + 60) |
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| 178 | #define MX3x_INT_EXT_SENSOR61 (NR_IRQS_LEGACY + 61) |
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| 179 | #define MX3x_INT_EXT_WDOG (NR_IRQS_LEGACY + 62) |
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| 180 | #define MX3x_INT_EXT_TV (NR_IRQS_LEGACY + 63) |
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| 181 | |
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| 182 | #define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ |
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| 183 | |
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| 184 | #endif /* ifndef __MACH_MX3x_H__ */ |
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| 185 | |
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