1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * arch/arm/mach-lpc32xx/include/mach/platform.h |
4 | * |
5 | * Author: Kevin Wells <kevin.wells@nxp.com> |
6 | * |
7 | * Copyright (C) 2010 NXP Semiconductors |
8 | */ |
9 | |
10 | #ifndef __ARM_LPC32XX_H |
11 | #define __ARM_LPC32XX_H |
12 | |
13 | #define _SBF(f, v) ((v) << (f)) |
14 | #define _BIT(n) _SBF(n, 1) |
15 | |
16 | /* |
17 | * AHB 0 physical base addresses |
18 | */ |
19 | #define LPC32XX_SLC_BASE 0x20020000 |
20 | #define LPC32XX_SSP0_BASE 0x20084000 |
21 | #define LPC32XX_SPI1_BASE 0x20088000 |
22 | #define LPC32XX_SSP1_BASE 0x2008C000 |
23 | #define LPC32XX_SPI2_BASE 0x20090000 |
24 | #define LPC32XX_I2S0_BASE 0x20094000 |
25 | #define LPC32XX_SD_BASE 0x20098000 |
26 | #define LPC32XX_I2S1_BASE 0x2009C000 |
27 | #define LPC32XX_MLC_BASE 0x200A8000 |
28 | #define LPC32XX_AHB0_START LPC32XX_SLC_BASE |
29 | #define LPC32XX_AHB0_SIZE 0x00089000 |
30 | |
31 | /* |
32 | * AHB 1 physical base addresses |
33 | */ |
34 | #define LPC32XX_DMA_BASE 0x31000000 |
35 | #define LPC32XX_USB_BASE 0x31020000 |
36 | #define LPC32XX_USBH_BASE 0x31020000 |
37 | #define LPC32XX_USB_OTG_BASE 0x31020000 |
38 | #define LPC32XX_OTG_I2C_BASE 0x31020300 |
39 | #define LPC32XX_LCD_BASE 0x31040000 |
40 | #define LPC32XX_ETHERNET_BASE 0x31060000 |
41 | #define LPC32XX_EMC_BASE 0x31080000 |
42 | #define LPC32XX_ETB_CFG_BASE 0x310C0000 |
43 | #define LPC32XX_ETB_DATA_BASE 0x310E0000 |
44 | #define LPC32XX_AHB1_START LPC32XX_DMA_BASE |
45 | #define LPC32XX_AHB1_SIZE 0x000E1000 |
46 | |
47 | /* |
48 | * FAB physical base addresses |
49 | */ |
50 | #define LPC32XX_CLK_PM_BASE 0x40004000 |
51 | #define LPC32XX_MIC_BASE 0x40008000 |
52 | #define LPC32XX_SIC1_BASE 0x4000C000 |
53 | #define LPC32XX_SIC2_BASE 0x40010000 |
54 | #define LPC32XX_HS_UART1_BASE 0x40014000 |
55 | #define LPC32XX_HS_UART2_BASE 0x40018000 |
56 | #define LPC32XX_HS_UART7_BASE 0x4001C000 |
57 | #define LPC32XX_RTC_BASE 0x40024000 |
58 | #define LPC32XX_RTC_RAM_BASE 0x40024080 |
59 | #define LPC32XX_GPIO_BASE 0x40028000 |
60 | #define LPC32XX_PWM3_BASE 0x4002C000 |
61 | #define LPC32XX_PWM4_BASE 0x40030000 |
62 | #define LPC32XX_MSTIM_BASE 0x40034000 |
63 | #define LPC32XX_HSTIM_BASE 0x40038000 |
64 | #define LPC32XX_WDTIM_BASE 0x4003C000 |
65 | #define LPC32XX_DEBUG_CTRL_BASE 0x40040000 |
66 | #define LPC32XX_TIMER0_BASE 0x40044000 |
67 | #define LPC32XX_ADC_BASE 0x40048000 |
68 | #define LPC32XX_TIMER1_BASE 0x4004C000 |
69 | #define LPC32XX_KSCAN_BASE 0x40050000 |
70 | #define LPC32XX_UART_CTRL_BASE 0x40054000 |
71 | #define LPC32XX_TIMER2_BASE 0x40058000 |
72 | #define LPC32XX_PWM1_BASE 0x4005C000 |
73 | #define LPC32XX_PWM2_BASE 0x4005C004 |
74 | #define LPC32XX_TIMER3_BASE 0x40060000 |
75 | |
76 | /* |
77 | * APB physical base addresses |
78 | */ |
79 | #define LPC32XX_UART3_BASE 0x40080000 |
80 | #define LPC32XX_UART4_BASE 0x40088000 |
81 | #define LPC32XX_UART5_BASE 0x40090000 |
82 | #define LPC32XX_UART6_BASE 0x40098000 |
83 | #define LPC32XX_I2C1_BASE 0x400A0000 |
84 | #define LPC32XX_I2C2_BASE 0x400A8000 |
85 | |
86 | /* |
87 | * FAB and APB base and sizing |
88 | */ |
89 | #define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE |
90 | #define LPC32XX_FABAPB_SIZE 0x000A5000 |
91 | |
92 | /* |
93 | * Internal memory bases and sizes |
94 | */ |
95 | #define LPC32XX_IRAM_BASE 0x08000000 |
96 | #define LPC32XX_IROM_BASE 0x0C000000 |
97 | |
98 | /* |
99 | * External Static Memory Bank Address Space Bases |
100 | */ |
101 | #define LPC32XX_EMC_CS0_BASE 0xE0000000 |
102 | #define LPC32XX_EMC_CS1_BASE 0xE1000000 |
103 | #define LPC32XX_EMC_CS2_BASE 0xE2000000 |
104 | #define LPC32XX_EMC_CS3_BASE 0xE3000000 |
105 | |
106 | /* |
107 | * External SDRAM Memory Bank Address Space Bases |
108 | */ |
109 | #define LPC32XX_EMC_DYCS0_BASE 0x80000000 |
110 | #define LPC32XX_EMC_DYCS1_BASE 0xA0000000 |
111 | |
112 | /* |
113 | * Clock and crystal information |
114 | */ |
115 | #define LPC32XX_MAIN_OSC_FREQ 13000000 |
116 | #define LPC32XX_CLOCK_OSC_FREQ 32768 |
117 | |
118 | /* |
119 | * Clock and Power control register offsets |
120 | */ |
121 | #define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\ |
122 | (x)) |
123 | #define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000) |
124 | #define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014) |
125 | #define LPC32XX_CLKPWR_P01_ER _PMREG(0x018) |
126 | #define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C) |
127 | #define LPC32XX_CLKPWR_INT_ER _PMREG(0x020) |
128 | #define LPC32XX_CLKPWR_INT_RS _PMREG(0x024) |
129 | #define LPC32XX_CLKPWR_INT_SR _PMREG(0x028) |
130 | #define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C) |
131 | #define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030) |
132 | #define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034) |
133 | #define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038) |
134 | #define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C) |
135 | #define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040) |
136 | #define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044) |
137 | #define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048) |
138 | #define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C) |
139 | #define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050) |
140 | #define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054) |
141 | #define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058) |
142 | #define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060) |
143 | #define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064) |
144 | #define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068) |
145 | #define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C) |
146 | #define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070) |
147 | #define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074) |
148 | #define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078) |
149 | #define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C) |
150 | #define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080) |
151 | #define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090) |
152 | #define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4) |
153 | #define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8) |
154 | #define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC) |
155 | #define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0) |
156 | #define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4) |
157 | #define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8) |
158 | #define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC) |
159 | #define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0) |
160 | #define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4) |
161 | #define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8) |
162 | #define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0) |
163 | #define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4) |
164 | #define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8) |
165 | #define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC) |
166 | #define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0) |
167 | #define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4) |
168 | #define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8) |
169 | #define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC) |
170 | #define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x)) |
171 | |
172 | /* |
173 | * clkpwr_debug_ctrl register definitions |
174 | */ |
175 | #define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4) |
176 | |
177 | /* |
178 | * clkpwr_bootmap register definitions |
179 | */ |
180 | #define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1) |
181 | |
182 | /* |
183 | * clkpwr_start_gpio register bit definitions |
184 | */ |
185 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31) |
186 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30) |
187 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29) |
188 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28) |
189 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27) |
190 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26) |
191 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25) |
192 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24) |
193 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23) |
194 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22) |
195 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21) |
196 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20) |
197 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19) |
198 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18) |
199 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17) |
200 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16) |
201 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15) |
202 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14) |
203 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13) |
204 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12) |
205 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11) |
206 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10) |
207 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9) |
208 | #define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8) |
209 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7) |
210 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6) |
211 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5) |
212 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4) |
213 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3) |
214 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2) |
215 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1) |
216 | #define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0) |
217 | |
218 | /* |
219 | * clkpwr_usbclk_pdiv register definitions |
220 | */ |
221 | #define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF |
222 | |
223 | /* |
224 | * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int, |
225 | * clkpwr_start_pol_int, register bit definitions |
226 | */ |
227 | #define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31) |
228 | #define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30) |
229 | #define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29) |
230 | #define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26) |
231 | #define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25) |
232 | #define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24) |
233 | #define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23) |
234 | #define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22) |
235 | #define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21) |
236 | #define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20) |
237 | #define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19) |
238 | #define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16) |
239 | #define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7) |
240 | #define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6) |
241 | #define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5) |
242 | #define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4) |
243 | #define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3) |
244 | #define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2) |
245 | #define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1) |
246 | #define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0) |
247 | |
248 | /* |
249 | * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin, |
250 | * clkpwr_start_pol_pin register bit definitions |
251 | */ |
252 | #define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31) |
253 | #define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30) |
254 | #define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28) |
255 | #define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26) |
256 | #define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25) |
257 | #define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24) |
258 | #define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23) |
259 | #define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22) |
260 | #define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21) |
261 | #define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18) |
262 | #define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17) |
263 | #define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16) |
264 | #define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15) |
265 | #define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14) |
266 | #define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13) |
267 | #define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12) |
268 | #define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11) |
269 | #define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT _BIT(10) |
270 | #define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9) |
271 | #define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8) |
272 | #define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT _BIT(7) |
273 | #define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6) |
274 | #define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT _BIT(5) |
275 | #define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT _BIT(4) |
276 | #define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT _BIT(3) |
277 | |
278 | /* |
279 | * clkpwr_hclk_div register definitions |
280 | */ |
281 | #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7) |
282 | #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7) |
283 | #define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7) |
284 | #define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2) |
285 | #define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3) |
286 | |
287 | /* |
288 | * clkpwr_pwr_ctrl register definitions |
289 | */ |
290 | #define LPC32XX_CLKPWR_CTRL_FORCE_PCLK _BIT(10) |
291 | #define LPC32XX_CLKPWR_SDRAM_SELF_RFSH _BIT(9) |
292 | #define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH _BIT(8) |
293 | #define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7) |
294 | #define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT _BIT(5) |
295 | #define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT _BIT(4) |
296 | #define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN _BIT(3) |
297 | #define LPC32XX_CLKPWR_SELECT_RUN_MODE _BIT(2) |
298 | #define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN _BIT(1) |
299 | #define LPC32XX_CLKPWR_STOP_MODE_CTRL _BIT(0) |
300 | |
301 | /* |
302 | * clkpwr_pll397_ctrl register definitions |
303 | */ |
304 | #define LPC32XX_CLKPWR_PLL397_MSLOCK_STS _BIT(10) |
305 | #define LPC32XX_CLKPWR_PLL397_BYPASS _BIT(9) |
306 | #define LPC32XX_CLKPWR_PLL397_BIAS_NORM 0x000 |
307 | #define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 0x040 |
308 | #define LPC32XX_CLKPWR_PLL397_BIAS_N25 0x080 |
309 | #define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 0x0C0 |
310 | #define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 0x100 |
311 | #define LPC32XX_CLKPWR_PLL397_BIAS_P25 0x140 |
312 | #define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 0x180 |
313 | #define LPC32XX_CLKPWR_PLL397_BIAS_P50 0x1C0 |
314 | #define LPC32XX_CLKPWR_PLL397_BIAS_MASK 0x1C0 |
315 | #define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS _BIT(1) |
316 | #define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS _BIT(0) |
317 | |
318 | /* |
319 | * clkpwr_main_osc_ctrl register definitions |
320 | */ |
321 | #define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2) |
322 | #define LPC32XX_CLKPWR_MOSC_CAP_MASK (0x7F << 2) |
323 | #define LPC32XX_CLKPWR_TEST_MODE _BIT(1) |
324 | #define LPC32XX_CLKPWR_MOSC_DISABLE _BIT(0) |
325 | |
326 | /* |
327 | * clkpwr_sysclk_ctrl register definitions |
328 | */ |
329 | #define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2) |
330 | #define LPC32XX_CLKPWR_SYSCTRL_BP_MASK (0x3FF << 2) |
331 | #define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 _BIT(1) |
332 | #define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX _BIT(0) |
333 | |
334 | /* |
335 | * clkpwr_lcdclk_ctrl register definitions |
336 | */ |
337 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000 |
338 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040 |
339 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080 |
340 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0 |
341 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100 |
342 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140 |
343 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180 |
344 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0 |
345 | #define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0 |
346 | #define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 0x020 |
347 | #define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F) |
348 | #define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 0x001F |
349 | |
350 | /* |
351 | * clkpwr_hclkpll_ctrl register definitions |
352 | */ |
353 | #define LPC32XX_CLKPWR_HCLKPLL_POWER_UP _BIT(16) |
354 | #define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS _BIT(15) |
355 | #define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14) |
356 | #define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13) |
357 | #define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11) |
358 | #define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) |
359 | #define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1) |
360 | #define LPC32XX_CLKPWR_HCLKPLL_PLL_STS _BIT(0) |
361 | |
362 | /* |
363 | * clkpwr_adc_clk_ctrl_1 register definitions |
364 | */ |
365 | #define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0) |
366 | #define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL _BIT(8) |
367 | |
368 | /* |
369 | * clkpwr_usb_ctrl register definitions |
370 | */ |
371 | #define LPC32XX_CLKPWR_USBCTRL_HCLK_EN _BIT(24) |
372 | #define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN _BIT(23) |
373 | #define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN _BIT(22) |
374 | #define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN _BIT(21) |
375 | #define LPC32XX_CLKPWR_USBCTRL_PU_ADD (0x0 << 19) |
376 | #define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER (0x1 << 19) |
377 | #define LPC32XX_CLKPWR_USBCTRL_PD_ADD (0x3 << 19) |
378 | #define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 _BIT(18) |
379 | #define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 _BIT(17) |
380 | #define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP _BIT(16) |
381 | #define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS _BIT(15) |
382 | #define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14) |
383 | #define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13) |
384 | #define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11) |
385 | #define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9) |
386 | #define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1) |
387 | #define LPC32XX_CLKPWR_USBCTRL_PLL_STS _BIT(0) |
388 | |
389 | /* |
390 | * clkpwr_sdramclk_ctrl register definitions |
391 | */ |
392 | #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22) |
393 | #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW _BIT(21) |
394 | #define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20) |
395 | #define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19) |
396 | #define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) (((n) & 0x1F) << 14) |
397 | #define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13) |
398 | #define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x7) << 10) |
399 | #define LPC32XX_CLKPWR_SDRCLK_USE_CAL _BIT(9) |
400 | #define LPC32XX_CLKPWR_SDRCLK_DO_CAL _BIT(8) |
401 | #define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC _BIT(7) |
402 | #define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) (((n) & 0x1F) << 2) |
403 | #define LPC32XX_CLKPWR_SDRCLK_USE_DDR _BIT(1) |
404 | #define LPC32XX_CLKPWR_SDRCLK_CLK_DIS _BIT(0) |
405 | |
406 | /* |
407 | * clkpwr_ssp_blk_ctrl register definitions |
408 | */ |
409 | #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX _BIT(5) |
410 | #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX _BIT(4) |
411 | #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX _BIT(3) |
412 | #define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX _BIT(2) |
413 | #define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN _BIT(1) |
414 | #define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN _BIT(0) |
415 | |
416 | /* |
417 | * clkpwr_i2s_clk_ctrl register definitions |
418 | */ |
419 | #define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6) |
420 | #define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5) |
421 | #define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4) |
422 | #define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3) |
423 | #define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2) |
424 | #define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN _BIT(1) |
425 | #define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN _BIT(0) |
426 | |
427 | /* |
428 | * clkpwr_ms_ctrl register definitions |
429 | */ |
430 | #define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS _BIT(10) |
431 | #define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN _BIT(9) |
432 | #define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS _BIT(8) |
433 | #define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS _BIT(7) |
434 | #define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS _BIT(6) |
435 | #define LPC32XX_CLKPWR_MSCARD_SDCARD_EN _BIT(5) |
436 | #define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF) |
437 | |
438 | /* |
439 | * clkpwr_macclk_ctrl register definitions |
440 | */ |
441 | #define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 0x00 |
442 | #define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 0x08 |
443 | #define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 0x18 |
444 | #define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 0x18 |
445 | #define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN _BIT(2) |
446 | #define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN _BIT(1) |
447 | #define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN _BIT(0) |
448 | |
449 | /* |
450 | * clkpwr_test_clk_sel register definitions |
451 | */ |
452 | #define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5) |
453 | #define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC (0x1 << 5) |
454 | #define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC (0x2 << 5) |
455 | #define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK (0x3 << 5) |
456 | #define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4) |
457 | #define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK (0x0 << 1) |
458 | #define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1) |
459 | #define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1) |
460 | #define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC (0x5 << 1) |
461 | #define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1) |
462 | #define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK (0x7 << 1) |
463 | #define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0) |
464 | |
465 | /* |
466 | * clkpwr_sw_int register definitions |
467 | */ |
468 | #define LPC32XX_CLKPWR_SW_INT(n) (_BIT(0) | (((n) & 0x7F) << 1)) |
469 | #define LPC32XX_CLKPWR_SW_GET_ARG(n) (((n) & 0xFE) >> 1) |
470 | |
471 | /* |
472 | * clkpwr_i2c_clk_ctrl register definitions |
473 | */ |
474 | #define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4) |
475 | #define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3) |
476 | #define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2) |
477 | #define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN _BIT(1) |
478 | #define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN _BIT(0) |
479 | |
480 | /* |
481 | * clkpwr_key_clk_ctrl register definitions |
482 | */ |
483 | #define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 0x1 |
484 | |
485 | /* |
486 | * clkpwr_adc_clk_ctrl register definitions |
487 | */ |
488 | #define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 0x1 |
489 | |
490 | /* |
491 | * clkpwr_pwm_clk_ctrl register definitions |
492 | */ |
493 | #define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) (((n) & 0xF) << 8) |
494 | #define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) (((n) & 0xF) << 4) |
495 | #define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8 |
496 | #define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 0x4 |
497 | #define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2 |
498 | #define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 0x1 |
499 | |
500 | /* |
501 | * clkpwr_timer_clk_ctrl register definitions |
502 | */ |
503 | #define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 0x2 |
504 | #define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 0x1 |
505 | |
506 | /* |
507 | * clkpwr_timers_pwms_clk_ctrl_1 register definitions |
508 | */ |
509 | #define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 0x40 |
510 | #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20 |
511 | #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10 |
512 | #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08 |
513 | #define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 0x04 |
514 | #define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 0x02 |
515 | #define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 0x01 |
516 | |
517 | /* |
518 | * clkpwr_spi_clk_ctrl register definitions |
519 | */ |
520 | #define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 0x80 |
521 | #define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 0x40 |
522 | #define LPC32XX_CLKPWR_SPICLK_USE_SPI2 0x20 |
523 | #define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 0x10 |
524 | #define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 0x08 |
525 | #define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 0x04 |
526 | #define LPC32XX_CLKPWR_SPICLK_USE_SPI1 0x02 |
527 | #define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 0x01 |
528 | |
529 | /* |
530 | * clkpwr_nand_clk_ctrl register definitions |
531 | */ |
532 | #define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 0x20 |
533 | #define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 0x10 |
534 | #define LPC32XX_CLKPWR_NANDCLK_DMA_INT 0x08 |
535 | #define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 0x04 |
536 | #define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 0x02 |
537 | #define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 0x01 |
538 | |
539 | /* |
540 | * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl |
541 | * and clkpwr_uart6_clk_ctrl register definitions |
542 | */ |
543 | #define LPC32XX_CLKPWR_UART_Y_DIV(y) ((y) & 0xFF) |
544 | #define LPC32XX_CLKPWR_UART_X_DIV(x) (((x) & 0xFF) << 8) |
545 | #define LPC32XX_CLKPWR_UART_USE_HCLK _BIT(16) |
546 | |
547 | /* |
548 | * clkpwr_irda_clk_ctrl register definitions |
549 | */ |
550 | #define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF) |
551 | #define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8) |
552 | |
553 | /* |
554 | * clkpwr_uart_clk_ctrl register definitions |
555 | */ |
556 | #define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3) |
557 | #define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2) |
558 | #define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1) |
559 | #define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0) |
560 | |
561 | /* |
562 | * clkpwr_dmaclk_ctrl register definitions |
563 | */ |
564 | #define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1 |
565 | |
566 | /* |
567 | * clkpwr_autoclock register definitions |
568 | */ |
569 | #define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40 |
570 | #define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02 |
571 | #define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01 |
572 | |
573 | /* |
574 | * Interrupt controller register offsets |
575 | */ |
576 | #define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00) |
577 | #define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04) |
578 | #define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08) |
579 | #define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C) |
580 | #define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10) |
581 | #define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14) |
582 | |
583 | /* |
584 | * Timer/counter register offsets |
585 | */ |
586 | #define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00) |
587 | #define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04) |
588 | #define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08) |
589 | #define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C) |
590 | #define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10) |
591 | #define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14) |
592 | #define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18) |
593 | #define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C) |
594 | #define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20) |
595 | #define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24) |
596 | #define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28) |
597 | #define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C) |
598 | #define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30) |
599 | #define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34) |
600 | #define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38) |
601 | #define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C) |
602 | #define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70) |
603 | |
604 | /* |
605 | * ir register definitions |
606 | */ |
607 | #define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3)) |
608 | #define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3))) |
609 | |
610 | /* |
611 | * tcr register definitions |
612 | */ |
613 | #define LPC32XX_TIMER_CNTR_TCR_EN 0x1 |
614 | #define LPC32XX_TIMER_CNTR_TCR_RESET 0x2 |
615 | |
616 | /* |
617 | * mcr register definitions |
618 | */ |
619 | #define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3)) |
620 | #define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1)) |
621 | #define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2)) |
622 | |
623 | /* |
624 | * Standard UART register offsets |
625 | */ |
626 | #define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00) |
627 | #define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04) |
628 | #define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08) |
629 | #define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C) |
630 | #define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10) |
631 | #define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14) |
632 | #define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18) |
633 | #define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C) |
634 | |
635 | /* |
636 | * UART control structure offsets |
637 | */ |
638 | #define _UCREG(x) io_p2v(\ |
639 | LPC32XX_UART_CTRL_BASE + (x)) |
640 | #define LPC32XX_UARTCTL_CTRL _UCREG(0x00) |
641 | #define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04) |
642 | #define LPC32XX_UARTCTL_CLOOP _UCREG(0x08) |
643 | |
644 | /* |
645 | * ctrl register definitions |
646 | */ |
647 | #define LPC32XX_UART_U3_MD_CTRL_EN _BIT(11) |
648 | #define LPC32XX_UART_IRRX6_INV_EN _BIT(10) |
649 | #define LPC32XX_UART_HDPX_EN _BIT(9) |
650 | #define LPC32XX_UART_UART6_IRDAMOD_BYPASS _BIT(5) |
651 | #define LPC32XX_RT_IRTX6_INV_EN _BIT(4) |
652 | #define LPC32XX_RT_IRTX6_INV_MIR_EN _BIT(3) |
653 | #define LPC32XX_RT_RX_IRPULSE_3_16_115K _BIT(2) |
654 | #define LPC32XX_RT_TX_IRPULSE_3_16_115K _BIT(1) |
655 | #define LPC32XX_UART_U5_ROUTE_TO_USB _BIT(0) |
656 | |
657 | /* |
658 | * clkmode register definitions |
659 | */ |
660 | #define LPC32XX_UART_ENABLED_CLOCKS(n) (((n) >> 16) & 0x7F) |
661 | #define LPC32XX_UART_ENABLED_CLOCK(n, u) (((n) >> (16 + (u))) & 0x1) |
662 | #define LPC32XX_UART_ENABLED_CLKS_ANY _BIT(14) |
663 | #define LPC32XX_UART_CLKMODE_OFF 0x0 |
664 | #define LPC32XX_UART_CLKMODE_ON 0x1 |
665 | #define LPC32XX_UART_CLKMODE_AUTO 0x2 |
666 | #define LPC32XX_UART_CLKMODE_MASK(u) (0x3 << ((((u) - 3) * 2) + 4)) |
667 | #define LPC32XX_UART_CLKMODE_LOAD(m, u) ((m) << ((((u) - 3) * 2) + 4)) |
668 | |
669 | /* |
670 | * GPIO Module Register offsets |
671 | */ |
672 | #define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x)) |
673 | #define LPC32XX_GPIO_P_MUX_SET _GPREG(0x100) |
674 | #define LPC32XX_GPIO_P_MUX_CLR _GPREG(0x104) |
675 | #define LPC32XX_GPIO_P_MUX_STATE _GPREG(0x108) |
676 | #define LPC32XX_GPIO_P3_MUX_SET _GPREG(0x110) |
677 | #define LPC32XX_GPIO_P3_MUX_CLR _GPREG(0x114) |
678 | #define LPC32XX_GPIO_P3_MUX_STATE _GPREG(0x118) |
679 | #define LPC32XX_GPIO_P0_MUX_SET _GPREG(0x120) |
680 | #define LPC32XX_GPIO_P0_MUX_CLR _GPREG(0x124) |
681 | #define LPC32XX_GPIO_P0_MUX_STATE _GPREG(0x128) |
682 | #define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130) |
683 | #define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134) |
684 | #define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138) |
685 | #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) |
686 | #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) |
687 | #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) |
688 | |
689 | /* |
690 | * USB Otg Registers |
691 | */ |
692 | #define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x)) |
693 | #define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4) |
694 | #define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8) |
695 | |
696 | /* USB OTG CLK CTRL bit defines */ |
697 | #define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4) |
698 | #define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3) |
699 | #define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2) |
700 | #define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1) |
701 | #define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0) |
702 | |
703 | /* |
704 | * Start of virtual addresses for IO devices |
705 | */ |
706 | #define IO_BASE 0xF0000000 |
707 | |
708 | /* |
709 | * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 |
710 | */ |
711 | #define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\ |
712 | IO_BASE) |
713 | |
714 | #define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x)) |
715 | #define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff)) |
716 | |
717 | #endif |
718 | |