| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | |
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| 3 | #ifndef __ASM_ARCH_BRIDGE_REGS_H |
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| 4 | #define __ASM_ARCH_BRIDGE_REGS_H |
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| 5 | |
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| 6 | #include "mv78xx0.h" |
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| 7 | |
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| 8 | #define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) |
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| 9 | #define L2_WRITETHROUGH 0x00020000 |
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| 10 | |
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| 11 | #define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) |
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| 12 | #define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) |
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| 13 | #define SOFT_RESET_OUT_EN 0x00000004 |
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| 14 | |
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| 15 | #define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) |
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| 16 | #define SOFT_RESET 0x00000001 |
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| 17 | |
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| 18 | #define BRIDGE_INT_TIMER1_CLR (~0x0004) |
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| 19 | |
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| 20 | #define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) |
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| 21 | #define IRQ_CAUSE_ERR_OFF 0x0000 |
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| 22 | #define IRQ_CAUSE_LOW_OFF 0x0004 |
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| 23 | #define IRQ_CAUSE_HIGH_OFF 0x0008 |
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| 24 | #define IRQ_MASK_ERR_OFF 0x000c |
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| 25 | #define IRQ_MASK_LOW_OFF 0x0010 |
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| 26 | #define IRQ_MASK_HIGH_OFF 0x0014 |
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| 27 | |
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| 28 | #define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) |
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| 29 | #define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) |
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| 30 | |
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| 31 | #endif |
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| 32 | |
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