| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * linux/arch/arm/plat-omap/sram-fn.S |
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| 4 | * |
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| 5 | * Functions that need to be run in internal SRAM |
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| 6 | */ |
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| 7 | |
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| 8 | #include <linux/linkage.h> |
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| 9 | #include <linux/soc/ti/omap1-io.h> |
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| 10 | |
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| 11 | #include <asm/assembler.h> |
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| 12 | |
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| 13 | #include "hardware.h" |
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| 14 | #include "iomap.h" |
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| 15 | |
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| 16 | .text |
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| 17 | |
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| 18 | /* |
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| 19 | * Reprograms ULPD and CKCTL. |
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| 20 | */ |
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| 21 | .align 3 |
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| 22 | ENTRY(omap1_sram_reprogram_clock) |
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| 23 | stmfd sp!, {r0 - r12, lr} @ save registers on stack |
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| 24 | |
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| 25 | mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000 |
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| 26 | orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000 |
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| 27 | orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00 |
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| 28 | |
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| 29 | mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000 |
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| 30 | orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000 |
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| 31 | orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00 |
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| 32 | |
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| 33 | tst r0, #1 << 4 @ want lock mode? |
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| 34 | beq newck @ nope |
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| 35 | bic r0, r0, #1 << 4 @ else clear lock bit |
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| 36 | strh r0, [r2] @ set dpll into bypass mode |
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| 37 | orr r0, r0, #1 << 4 @ set lock bit again |
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| 38 | |
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| 39 | newck: |
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| 40 | strh r1, [r3] @ write new ckctl value |
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| 41 | strh r0, [r2] @ write new dpll value |
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| 42 | |
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| 43 | mov r4, #0x0700 @ let the clocks settle |
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| 44 | orr r4, r4, #0x00ff |
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| 45 | delay: sub r4, r4, #1 |
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| 46 | cmp r4, #0 |
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| 47 | bne delay |
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| 48 | |
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| 49 | lock: ldrh r4, [r2], #0 @ read back dpll value |
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| 50 | tst r0, #1 << 4 @ want lock mode? |
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| 51 | beq out @ nope |
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| 52 | tst r4, #1 << 0 @ dpll rate locked? |
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| 53 | beq lock @ try again |
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| 54 | |
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| 55 | out: |
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| 56 | ldmfd sp!, {r0 - r12, pc} @ restore regs and return |
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| 57 | ENTRY(omap1_sram_reprogram_clock_sz) |
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| 58 | .word . - omap1_sram_reprogram_clock |
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| 59 | |
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