| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * DRA7xx CM2 instance offset macros |
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| 4 | * |
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| 5 | * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com |
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| 6 | * |
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| 7 | * Generated by code originally written by: |
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| 8 | * Paul Walmsley (paul@pwsan.com) |
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| 9 | * Rajendra Nayak (rnayak@ti.com) |
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| 10 | * Benoit Cousson (b-cousson@ti.com) |
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| 11 | * |
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| 12 | * This file is automatically generated from the OMAP hardware databases. |
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| 13 | * We respectfully ask that any modifications to this file be coordinated |
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| 14 | * with the public linux-omap@vger.kernel.org mailing list and the |
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| 15 | * authors above to ensure that the autogeneration scripts are kept |
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| 16 | * up-to-date with the file contents. |
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| 17 | */ |
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| 18 | |
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| 19 | #ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H |
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| 20 | #define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H |
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| 21 | |
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| 22 | /* CM2 base address */ |
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| 23 | #define DRA7XX_CM_CORE_BASE 0x4a008000 |
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| 24 | |
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| 25 | #define DRA7XX_CM_CORE_REGADDR(inst, reg) \ |
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| 26 | OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg)) |
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| 27 | |
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| 28 | /* CM_CORE instances */ |
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| 29 | #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000 |
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| 30 | #define DRA7XX_CM_CORE_CKGEN_INST 0x0104 |
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| 31 | #define DRA7XX_CM_CORE_COREAON_INST 0x0600 |
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| 32 | #define DRA7XX_CM_CORE_CORE_INST 0x0700 |
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| 33 | #define DRA7XX_CM_CORE_IVA_INST 0x0f00 |
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| 34 | #define DRA7XX_CM_CORE_CAM_INST 0x1000 |
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| 35 | #define DRA7XX_CM_CORE_DSS_INST 0x1100 |
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| 36 | #define DRA7XX_CM_CORE_GPU_INST 0x1200 |
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| 37 | #define DRA7XX_CM_CORE_L3INIT_INST 0x1300 |
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| 38 | #define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600 |
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| 39 | #define DRA7XX_CM_CORE_L4PER_INST 0x1700 |
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| 40 | |
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| 41 | /* CM_CORE clockdomain register offsets (from instance start) */ |
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| 42 | #define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 |
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| 43 | #define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 |
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| 44 | #define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200 |
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| 45 | #define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 |
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| 46 | #define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 |
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| 47 | #define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520 |
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| 48 | #define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 |
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| 49 | #define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 |
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| 50 | #define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 |
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| 51 | #define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 |
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| 52 | #define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 |
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| 53 | #define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 |
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| 54 | #define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 |
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| 55 | #define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0 |
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| 56 | #define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0 |
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| 57 | #define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 |
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| 58 | #define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000 |
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| 59 | #define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180 |
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| 60 | #define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc |
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| 61 | #define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210 |
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| 62 | |
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| 63 | #endif |
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| 64 | |
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