| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * AM43x PRCM defines |
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| 4 | * |
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| 5 | * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/ |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H |
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| 9 | #define __ARCH_ARM_MACH_OMAP2_PRCM_43XX_H |
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| 10 | |
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| 11 | #define AM43XX_PRM_PARTITION 1 |
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| 12 | #define AM43XX_CM_PARTITION 1 |
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| 13 | |
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| 14 | /* PRM instances */ |
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| 15 | #define AM43XX_PRM_OCP_SOCKET_INST 0x0000 |
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| 16 | #define AM43XX_PRM_MPU_INST 0x0300 |
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| 17 | #define AM43XX_PRM_GFX_INST 0x0400 |
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| 18 | #define AM43XX_PRM_RTC_INST 0x0500 |
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| 19 | #define AM43XX_PRM_TAMPER_INST 0x0600 |
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| 20 | #define AM43XX_PRM_CEFUSE_INST 0x0700 |
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| 21 | #define AM43XX_PRM_PER_INST 0x0800 |
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| 22 | #define AM43XX_PRM_WKUP_INST 0x2000 |
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| 23 | #define AM43XX_PRM_DEVICE_INST 0x4000 |
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| 24 | |
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| 25 | /* PRM_IRQ offsets */ |
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| 26 | #define AM43XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 |
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| 27 | #define AM43XX_PRM_IRQENABLE_MPU_OFFSET 0x0008 |
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| 28 | |
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| 29 | /* Other PRM offsets */ |
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| 30 | #define AM43XX_PRM_IO_PMCTRL_OFFSET 0x0024 |
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| 31 | |
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| 32 | /* CM instances */ |
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| 33 | #define AM43XX_CM_WKUP_INST 0x2800 |
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| 34 | #define AM43XX_CM_MPU_INST 0x8300 |
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| 35 | #define AM43XX_CM_GFX_INST 0x8400 |
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| 36 | #define AM43XX_CM_RTC_INST 0x8500 |
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| 37 | #define AM43XX_CM_TAMPER_INST 0x8600 |
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| 38 | #define AM43XX_CM_CEFUSE_INST 0x8700 |
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| 39 | #define AM43XX_CM_PER_INST 0x8800 |
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| 40 | |
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| 41 | /* CD offsets */ |
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| 42 | #define AM43XX_CM_WKUP_L3_AON_CDOFFS 0x0000 |
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| 43 | #define AM43XX_CM_WKUP_L3S_TSC_CDOFFS 0x0100 |
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| 44 | #define AM43XX_CM_WKUP_L4_WKUP_AON_CDOFFS 0x0200 |
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| 45 | #define AM43XX_CM_WKUP_WKUP_CDOFFS 0x0300 |
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| 46 | #define AM43XX_CM_MPU_MPU_CDOFFS 0x0000 |
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| 47 | #define AM43XX_CM_GFX_GFX_L3_CDOFFS 0x0000 |
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| 48 | #define AM43XX_CM_RTC_RTC_CDOFFS 0x0000 |
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| 49 | #define AM43XX_CM_TAMPER_TAMPER_CDOFFS 0x0000 |
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| 50 | #define AM43XX_CM_CEFUSE_CEFUSE_CDOFFS 0x0000 |
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| 51 | #define AM43XX_CM_PER_L3_CDOFFS 0x0000 |
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| 52 | #define AM43XX_CM_PER_L3S_CDOFFS 0x0200 |
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| 53 | #define AM43XX_CM_PER_ICSS_CDOFFS 0x0300 |
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| 54 | #define AM43XX_CM_PER_L4LS_CDOFFS 0x0400 |
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| 55 | #define AM43XX_CM_PER_EMIF_CDOFFS 0x0700 |
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| 56 | #define AM43XX_CM_PER_LCDC_CDOFFS 0x0800 |
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| 57 | #define AM43XX_CM_PER_DSS_CDOFFS 0x0a00 |
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| 58 | #define AM43XX_CM_PER_CPSW_CDOFFS 0x0b00 |
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| 59 | #define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00 |
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| 60 | |
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| 61 | /* CLK CTRL offsets */ |
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| 62 | #define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 |
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| 63 | #define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0720 |
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| 64 | |
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| 65 | #endif |
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| 66 | |
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