| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * OMAP44xx PRM instance offset macros |
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| 4 | * |
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| 5 | * Copyright (C) 2009-2011 Texas Instruments, Inc. |
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| 6 | * Copyright (C) 2009-2010 Nokia Corporation |
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| 7 | * |
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| 8 | * Paul Walmsley (paul@pwsan.com) |
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| 9 | * Rajendra Nayak (rnayak@ti.com) |
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| 10 | * Benoit Cousson (b-cousson@ti.com) |
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| 11 | * |
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| 12 | * This file is automatically generated from the OMAP hardware databases. |
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| 13 | * We respectfully ask that any modifications to this file be coordinated |
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| 14 | * with the public linux-omap@vger.kernel.org mailing list and the |
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| 15 | * authors above to ensure that the autogeneration scripts are kept |
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| 16 | * up-to-date with the file contents. |
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| 17 | * |
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| 18 | * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", |
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| 19 | * or "OMAP4430". |
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| 20 | */ |
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| 21 | |
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| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM44XX_H |
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| 23 | #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H |
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| 24 | |
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| 25 | #include "prm44xx_54xx.h" |
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| 26 | #include "prm.h" |
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| 27 | |
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| 28 | #define OMAP4430_PRM_BASE 0x4a306000 |
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| 29 | |
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| 30 | #define OMAP44XX_PRM_REGADDR(inst, reg) \ |
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| 31 | OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg)) |
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| 32 | |
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| 33 | |
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| 34 | /* PRM instances */ |
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| 35 | #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000 |
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| 36 | #define OMAP4430_PRM_CKGEN_INST 0x0100 |
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| 37 | #define OMAP4430_PRM_MPU_INST 0x0300 |
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| 38 | #define OMAP4430_PRM_TESLA_INST 0x0400 |
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| 39 | #define OMAP4430_PRM_ABE_INST 0x0500 |
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| 40 | #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600 |
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| 41 | #define OMAP4430_PRM_CORE_INST 0x0700 |
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| 42 | #define OMAP4430_PRM_IVAHD_INST 0x0f00 |
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| 43 | #define OMAP4430_PRM_CAM_INST 0x1000 |
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| 44 | #define OMAP4430_PRM_DSS_INST 0x1100 |
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| 45 | #define OMAP4430_PRM_GFX_INST 0x1200 |
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| 46 | #define OMAP4430_PRM_L3INIT_INST 0x1300 |
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| 47 | #define OMAP4430_PRM_L4PER_INST 0x1400 |
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| 48 | #define OMAP4430_PRM_CEFUSE_INST 0x1600 |
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| 49 | #define OMAP4430_PRM_WKUP_INST 0x1700 |
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| 50 | #define OMAP4430_PRM_WKUP_CM_INST 0x1800 |
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| 51 | #define OMAP4430_PRM_EMU_INST 0x1900 |
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| 52 | #define OMAP4430_PRM_EMU_CM_INST 0x1a00 |
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| 53 | #define OMAP4430_PRM_DEVICE_INST 0x1b00 |
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| 54 | |
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| 55 | /* PRM clockdomain register offsets (from instance start) */ |
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| 56 | #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 |
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| 57 | #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 |
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| 58 | |
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| 59 | /* OMAP4 specific register offsets */ |
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| 60 | #define OMAP4_RM_RSTST 0x0004 |
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| 61 | #define OMAP4_PM_PWSTCTRL 0x0000 |
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| 62 | #define OMAP4_PM_PWSTST 0x0004 |
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| 63 | |
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| 64 | /* PRM.OCP_SOCKET_PRM register offsets */ |
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| 65 | #define OMAP4_REVISION_PRM_OFFSET 0x0000 |
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| 66 | #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010 |
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| 67 | #define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010) |
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| 68 | #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 |
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| 69 | #define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018 |
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| 70 | #define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018) |
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| 71 | |
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| 72 | /* PRM.MPU_PRM register offsets */ |
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| 73 | #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 |
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| 74 | |
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| 75 | /* PRM.DEVICE_PRM register offsets */ |
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| 76 | #define OMAP4_PRM_RSTCTRL_OFFSET 0x0000 |
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| 77 | #define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010 |
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| 78 | #define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020 |
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| 79 | #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 |
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| 80 | #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c |
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| 81 | #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030 |
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| 82 | #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 |
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| 83 | #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 |
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| 84 | #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c |
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| 85 | #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040 |
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| 86 | #define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044 |
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| 87 | #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 |
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| 88 | #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c |
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| 89 | #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 |
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| 90 | #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 |
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| 91 | #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058 |
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| 92 | #define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c |
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| 93 | #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 |
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| 94 | #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 |
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| 95 | #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 |
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| 96 | #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c |
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| 97 | #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070 |
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| 98 | #define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074 |
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| 99 | #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078 |
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| 100 | #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c |
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| 101 | #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080 |
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| 102 | #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084 |
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| 103 | #define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088 |
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| 104 | #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c |
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| 105 | #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090 |
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| 106 | #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 |
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| 107 | #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098 |
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| 108 | #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c |
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| 109 | #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 |
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| 110 | #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 |
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| 111 | #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8 |
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| 112 | #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac |
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| 113 | |
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| 114 | #endif |
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| 115 | |
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