| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * IRQ definitions for Orion SoC |
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| 4 | * |
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| 5 | * Maintainer: Tzachi Perelstein <tzachi@marvell.com> |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef __ASM_ARCH_IRQS_H |
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| 9 | #define __ASM_ARCH_IRQS_H |
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| 10 | |
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| 11 | /* |
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| 12 | * Orion Main Interrupt Controller |
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| 13 | */ |
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| 14 | #define IRQ_ORION5X_BRIDGE (1 + 0) |
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| 15 | #define IRQ_ORION5X_DOORBELL_H2C (1 + 1) |
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| 16 | #define IRQ_ORION5X_DOORBELL_C2H (1 + 2) |
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| 17 | #define IRQ_ORION5X_UART0 (1 + 3) |
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| 18 | #define IRQ_ORION5X_UART1 (1 + 4) |
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| 19 | #define IRQ_ORION5X_I2C (1 + 5) |
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| 20 | #define IRQ_ORION5X_GPIO_0_7 (1 + 6) |
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| 21 | #define IRQ_ORION5X_GPIO_8_15 (1 + 7) |
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| 22 | #define IRQ_ORION5X_GPIO_16_23 (1 + 8) |
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| 23 | #define IRQ_ORION5X_GPIO_24_31 (1 + 9) |
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| 24 | #define IRQ_ORION5X_PCIE0_ERR (1 + 10) |
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| 25 | #define IRQ_ORION5X_PCIE0_INT (1 + 11) |
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| 26 | #define IRQ_ORION5X_USB1_CTRL (1 + 12) |
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| 27 | #define IRQ_ORION5X_DEV_BUS_ERR (1 + 14) |
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| 28 | #define IRQ_ORION5X_PCI_ERR (1 + 15) |
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| 29 | #define IRQ_ORION5X_USB_BR_ERR (1 + 16) |
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| 30 | #define IRQ_ORION5X_USB0_CTRL (1 + 17) |
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| 31 | #define IRQ_ORION5X_ETH_RX (1 + 18) |
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| 32 | #define IRQ_ORION5X_ETH_TX (1 + 19) |
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| 33 | #define IRQ_ORION5X_ETH_MISC (1 + 20) |
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| 34 | #define IRQ_ORION5X_ETH_SUM (1 + 21) |
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| 35 | #define IRQ_ORION5X_ETH_ERR (1 + 22) |
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| 36 | #define IRQ_ORION5X_IDMA_ERR (1 + 23) |
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| 37 | #define IRQ_ORION5X_IDMA_0 (1 + 24) |
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| 38 | #define IRQ_ORION5X_IDMA_1 (1 + 25) |
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| 39 | #define IRQ_ORION5X_IDMA_2 (1 + 26) |
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| 40 | #define IRQ_ORION5X_IDMA_3 (1 + 27) |
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| 41 | #define IRQ_ORION5X_CESA (1 + 28) |
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| 42 | #define IRQ_ORION5X_SATA (1 + 29) |
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| 43 | #define IRQ_ORION5X_XOR0 (1 + 30) |
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| 44 | #define IRQ_ORION5X_XOR1 (1 + 31) |
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| 45 | |
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| 46 | /* |
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| 47 | * Orion General Purpose Pins |
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| 48 | */ |
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| 49 | #define IRQ_ORION5X_GPIO_START 33 |
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| 50 | #define NR_GPIO_IRQS 32 |
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| 51 | |
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| 52 | #define ORION5X_NR_IRQS (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS) |
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| 53 | |
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| 54 | |
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| 55 | #endif |
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| 56 | |
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