| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #ifndef __ASM_MACH_ADDR_MAP_H |
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| 3 | #define __ASM_MACH_ADDR_MAP_H |
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| 4 | |
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| 5 | /* |
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| 6 | * Chip Selects |
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| 7 | */ |
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| 8 | #define PXA_CS0_PHYS 0x00000000 |
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| 9 | #define PXA_CS1_PHYS 0x04000000 |
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| 10 | #define PXA_CS2_PHYS 0x08000000 |
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| 11 | #define PXA_CS3_PHYS 0x0C000000 |
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| 12 | #define PXA_CS4_PHYS 0x10000000 |
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| 13 | #define PXA_CS5_PHYS 0x14000000 |
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| 14 | |
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| 15 | #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */ |
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| 16 | #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */ |
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| 17 | #define PXA3xx_CS2_PHYS 0x10000000 |
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| 18 | #define PXA3xx_CS3_PHYS 0x14000000 |
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| 19 | |
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| 20 | /* |
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| 21 | * Peripheral Bus |
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| 22 | */ |
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| 23 | #define PERIPH_PHYS 0x40000000 |
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| 24 | #define PERIPH_VIRT IOMEM(0xf2000000) |
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| 25 | #define PERIPH_SIZE 0x02000000 |
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| 26 | |
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| 27 | /* |
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| 28 | * Static Memory Controller (w/ SDRAM controls on PXA25x/PXA27x) |
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| 29 | */ |
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| 30 | #define PXA2XX_SMEMC_PHYS 0x48000000 |
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| 31 | #define PXA3XX_SMEMC_PHYS 0x4a000000 |
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| 32 | #define SMEMC_VIRT IOMEM(0xf6000000) |
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| 33 | #define SMEMC_SIZE 0x00100000 |
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| 34 | |
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| 35 | /* |
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| 36 | * Dynamic Memory Controller (only on PXA3xx) |
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| 37 | */ |
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| 38 | #define DMEMC_PHYS 0x48100000 |
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| 39 | #define DMEMC_VIRT IOMEM(0xf6100000) |
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| 40 | #define DMEMC_SIZE 0x00100000 |
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| 41 | |
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| 42 | /* |
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| 43 | * Reserved space for low level debug virtual addresses within |
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| 44 | * 0xf6200000..0xf6201000 |
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| 45 | */ |
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| 46 | |
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| 47 | /* |
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| 48 | * DFI Bus for NAND, PXA3xx only |
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| 49 | */ |
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| 50 | #define NAND_PHYS 0x43100000 |
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| 51 | #define NAND_VIRT IOMEM(0xf6300000) |
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| 52 | #define NAND_SIZE 0x00100000 |
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| 53 | |
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| 54 | /* |
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| 55 | * Internal Memory Controller (PXA27x and later) |
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| 56 | */ |
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| 57 | #define IMEMC_PHYS 0x58000000 |
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| 58 | #define IMEMC_VIRT IOMEM(0xfe000000) |
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| 59 | #define IMEMC_SIZE 0x00100000 |
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| 60 | |
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| 61 | #endif /* __ASM_MACH_ADDR_MAP_H */ |
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| 62 | |
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