| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd |
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| 4 | * Author: Tony Xie <tony.xie@rock-chips.com> |
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| 5 | */ |
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| 6 | |
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| 7 | #include <linux/linkage.h> |
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| 8 | #include <asm/assembler.h> |
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| 9 | #include <asm/page.h> |
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| 10 | |
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| 11 | .data |
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| 12 | /* |
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| 13 | * this code will be copied from |
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| 14 | * ddr to sram for system resumeing. |
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| 15 | * so it is ".data section". |
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| 16 | */ |
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| 17 | .align 2 |
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| 18 | |
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| 19 | ENTRY(rockchip_slp_cpu_resume) |
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| 20 | setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off |
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| 21 | mrc p15, 0, r1, c0, c0, 5 |
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| 22 | and r1, r1, #0xf |
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| 23 | cmp r1, #0 |
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| 24 | /* olny cpu0 can continue to run, the others is halt here */ |
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| 25 | beq cpu0run |
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| 26 | secondary_loop: |
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| 27 | wfe |
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| 28 | b secondary_loop |
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| 29 | cpu0run: |
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| 30 | ldr r3, rkpm_bootdata_l2ctlr_f |
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| 31 | cmp r3, #0 |
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| 32 | beq sp_set |
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| 33 | ldr r3, rkpm_bootdata_l2ctlr |
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| 34 | mcr p15, 1, r3, c9, c0, 2 |
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| 35 | sp_set: |
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| 36 | ldr sp, rkpm_bootdata_cpusp |
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| 37 | ldr r1, rkpm_bootdata_cpu_code |
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| 38 | bx r1 |
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| 39 | ENDPROC(rockchip_slp_cpu_resume) |
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| 40 | |
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| 41 | /* Parameters filled in by the kernel */ |
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| 42 | |
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| 43 | /* Flag for whether to restore L2CTLR on resume */ |
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| 44 | .global rkpm_bootdata_l2ctlr_f |
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| 45 | rkpm_bootdata_l2ctlr_f: |
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| 46 | .long 0 |
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| 47 | |
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| 48 | /* Saved L2CTLR to restore on resume */ |
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| 49 | .global rkpm_bootdata_l2ctlr |
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| 50 | rkpm_bootdata_l2ctlr: |
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| 51 | .long 0 |
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| 52 | |
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| 53 | /* CPU resume SP addr */ |
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| 54 | .globl rkpm_bootdata_cpusp |
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| 55 | rkpm_bootdata_cpusp: |
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| 56 | .long 0 |
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| 57 | |
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| 58 | /* CPU resume function (physical address) */ |
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| 59 | .globl rkpm_bootdata_cpu_code |
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| 60 | rkpm_bootdata_cpu_code: |
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| 61 | .long 0 |
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| 62 | |
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| 63 | ENTRY(rk3288_bootram_sz) |
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| 64 | .word . - rockchip_slp_cpu_resume |
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| 65 | |
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