| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* linux/arch/arm/mach-s3c64xx/include/mach/irqs.h |
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| 3 | * |
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| 4 | * Copyright 2008 Openmoko, Inc. |
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| 5 | * Copyright 2008 Simtec Electronics |
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| 6 | * Ben Dooks <ben@simtec.co.uk> |
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| 7 | * http://armlinux.simtec.co.uk/ |
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| 8 | * |
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| 9 | * S3C64XX - IRQ support |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef __ASM_MACH_S3C64XX_IRQS_H |
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| 13 | #define __ASM_MACH_S3C64XX_IRQS_H __FILE__ |
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| 14 | |
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| 15 | /* we keep the first set of CPU IRQs out of the range of |
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| 16 | * the ISA space, so that the PC104 has them to itself |
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| 17 | * and we don't end up having to do horrible things to the |
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| 18 | * standard ISA drivers.... |
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| 19 | * |
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| 20 | * note, since we're using the VICs, our start must be a |
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| 21 | * mulitple of 32 to allow the common code to work |
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| 22 | */ |
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| 23 | |
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| 24 | #define S3C_IRQ_OFFSET (32) |
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| 25 | |
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| 26 | #define S3C_IRQ(x) ((x) + S3C_IRQ_OFFSET) |
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| 27 | |
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| 28 | #define IRQ_VIC0_BASE S3C_IRQ(0) |
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| 29 | #define IRQ_VIC1_BASE S3C_IRQ(32) |
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| 30 | |
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| 31 | /* VIC based IRQs */ |
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| 32 | |
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| 33 | #define S3C64XX_IRQ_VIC0(x) (IRQ_VIC0_BASE + (x)) |
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| 34 | #define S3C64XX_IRQ_VIC1(x) (IRQ_VIC1_BASE + (x)) |
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| 35 | |
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| 36 | /* VIC0 */ |
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| 37 | |
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| 38 | #define IRQ_EINT0_3 S3C64XX_IRQ_VIC0(0) |
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| 39 | #define IRQ_EINT4_11 S3C64XX_IRQ_VIC0(1) |
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| 40 | #define IRQ_RTC_TIC S3C64XX_IRQ_VIC0(2) |
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| 41 | #define IRQ_CAMIF_C S3C64XX_IRQ_VIC0(3) |
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| 42 | #define IRQ_CAMIF_P S3C64XX_IRQ_VIC0(4) |
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| 43 | #define IRQ_CAMIF_MC S3C64XX_IRQ_VIC0(5) |
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| 44 | #define IRQ_S3C6410_IIC1 S3C64XX_IRQ_VIC0(5) |
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| 45 | #define IRQ_S3C6410_IIS S3C64XX_IRQ_VIC0(6) |
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| 46 | #define IRQ_S3C6400_CAMIF_MP S3C64XX_IRQ_VIC0(6) |
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| 47 | #define IRQ_CAMIF_WE_C S3C64XX_IRQ_VIC0(7) |
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| 48 | #define IRQ_S3C6410_G3D S3C64XX_IRQ_VIC0(8) |
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| 49 | #define IRQ_S3C6400_CAMIF_WE_P S3C64XX_IRQ_VIC0(8) |
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| 50 | #define IRQ_POST0 S3C64XX_IRQ_VIC0(9) |
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| 51 | #define IRQ_ROTATOR S3C64XX_IRQ_VIC0(10) |
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| 52 | #define IRQ_2D S3C64XX_IRQ_VIC0(11) |
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| 53 | #define IRQ_TVENC S3C64XX_IRQ_VIC0(12) |
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| 54 | #define IRQ_SCALER S3C64XX_IRQ_VIC0(13) |
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| 55 | #define IRQ_BATF S3C64XX_IRQ_VIC0(14) |
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| 56 | #define IRQ_JPEG S3C64XX_IRQ_VIC0(15) |
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| 57 | #define IRQ_MFC S3C64XX_IRQ_VIC0(16) |
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| 58 | #define IRQ_SDMA0 S3C64XX_IRQ_VIC0(17) |
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| 59 | #define IRQ_SDMA1 S3C64XX_IRQ_VIC0(18) |
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| 60 | #define IRQ_ARM_DMAERR S3C64XX_IRQ_VIC0(19) |
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| 61 | #define IRQ_ARM_DMA S3C64XX_IRQ_VIC0(20) |
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| 62 | #define IRQ_ARM_DMAS S3C64XX_IRQ_VIC0(21) |
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| 63 | #define IRQ_KEYPAD S3C64XX_IRQ_VIC0(22) |
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| 64 | #define IRQ_TIMER0_VIC S3C64XX_IRQ_VIC0(23) |
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| 65 | #define IRQ_TIMER1_VIC S3C64XX_IRQ_VIC0(24) |
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| 66 | #define IRQ_TIMER2_VIC S3C64XX_IRQ_VIC0(25) |
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| 67 | #define IRQ_WDT S3C64XX_IRQ_VIC0(26) |
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| 68 | #define IRQ_TIMER3_VIC S3C64XX_IRQ_VIC0(27) |
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| 69 | #define IRQ_TIMER4_VIC S3C64XX_IRQ_VIC0(28) |
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| 70 | #define IRQ_LCD_FIFO S3C64XX_IRQ_VIC0(29) |
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| 71 | #define IRQ_LCD_VSYNC S3C64XX_IRQ_VIC0(30) |
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| 72 | #define IRQ_LCD_SYSTEM S3C64XX_IRQ_VIC0(31) |
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| 73 | |
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| 74 | /* VIC1 */ |
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| 75 | |
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| 76 | #define IRQ_EINT12_19 S3C64XX_IRQ_VIC1(0) |
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| 77 | #define IRQ_EINT20_27 S3C64XX_IRQ_VIC1(1) |
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| 78 | #define IRQ_PCM0 S3C64XX_IRQ_VIC1(2) |
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| 79 | #define IRQ_PCM1 S3C64XX_IRQ_VIC1(3) |
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| 80 | #define IRQ_AC97 S3C64XX_IRQ_VIC1(4) |
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| 81 | #define IRQ_UART0 S3C64XX_IRQ_VIC1(5) |
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| 82 | #define IRQ_UART1 S3C64XX_IRQ_VIC1(6) |
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| 83 | #define IRQ_UART2 S3C64XX_IRQ_VIC1(7) |
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| 84 | #define IRQ_UART3 S3C64XX_IRQ_VIC1(8) |
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| 85 | #define IRQ_DMA0 S3C64XX_IRQ_VIC1(9) |
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| 86 | #define IRQ_DMA1 S3C64XX_IRQ_VIC1(10) |
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| 87 | #define IRQ_ONENAND0 S3C64XX_IRQ_VIC1(11) |
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| 88 | #define IRQ_ONENAND1 S3C64XX_IRQ_VIC1(12) |
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| 89 | #define IRQ_NFC S3C64XX_IRQ_VIC1(13) |
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| 90 | #define IRQ_CFCON S3C64XX_IRQ_VIC1(14) |
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| 91 | #define IRQ_USBH S3C64XX_IRQ_VIC1(15) |
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| 92 | #define IRQ_SPI0 S3C64XX_IRQ_VIC1(16) |
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| 93 | #define IRQ_SPI1 S3C64XX_IRQ_VIC1(17) |
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| 94 | #define IRQ_IIC S3C64XX_IRQ_VIC1(18) |
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| 95 | #define IRQ_HSItx S3C64XX_IRQ_VIC1(19) |
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| 96 | #define IRQ_HSIrx S3C64XX_IRQ_VIC1(20) |
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| 97 | #define IRQ_RESERVED S3C64XX_IRQ_VIC1(21) |
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| 98 | #define IRQ_MSM S3C64XX_IRQ_VIC1(22) |
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| 99 | #define IRQ_HOSTIF S3C64XX_IRQ_VIC1(23) |
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| 100 | #define IRQ_HSMMC0 S3C64XX_IRQ_VIC1(24) |
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| 101 | #define IRQ_HSMMC1 S3C64XX_IRQ_VIC1(25) |
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| 102 | #define IRQ_HSMMC2 IRQ_SPI1 /* shared with SPI1 */ |
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| 103 | #define IRQ_OTG S3C64XX_IRQ_VIC1(26) |
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| 104 | #define IRQ_IRDA S3C64XX_IRQ_VIC1(27) |
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| 105 | #define IRQ_RTC_ALARM S3C64XX_IRQ_VIC1(28) |
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| 106 | #define IRQ_SEC S3C64XX_IRQ_VIC1(29) |
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| 107 | #define IRQ_PENDN S3C64XX_IRQ_VIC1(30) |
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| 108 | #define IRQ_TC IRQ_PENDN |
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| 109 | #define IRQ_ADC S3C64XX_IRQ_VIC1(31) |
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| 110 | |
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| 111 | /* compatibility for device defines */ |
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| 112 | |
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| 113 | #define IRQ_IIC1 IRQ_S3C6410_IIC1 |
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| 114 | |
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| 115 | /* Since the IRQ_EINT(x) are a linear mapping on current s3c64xx series |
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| 116 | * we just defined them as an IRQ_EINT(x) macro from S3C_IRQ_EINT_BASE |
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| 117 | * which we place after the pair of VICs. */ |
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| 118 | |
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| 119 | #define S3C_IRQ_EINT_BASE S3C_IRQ(64+5) |
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| 120 | |
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| 121 | #define S3C_EINT(x) ((x) + S3C_IRQ_EINT_BASE) |
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| 122 | #define IRQ_EINT(x) S3C_EINT(x) |
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| 123 | #define IRQ_EINT_BIT(x) ((x) - S3C_EINT(0)) |
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| 124 | |
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| 125 | /* Next the external interrupt groups. These are similar to the IRQ_EINT(x) |
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| 126 | * that they are sourced from the GPIO pins but with a different scheme for |
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| 127 | * priority and source indication. |
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| 128 | * |
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| 129 | * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO |
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| 130 | * interrupts, but for historical reasons they are kept apart from these |
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| 131 | * next interrupts. |
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| 132 | * |
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| 133 | * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the |
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| 134 | * machine specific support files. |
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| 135 | */ |
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| 136 | |
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| 137 | #define IRQ_EINT_GROUP1_NR (15) |
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| 138 | #define IRQ_EINT_GROUP2_NR (8) |
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| 139 | #define IRQ_EINT_GROUP3_NR (5) |
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| 140 | #define IRQ_EINT_GROUP4_NR (14) |
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| 141 | #define IRQ_EINT_GROUP5_NR (7) |
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| 142 | #define IRQ_EINT_GROUP6_NR (10) |
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| 143 | #define IRQ_EINT_GROUP7_NR (16) |
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| 144 | #define IRQ_EINT_GROUP8_NR (15) |
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| 145 | #define IRQ_EINT_GROUP9_NR (9) |
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| 146 | |
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| 147 | #define IRQ_EINT_GROUP_BASE S3C_EINT(28) |
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| 148 | #define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0x00) |
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| 149 | #define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) |
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| 150 | #define IRQ_EINT_GROUP3_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) |
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| 151 | #define IRQ_EINT_GROUP4_BASE (IRQ_EINT_GROUP3_BASE + IRQ_EINT_GROUP3_NR) |
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| 152 | #define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP4_BASE + IRQ_EINT_GROUP4_NR) |
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| 153 | #define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) |
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| 154 | #define IRQ_EINT_GROUP7_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) |
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| 155 | #define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP7_BASE + IRQ_EINT_GROUP7_NR) |
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| 156 | #define IRQ_EINT_GROUP9_BASE (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR) |
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| 157 | |
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| 158 | #define IRQ_EINT_GROUP(group, no) (IRQ_EINT_GROUP##group##_BASE + (no)) |
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| 159 | |
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| 160 | /* Some boards have their own IRQs behind this */ |
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| 161 | #define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1) |
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| 162 | |
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| 163 | /* Set the default nr_irqs, boards can override if necessary */ |
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| 164 | #define S3C64XX_NR_IRQS IRQ_BOARD_START |
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| 165 | |
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| 166 | /* Compatibility */ |
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| 167 | |
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| 168 | #define IRQ_ONENAND IRQ_ONENAND0 |
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| 169 | #define IRQ_I2S0 IRQ_S3C6410_IIS |
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| 170 | |
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| 171 | #endif /* __ASM_MACH_S3C64XX_IRQS_H */ |
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| 172 | |
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| 173 | |
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