| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright 2003, 2007 Simtec Electronics |
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| 4 | * http://armlinux.simtec.co.uk/ |
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| 5 | * Ben Dooks <ben@simtec.co.uk> |
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| 6 | * |
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| 7 | * S3C - Memory map definitions (virtual addresses) |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __ASM_PLAT_MAP_H |
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| 11 | #define __ASM_PLAT_MAP_H __FILE__ |
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| 12 | |
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| 13 | /* Fit all our registers in at 0xF6000000 upwards, trying to use as |
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| 14 | * little of the VA space as possible so vmalloc and friends have a |
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| 15 | * better chance of getting memory. |
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| 16 | * |
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| 17 | * we try to ensure stuff like the IRQ registers are available for |
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| 18 | * an single MOVS instruction (ie, only 8 bits of set data) |
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| 19 | */ |
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| 20 | |
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| 21 | #define S3C_ADDR_BASE 0xF6000000 |
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| 22 | |
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| 23 | #ifndef __ASSEMBLY__ |
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| 24 | #define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x)) |
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| 25 | #else |
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| 26 | #define S3C_ADDR(x) (S3C_ADDR_BASE + (x)) |
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| 27 | #endif |
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| 28 | |
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| 29 | #define S3C_VA_IRQ S3C_ADDR(0x00000000) /* irq controller(s) */ |
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| 30 | #define S3C_VA_SYS S3C_ADDR(0x00100000) /* system control */ |
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| 31 | #define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ |
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| 32 | #define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ |
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| 33 | #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ |
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| 34 | #define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ |
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| 35 | |
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| 36 | /* ISA device mapping for BAST to use with inb()/outb() on 8-bit I/O. |
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| 37 | * 16-bit I/O on BAST now requires driver modifications to manually |
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| 38 | * ioremap CS3. |
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| 39 | */ |
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| 40 | #define S3C24XX_VA_ISA_BYTE PCI_IOBASE |
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| 41 | |
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| 42 | /* This is used for the CPU specific mappings that may be needed, so that |
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| 43 | * they do not need to directly used S3C_ADDR() and thus make it easier to |
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| 44 | * modify the space for mapping. |
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| 45 | */ |
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| 46 | #define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x)) |
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| 47 | |
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| 48 | #endif /* __ASM_PLAT_MAP_H */ |
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| 49 | |
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