| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* linux/arch/arm/plat-s3c64xx/include/mach/regs-gpio.h |
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| 3 | * |
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| 4 | * Copyright 2008 Openmoko, Inc. |
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| 5 | * Copyright 2008 Simtec Electronics |
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| 6 | * Ben Dooks <ben@simtec.co.uk> |
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| 7 | * http://armlinux.simtec.co.uk/ |
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| 8 | * |
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| 9 | * S3C64XX - GPIO register definitions |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef __ASM_PLAT_S3C64XX_REGS_GPIO_H |
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| 13 | #define __ASM_PLAT_S3C64XX_REGS_GPIO_H __FILE__ |
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| 14 | |
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| 15 | /* Base addresses for each of the banks */ |
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| 16 | |
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| 17 | #define S3C64XX_GPIOREG(reg) (S3C64XX_VA_GPIO + (reg)) |
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| 18 | |
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| 19 | #define S3C64XX_GPA_BASE S3C64XX_GPIOREG(0x0000) |
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| 20 | #define S3C64XX_GPB_BASE S3C64XX_GPIOREG(0x0020) |
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| 21 | #define S3C64XX_GPC_BASE S3C64XX_GPIOREG(0x0040) |
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| 22 | #define S3C64XX_GPD_BASE S3C64XX_GPIOREG(0x0060) |
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| 23 | #define S3C64XX_GPE_BASE S3C64XX_GPIOREG(0x0080) |
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| 24 | #define S3C64XX_GPF_BASE S3C64XX_GPIOREG(0x00A0) |
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| 25 | #define S3C64XX_GPG_BASE S3C64XX_GPIOREG(0x00C0) |
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| 26 | #define S3C64XX_GPH_BASE S3C64XX_GPIOREG(0x00E0) |
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| 27 | #define S3C64XX_GPI_BASE S3C64XX_GPIOREG(0x0100) |
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| 28 | #define S3C64XX_GPJ_BASE S3C64XX_GPIOREG(0x0120) |
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| 29 | #define S3C64XX_GPK_BASE S3C64XX_GPIOREG(0x0800) |
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| 30 | #define S3C64XX_GPL_BASE S3C64XX_GPIOREG(0x0810) |
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| 31 | #define S3C64XX_GPM_BASE S3C64XX_GPIOREG(0x0820) |
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| 32 | #define S3C64XX_GPN_BASE S3C64XX_GPIOREG(0x0830) |
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| 33 | #define S3C64XX_GPO_BASE S3C64XX_GPIOREG(0x0140) |
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| 34 | #define S3C64XX_GPP_BASE S3C64XX_GPIOREG(0x0160) |
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| 35 | #define S3C64XX_GPQ_BASE S3C64XX_GPIOREG(0x0180) |
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| 36 | |
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| 37 | /* SPCON */ |
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| 38 | |
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| 39 | #define S3C64XX_SPCON S3C64XX_GPIOREG(0x1A0) |
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| 40 | |
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| 41 | #define S3C64XX_SPCON_DRVCON_CAM_MASK (0x3 << 30) |
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| 42 | #define S3C64XX_SPCON_DRVCON_CAM_SHIFT (30) |
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| 43 | #define S3C64XX_SPCON_DRVCON_CAM_2mA (0x0 << 30) |
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| 44 | #define S3C64XX_SPCON_DRVCON_CAM_4mA (0x1 << 30) |
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| 45 | #define S3C64XX_SPCON_DRVCON_CAM_7mA (0x2 << 30) |
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| 46 | #define S3C64XX_SPCON_DRVCON_CAM_9mA (0x3 << 30) |
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| 47 | |
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| 48 | #define S3C64XX_SPCON_DRVCON_HSSPI_MASK (0x3 << 28) |
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| 49 | #define S3C64XX_SPCON_DRVCON_HSSPI_SHIFT (28) |
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| 50 | #define S3C64XX_SPCON_DRVCON_HSSPI_2mA (0x0 << 28) |
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| 51 | #define S3C64XX_SPCON_DRVCON_HSSPI_4mA (0x1 << 28) |
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| 52 | #define S3C64XX_SPCON_DRVCON_HSSPI_7mA (0x2 << 28) |
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| 53 | #define S3C64XX_SPCON_DRVCON_HSSPI_9mA (0x3 << 28) |
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| 54 | |
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| 55 | #define S3C64XX_SPCON_DRVCON_HSMMC_MASK (0x3 << 26) |
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| 56 | #define S3C64XX_SPCON_DRVCON_HSMMC_SHIFT (26) |
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| 57 | #define S3C64XX_SPCON_DRVCON_HSMMC_2mA (0x0 << 26) |
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| 58 | #define S3C64XX_SPCON_DRVCON_HSMMC_4mA (0x1 << 26) |
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| 59 | #define S3C64XX_SPCON_DRVCON_HSMMC_7mA (0x2 << 26) |
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| 60 | #define S3C64XX_SPCON_DRVCON_HSMMC_9mA (0x3 << 26) |
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| 61 | |
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| 62 | #define S3C64XX_SPCON_DRVCON_LCD_MASK (0x3 << 24) |
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| 63 | #define S3C64XX_SPCON_DRVCON_LCD_SHIFT (24) |
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| 64 | #define S3C64XX_SPCON_DRVCON_LCD_2mA (0x0 << 24) |
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| 65 | #define S3C64XX_SPCON_DRVCON_LCD_4mA (0x1 << 24) |
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| 66 | #define S3C64XX_SPCON_DRVCON_LCD_7mA (0x2 << 24) |
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| 67 | #define S3C64XX_SPCON_DRVCON_LCD_9mA (0x3 << 24) |
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| 68 | |
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| 69 | #define S3C64XX_SPCON_DRVCON_MODEM_MASK (0x3 << 22) |
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| 70 | #define S3C64XX_SPCON_DRVCON_MODEM_SHIFT (22) |
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| 71 | #define S3C64XX_SPCON_DRVCON_MODEM_2mA (0x0 << 22) |
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| 72 | #define S3C64XX_SPCON_DRVCON_MODEM_4mA (0x1 << 22) |
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| 73 | #define S3C64XX_SPCON_DRVCON_MODEM_7mA (0x2 << 22) |
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| 74 | #define S3C64XX_SPCON_DRVCON_MODEM_9mA (0x3 << 22) |
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| 75 | |
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| 76 | #define S3C64XX_SPCON_nRSTOUT_OEN (1 << 21) |
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| 77 | |
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| 78 | #define S3C64XX_SPCON_DRVCON_SPICLK1_MASK (0x3 << 18) |
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| 79 | #define S3C64XX_SPCON_DRVCON_SPICLK1_SHIFT (18) |
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| 80 | #define S3C64XX_SPCON_DRVCON_SPICLK1_2mA (0x0 << 18) |
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| 81 | #define S3C64XX_SPCON_DRVCON_SPICLK1_4mA (0x1 << 18) |
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| 82 | #define S3C64XX_SPCON_DRVCON_SPICLK1_7mA (0x2 << 18) |
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| 83 | #define S3C64XX_SPCON_DRVCON_SPICLK1_9mA (0x3 << 18) |
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| 84 | |
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| 85 | #define S3C64XX_SPCON_MEM1_DQS_PUD_MASK (0x3 << 16) |
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| 86 | #define S3C64XX_SPCON_MEM1_DQS_PUD_SHIFT (16) |
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| 87 | #define S3C64XX_SPCON_MEM1_DQS_PUD_DISABLED (0x0 << 16) |
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| 88 | #define S3C64XX_SPCON_MEM1_DQS_PUD_DOWN (0x1 << 16) |
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| 89 | #define S3C64XX_SPCON_MEM1_DQS_PUD_UP (0x2 << 16) |
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| 90 | |
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| 91 | #define S3C64XX_SPCON_MEM1_D_PUD1_MASK (0x3 << 14) |
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| 92 | #define S3C64XX_SPCON_MEM1_D_PUD1_SHIFT (14) |
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| 93 | #define S3C64XX_SPCON_MEM1_D_PUD1_DISABLED (0x0 << 14) |
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| 94 | #define S3C64XX_SPCON_MEM1_D_PUD1_DOWN (0x1 << 14) |
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| 95 | #define S3C64XX_SPCON_MEM1_D_PUD1_UP (0x2 << 14) |
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| 96 | |
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| 97 | #define S3C64XX_SPCON_MEM1_D_PUD0_MASK (0x3 << 12) |
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| 98 | #define S3C64XX_SPCON_MEM1_D_PUD0_SHIFT (12) |
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| 99 | #define S3C64XX_SPCON_MEM1_D_PUD0_DISABLED (0x0 << 12) |
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| 100 | #define S3C64XX_SPCON_MEM1_D_PUD0_DOWN (0x1 << 12) |
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| 101 | #define S3C64XX_SPCON_MEM1_D_PUD0_UP (0x2 << 12) |
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| 102 | |
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| 103 | #define S3C64XX_SPCON_MEM0_D_PUD_MASK (0x3 << 8) |
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| 104 | #define S3C64XX_SPCON_MEM0_D_PUD_SHIFT (8) |
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| 105 | #define S3C64XX_SPCON_MEM0_D_PUD_DISABLED (0x0 << 8) |
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| 106 | #define S3C64XX_SPCON_MEM0_D_PUD_DOWN (0x1 << 8) |
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| 107 | #define S3C64XX_SPCON_MEM0_D_PUD_UP (0x2 << 8) |
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| 108 | |
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| 109 | #define S3C64XX_SPCON_USBH_DMPD (1 << 7) |
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| 110 | #define S3C64XX_SPCON_USBH_DPPD (1 << 6) |
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| 111 | #define S3C64XX_SPCON_USBH_PUSW2 (1 << 5) |
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| 112 | #define S3C64XX_SPCON_USBH_PUSW1 (1 << 4) |
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| 113 | #define S3C64XX_SPCON_USBH_SUSPND (1 << 3) |
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| 114 | |
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| 115 | #define S3C64XX_SPCON_LCD_SEL_MASK (0x3 << 0) |
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| 116 | #define S3C64XX_SPCON_LCD_SEL_SHIFT (0) |
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| 117 | #define S3C64XX_SPCON_LCD_SEL_HOST (0x0 << 0) |
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| 118 | #define S3C64XX_SPCON_LCD_SEL_RGB (0x1 << 0) |
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| 119 | #define S3C64XX_SPCON_LCD_SEL_606_656 (0x2 << 0) |
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| 120 | |
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| 121 | |
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| 122 | /* External interrupt registers */ |
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| 123 | |
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| 124 | #define S3C64XX_EINT12CON S3C64XX_GPIOREG(0x200) |
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| 125 | #define S3C64XX_EINT34CON S3C64XX_GPIOREG(0x204) |
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| 126 | #define S3C64XX_EINT56CON S3C64XX_GPIOREG(0x208) |
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| 127 | #define S3C64XX_EINT78CON S3C64XX_GPIOREG(0x20C) |
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| 128 | #define S3C64XX_EINT9CON S3C64XX_GPIOREG(0x210) |
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| 129 | |
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| 130 | #define S3C64XX_EINT12FLTCON S3C64XX_GPIOREG(0x220) |
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| 131 | #define S3C64XX_EINT34FLTCON S3C64XX_GPIOREG(0x224) |
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| 132 | #define S3C64XX_EINT56FLTCON S3C64XX_GPIOREG(0x228) |
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| 133 | #define S3C64XX_EINT78FLTCON S3C64XX_GPIOREG(0x22C) |
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| 134 | #define S3C64XX_EINT9FLTCON S3C64XX_GPIOREG(0x230) |
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| 135 | |
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| 136 | #define S3C64XX_EINT12MASK S3C64XX_GPIOREG(0x240) |
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| 137 | #define S3C64XX_EINT34MASK S3C64XX_GPIOREG(0x244) |
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| 138 | #define S3C64XX_EINT56MASK S3C64XX_GPIOREG(0x248) |
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| 139 | #define S3C64XX_EINT78MASK S3C64XX_GPIOREG(0x24C) |
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| 140 | #define S3C64XX_EINT9MASK S3C64XX_GPIOREG(0x250) |
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| 141 | |
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| 142 | #define S3C64XX_EINT12PEND S3C64XX_GPIOREG(0x260) |
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| 143 | #define S3C64XX_EINT34PEND S3C64XX_GPIOREG(0x264) |
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| 144 | #define S3C64XX_EINT56PEND S3C64XX_GPIOREG(0x268) |
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| 145 | #define S3C64XX_EINT78PEND S3C64XX_GPIOREG(0x26C) |
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| 146 | #define S3C64XX_EINT9PEND S3C64XX_GPIOREG(0x270) |
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| 147 | |
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| 148 | #define S3C64XX_PRIORITY S3C64XX_GPIOREG(0x280) |
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| 149 | #define S3C64XX_PRIORITY_ARB(x) (1 << (x)) |
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| 150 | |
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| 151 | #define S3C64XX_SERVICE S3C64XX_GPIOREG(0x284) |
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| 152 | #define S3C64XX_SERVICEPEND S3C64XX_GPIOREG(0x288) |
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| 153 | |
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| 154 | #define S3C64XX_EINT0CON0 S3C64XX_GPIOREG(0x900) |
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| 155 | #define S3C64XX_EINT0CON1 S3C64XX_GPIOREG(0x904) |
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| 156 | #define S3C64XX_EINT0FLTCON0 S3C64XX_GPIOREG(0x910) |
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| 157 | #define S3C64XX_EINT0FLTCON1 S3C64XX_GPIOREG(0x914) |
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| 158 | #define S3C64XX_EINT0FLTCON2 S3C64XX_GPIOREG(0x918) |
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| 159 | #define S3C64XX_EINT0FLTCON3 S3C64XX_GPIOREG(0x91C) |
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| 160 | |
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| 161 | #define S3C64XX_EINT0MASK S3C64XX_GPIOREG(0x920) |
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| 162 | #define S3C64XX_EINT0PEND S3C64XX_GPIOREG(0x924) |
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| 163 | |
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| 164 | /* GPIO sleep configuration */ |
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| 165 | |
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| 166 | #define S3C64XX_SPCONSLP S3C64XX_GPIOREG(0x880) |
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| 167 | |
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| 168 | #define S3C64XX_SPCONSLP_TDO_PULLDOWN (1 << 14) |
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| 169 | #define S3C64XX_SPCONSLP_CKE1INIT (1 << 5) |
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| 170 | |
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| 171 | #define S3C64XX_SPCONSLP_RSTOUT_MASK (0x3 << 12) |
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| 172 | #define S3C64XX_SPCONSLP_RSTOUT_OUT0 (0x0 << 12) |
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| 173 | #define S3C64XX_SPCONSLP_RSTOUT_OUT1 (0x1 << 12) |
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| 174 | #define S3C64XX_SPCONSLP_RSTOUT_HIZ (0x2 << 12) |
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| 175 | |
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| 176 | #define S3C64XX_SPCONSLP_KPCOL_MASK (0x3 << 0) |
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| 177 | #define S3C64XX_SPCONSLP_KPCOL_OUT0 (0x0 << 0) |
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| 178 | #define S3C64XX_SPCONSLP_KPCOL_OUT1 (0x1 << 0) |
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| 179 | #define S3C64XX_SPCONSLP_KPCOL_INP (0x2 << 0) |
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| 180 | |
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| 181 | |
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| 182 | #define S3C64XX_SLPEN S3C64XX_GPIOREG(0x930) |
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| 183 | |
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| 184 | #define S3C64XX_SLPEN_USE_xSLP (1 << 0) |
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| 185 | #define S3C64XX_SLPEN_CFG_BYSLPEN (1 << 1) |
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| 186 | |
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| 187 | #endif /* __ASM_PLAT_S3C64XX_REGS_GPIO_H */ |
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| 188 | |
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| 189 | |
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