| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright 2008 Openmoko, Inc. |
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| 4 | * Copyright 2008 Simtec Electronics |
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| 5 | * http://armlinux.simtec.co.uk/ |
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| 6 | * Ben Dooks <ben@simtec.co.uk> |
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| 7 | * |
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| 8 | * S3C64XX - syscon power and sleep control registers |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef __MACH_S3C64XX_REGS_SYSCON_POWER_H |
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| 12 | #define __MACH_S3C64XX_REGS_SYSCON_POWER_H __FILE__ |
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| 13 | |
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| 14 | #define S3C64XX_PWR_CFG S3C_SYSREG(0x804) |
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| 15 | |
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| 16 | #define S3C64XX_PWRCFG_OSC_OTG_DISABLE (1 << 17) |
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| 17 | #define S3C64XX_PWRCFG_MMC2_DISABLE (1 << 16) |
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| 18 | #define S3C64XX_PWRCFG_MMC1_DISABLE (1 << 15) |
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| 19 | #define S3C64XX_PWRCFG_MMC0_DISABLE (1 << 14) |
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| 20 | #define S3C64XX_PWRCFG_HSI_DISABLE (1 << 13) |
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| 21 | #define S3C64XX_PWRCFG_TS_DISABLE (1 << 12) |
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| 22 | #define S3C64XX_PWRCFG_RTC_TICK_DISABLE (1 << 11) |
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| 23 | #define S3C64XX_PWRCFG_RTC_ALARM_DISABLE (1 << 10) |
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| 24 | #define S3C64XX_PWRCFG_MSM_DISABLE (1 << 9) |
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| 25 | #define S3C64XX_PWRCFG_KEY_DISABLE (1 << 8) |
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| 26 | #define S3C64XX_PWRCFG_BATF_DISABLE (1 << 7) |
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| 27 | |
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| 28 | #define S3C64XX_PWRCFG_CFG_WFI_MASK (0x3 << 5) |
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| 29 | #define S3C64XX_PWRCFG_CFG_WFI_SHIFT (5) |
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| 30 | #define S3C64XX_PWRCFG_CFG_WFI_IGNORE (0x0 << 5) |
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| 31 | #define S3C64XX_PWRCFG_CFG_WFI_IDLE (0x1 << 5) |
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| 32 | #define S3C64XX_PWRCFG_CFG_WFI_STOP (0x2 << 5) |
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| 33 | #define S3C64XX_PWRCFG_CFG_WFI_SLEEP (0x3 << 5) |
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| 34 | |
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| 35 | #define S3C64XX_PWRCFG_CFG_BATFLT_MASK (0x3 << 3) |
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| 36 | #define S3C64XX_PWRCFG_CFG_BATFLT_SHIFT (3) |
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| 37 | #define S3C64XX_PWRCFG_CFG_BATFLT_IGNORE (0x0 << 3) |
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| 38 | #define S3C64XX_PWRCFG_CFG_BATFLT_IRQ (0x1 << 3) |
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| 39 | #define S3C64XX_PWRCFG_CFG_BATFLT_SLEEP (0x3 << 3) |
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| 40 | |
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| 41 | #define S3C64XX_PWRCFG_CFG_BAT_WAKE (1 << 2) |
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| 42 | #define S3C64XX_PWRCFG_OSC27_EN (1 << 0) |
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| 43 | |
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| 44 | #define S3C64XX_EINT_MASK S3C_SYSREG(0x808) |
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| 45 | |
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| 46 | #define S3C64XX_NORMAL_CFG S3C_SYSREG(0x810) |
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| 47 | |
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| 48 | #define S3C64XX_NORMALCFG_IROM_ON (1 << 30) |
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| 49 | #define S3C64XX_NORMALCFG_DOMAIN_ETM_ON (1 << 16) |
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| 50 | #define S3C64XX_NORMALCFG_DOMAIN_S_ON (1 << 15) |
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| 51 | #define S3C64XX_NORMALCFG_DOMAIN_F_ON (1 << 14) |
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| 52 | #define S3C64XX_NORMALCFG_DOMAIN_P_ON (1 << 13) |
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| 53 | #define S3C64XX_NORMALCFG_DOMAIN_I_ON (1 << 12) |
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| 54 | #define S3C64XX_NORMALCFG_DOMAIN_G_ON (1 << 10) |
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| 55 | #define S3C64XX_NORMALCFG_DOMAIN_V_ON (1 << 9) |
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| 56 | |
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| 57 | #define S3C64XX_STOP_CFG S3C_SYSREG(0x814) |
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| 58 | |
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| 59 | #define S3C64XX_STOPCFG_MEMORY_ARM_ON (1 << 29) |
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| 60 | #define S3C64XX_STOPCFG_TOP_MEMORY_ON (1 << 20) |
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| 61 | #define S3C64XX_STOPCFG_ARM_LOGIC_ON (1 << 17) |
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| 62 | #define S3C64XX_STOPCFG_TOP_LOGIC_ON (1 << 8) |
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| 63 | #define S3C64XX_STOPCFG_OSC_EN (1 << 0) |
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| 64 | |
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| 65 | #define S3C64XX_SLEEP_CFG S3C_SYSREG(0x818) |
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| 66 | |
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| 67 | #define S3C64XX_SLEEPCFG_OSC_EN (1 << 0) |
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| 68 | |
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| 69 | #define S3C64XX_STOP_MEM_CFG S3C_SYSREG(0x81c) |
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| 70 | |
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| 71 | #define S3C64XX_STOPMEMCFG_MODEMIF_RETAIN (1 << 6) |
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| 72 | #define S3C64XX_STOPMEMCFG_HOSTIF_RETAIN (1 << 5) |
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| 73 | #define S3C64XX_STOPMEMCFG_OTG_RETAIN (1 << 4) |
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| 74 | #define S3C64XX_STOPMEMCFG_HSMCC_RETAIN (1 << 3) |
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| 75 | #define S3C64XX_STOPMEMCFG_IROM_RETAIN (1 << 2) |
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| 76 | #define S3C64XX_STOPMEMCFG_IRDA_RETAIN (1 << 1) |
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| 77 | #define S3C64XX_STOPMEMCFG_NFCON_RETAIN (1 << 0) |
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| 78 | |
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| 79 | #define S3C64XX_OSC_STABLE S3C_SYSREG(0x824) |
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| 80 | #define S3C64XX_PWR_STABLE S3C_SYSREG(0x828) |
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| 81 | |
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| 82 | #define S3C64XX_WAKEUP_STAT S3C_SYSREG(0x908) |
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| 83 | |
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| 84 | #define S3C64XX_WAKEUPSTAT_MMC2 (1 << 11) |
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| 85 | #define S3C64XX_WAKEUPSTAT_MMC1 (1 << 10) |
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| 86 | #define S3C64XX_WAKEUPSTAT_MMC0 (1 << 9) |
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| 87 | #define S3C64XX_WAKEUPSTAT_HSI (1 << 8) |
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| 88 | #define S3C64XX_WAKEUPSTAT_BATFLT (1 << 6) |
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| 89 | #define S3C64XX_WAKEUPSTAT_MSM (1 << 5) |
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| 90 | #define S3C64XX_WAKEUPSTAT_KEY (1 << 4) |
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| 91 | #define S3C64XX_WAKEUPSTAT_TS (1 << 3) |
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| 92 | #define S3C64XX_WAKEUPSTAT_RTC_TICK (1 << 2) |
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| 93 | #define S3C64XX_WAKEUPSTAT_RTC_ALARM (1 << 1) |
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| 94 | #define S3C64XX_WAKEUPSTAT_EINT (1 << 0) |
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| 95 | |
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| 96 | #define S3C64XX_BLK_PWR_STAT S3C_SYSREG(0x90c) |
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| 97 | |
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| 98 | #define S3C64XX_BLKPWRSTAT_G (1 << 7) |
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| 99 | #define S3C64XX_BLKPWRSTAT_ETM (1 << 6) |
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| 100 | #define S3C64XX_BLKPWRSTAT_S (1 << 5) |
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| 101 | #define S3C64XX_BLKPWRSTAT_F (1 << 4) |
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| 102 | #define S3C64XX_BLKPWRSTAT_P (1 << 3) |
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| 103 | #define S3C64XX_BLKPWRSTAT_I (1 << 2) |
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| 104 | #define S3C64XX_BLKPWRSTAT_V (1 << 1) |
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| 105 | #define S3C64XX_BLKPWRSTAT_TOP (1 << 0) |
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| 106 | |
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| 107 | #define S3C64XX_INFORM0 S3C_SYSREG(0xA00) |
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| 108 | #define S3C64XX_INFORM1 S3C_SYSREG(0xA04) |
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| 109 | #define S3C64XX_INFORM2 S3C_SYSREG(0xA08) |
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| 110 | #define S3C64XX_INFORM3 S3C_SYSREG(0xA0C) |
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| 111 | |
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| 112 | #endif /* __MACH_S3C64XX_REGS_SYSCON_POWER_H */ |
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| 113 | |
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