| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright 2008 Openmoko, Inc. |
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| 4 | * Copyright 2008 Simtec Electronics |
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| 5 | * http://armlinux.simtec.co.uk/ |
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| 6 | * Ben Dooks <ben@simtec.co.uk> |
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| 7 | * |
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| 8 | * S3C - USB2.0 Highspeed/OtG device PHY registers |
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| 9 | */ |
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| 10 | |
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| 11 | /* Note, this is a separate header file as some of the clock framework |
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| 12 | * needs to touch this if the clk_48m is used as the USB OHCI or other |
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| 13 | * peripheral source. |
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| 14 | */ |
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| 15 | |
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| 16 | #ifndef __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H |
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| 17 | #define __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H __FILE__ |
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| 18 | |
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| 19 | /* S3C64XX_PA_USB_HSPHY */ |
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| 20 | |
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| 21 | #define S3C_HSOTG_PHYREG(x) ((x) + S3C_VA_USB_HSPHY) |
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| 22 | |
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| 23 | #define S3C_PHYPWR S3C_HSOTG_PHYREG(0x00) |
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| 24 | #define S3C_PHYPWR_NORMAL_MASK (0x19 << 0) |
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| 25 | #define S3C_PHYPWR_OTG_DISABLE (1 << 4) |
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| 26 | #define S3C_PHYPWR_ANALOG_POWERDOWN (1 << 3) |
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| 27 | #define SRC_PHYPWR_FORCE_SUSPEND (1 << 1) |
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| 28 | |
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| 29 | #define S3C_PHYCLK S3C_HSOTG_PHYREG(0x04) |
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| 30 | #define S3C_PHYCLK_MODE_USB11 (1 << 6) |
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| 31 | #define S3C_PHYCLK_EXT_OSC (1 << 5) |
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| 32 | #define S3C_PHYCLK_CLK_FORCE (1 << 4) |
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| 33 | #define S3C_PHYCLK_ID_PULL (1 << 2) |
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| 34 | #define S3C_PHYCLK_CLKSEL_MASK (0x3 << 0) |
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| 35 | #define S3C_PHYCLK_CLKSEL_SHIFT (0) |
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| 36 | #define S3C_PHYCLK_CLKSEL_48M (0x0 << 0) |
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| 37 | #define S3C_PHYCLK_CLKSEL_12M (0x2 << 0) |
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| 38 | #define S3C_PHYCLK_CLKSEL_24M (0x3 << 0) |
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| 39 | |
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| 40 | #define S3C_RSTCON S3C_HSOTG_PHYREG(0x08) |
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| 41 | #define S3C_RSTCON_PHYCLK (1 << 2) |
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| 42 | #define S3C_RSTCON_HCLK (1 << 1) |
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| 43 | #define S3C_RSTCON_PHY (1 << 0) |
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| 44 | |
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| 45 | #define S3C_PHYTUNE S3C_HSOTG_PHYREG(0x20) |
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| 46 | |
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| 47 | #endif /* __PLAT_S3C64XX_REGS_USB_HSOTG_PHY_H */ |
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| 48 | |
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