| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* linux/arch/arm/plat-s3c64xx/sleep.S |
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| 3 | * |
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| 4 | * Copyright 2008 Openmoko, Inc. |
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| 5 | * Copyright 2008 Simtec Electronics |
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| 6 | * Ben Dooks <ben@simtec.co.uk> |
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| 7 | * http://armlinux.simtec.co.uk/ |
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| 8 | * |
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| 9 | * S3C64XX CPU sleep code |
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| 10 | */ |
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| 11 | |
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| 12 | #include <linux/linkage.h> |
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| 13 | #include <asm/assembler.h> |
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| 14 | #include "map.h" |
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| 15 | |
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| 16 | #undef S3C64XX_VA_GPIO |
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| 17 | #define S3C64XX_VA_GPIO (0x0) |
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| 18 | |
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| 19 | #include "regs-gpio.h" |
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| 20 | |
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| 21 | #define LL_UART (S3C_PA_UART + (0x400 * CONFIG_S3C_LOWLEVEL_UART_PORT)) |
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| 22 | |
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| 23 | .text |
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| 24 | |
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| 25 | /* Sleep magic, the word before the resume entry point so that the |
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| 26 | * bootloader can check for a resumeable image. */ |
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| 27 | |
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| 28 | .word 0x2bedf00d |
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| 29 | |
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| 30 | /* s3c_cpu_reusme |
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| 31 | * |
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| 32 | * This is the entry point, stored by whatever method the bootloader |
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| 33 | * requires to get the kernel runnign again. This code expects to be |
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| 34 | * entered with no caches live and the MMU disabled. It will then |
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| 35 | * restore the MMU and other basic CP registers saved and restart |
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| 36 | * the kernel C code to finish the resume code. |
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| 37 | */ |
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| 38 | |
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| 39 | ENTRY(s3c_cpu_resume) |
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| 40 | msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE |
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| 41 | ldr r2, =LL_UART /* for debug */ |
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| 42 | b cpu_resume |
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| 43 | |
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