| 1 | /* SPDX-License-Identifier: GPL-2.0+ |
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| 2 | * |
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| 3 | * Shared SCU setup for mach-shmobile |
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| 4 | * |
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| 5 | * Copyright (C) 2012 Bastian Hecht |
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| 6 | */ |
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| 7 | |
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| 8 | #include <linux/linkage.h> |
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| 9 | #include <linux/init.h> |
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| 10 | #include <asm/page.h> |
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| 11 | |
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| 12 | /* |
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| 13 | * Boot code for secondary CPUs. |
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| 14 | * |
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| 15 | * First we turn on L1 cache coherency for our CPU. Then we jump to |
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| 16 | * secondary_startup that invalidates the cache and hands over control |
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| 17 | * to the common ARM startup code. |
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| 18 | */ |
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| 19 | ENTRY(shmobile_boot_scu) |
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| 20 | @ r0 = SCU base address |
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| 21 | mrc p15, 0, r1, c0, c0, 5 @ read MPIDR |
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| 22 | and r1, r1, #3 @ mask out cpu ID |
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| 23 | lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits |
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| 24 | ldr r2, [r0, #8] @ SCU Power Status Register |
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| 25 | mov r3, #3 |
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| 26 | lsl r3, r3, r1 |
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| 27 | bic r2, r2, r3 @ Clear bits of our CPU (Run Mode) |
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| 28 | str r2, [r0, #8] @ write back |
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| 29 | |
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| 30 | b secondary_startup |
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| 31 | ENDPROC(shmobile_boot_scu) |
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| 32 | |
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