| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * The ARM LDRD and Thumb LDRSB instructions use bit 20/11 (ARM/Thumb) |
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| 4 | * differently than every other instruction, so it is set to 0 (write) |
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| 5 | * even though the instructions are read instructions. This means that |
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| 6 | * during an abort the instructions will be treated as a write and the |
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| 7 | * handler will raise a signal from unwriteable locations if they |
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| 8 | * fault. We have to specifically check for these instructions |
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| 9 | * from the abort handlers to treat them properly. |
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| 10 | * |
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| 11 | */ |
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| 12 | |
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| 13 | .macro do_thumb_abort, fsr, pc, psr, tmp |
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| 14 | tst \psr, #PSR_T_BIT |
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| 15 | beq not_thumb |
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| 16 | ldrh \tmp, [\pc] @ Read aborted Thumb instruction |
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| 17 | uaccess_disable ip @ disable userspace access |
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| 18 | and \tmp, \tmp, # 0xfe00 @ Mask opcode field |
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| 19 | cmp \tmp, # 0x5600 @ Is it ldrsb? |
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| 20 | orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes |
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| 21 | tst \tmp, #1 << 11 @ L = 0 -> write |
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| 22 | orreq \fsr, \fsr, #1 << 11 @ yes. |
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| 23 | b do_DataAbort |
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| 24 | not_thumb: |
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| 25 | .endm |
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| 26 | |
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| 27 | /* |
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| 28 | * We check for the following instruction encoding for LDRD. |
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| 29 | * |
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| 30 | * [27:25] == 000 |
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| 31 | * [7:4] == 1101 |
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| 32 | * [20] == 0 |
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| 33 | */ |
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| 34 | .macro teq_ldrd, tmp, insn |
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| 35 | mov \tmp, #0x0e100000 |
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| 36 | orr \tmp, #0x000000f0 |
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| 37 | and \tmp, \insn, \tmp |
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| 38 | teq \tmp, #0x000000d0 |
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| 39 | .endm |
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| 40 | |
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