| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Marvell Tauros3 cache controller includes |
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| 4 | * |
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| 5 | * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> |
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| 6 | * |
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| 7 | * based on GPL'ed 2.6 kernel sources |
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| 8 | * (c) Marvell International Ltd. |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef __ASM_ARM_HARDWARE_TAUROS3_H |
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| 12 | #define __ASM_ARM_HARDWARE_TAUROS3_H |
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| 13 | |
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| 14 | /* |
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| 15 | * Marvell Tauros3 L2CC is compatible with PL310 r0p0 |
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| 16 | * but with PREFETCH_CTRL (r2p0) and an additional event counter. |
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| 17 | * Also, there is AUX2_CTRL for some Marvell specific control. |
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| 18 | */ |
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| 19 | |
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| 20 | #define TAUROS3_EVENT_CNT2_CFG 0x224 |
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| 21 | #define TAUROS3_EVENT_CNT2_VAL 0x228 |
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| 22 | #define TAUROS3_INV_ALL 0x780 |
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| 23 | #define TAUROS3_CLEAN_ALL 0x784 |
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| 24 | #define TAUROS3_AUX2_CTRL 0x820 |
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| 25 | |
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| 26 | /* Registers shifts and masks */ |
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| 27 | #define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN (1 << 2) |
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| 28 | |
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| 29 | #endif |
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| 30 | |
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