1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Just-In-Time compiler for BPF filters on 32bit ARM |
4 | * |
5 | * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com> |
6 | */ |
7 | |
8 | #ifndef PFILTER_OPCODES_ARM_H |
9 | #define PFILTER_OPCODES_ARM_H |
10 | |
11 | /* ARM 32bit Registers */ |
12 | #define ARM_R0 0 |
13 | #define ARM_R1 1 |
14 | #define ARM_R2 2 |
15 | #define ARM_R3 3 |
16 | #define ARM_R4 4 |
17 | #define ARM_R5 5 |
18 | #define ARM_R6 6 |
19 | #define ARM_R7 7 |
20 | #define ARM_R8 8 |
21 | #define ARM_R9 9 |
22 | #define ARM_R10 10 |
23 | #define ARM_FP 11 /* Frame Pointer */ |
24 | #define ARM_IP 12 /* Intra-procedure scratch register */ |
25 | #define ARM_SP 13 /* Stack pointer: as load/store base reg */ |
26 | #define ARM_LR 14 /* Link Register */ |
27 | #define ARM_PC 15 /* Program counter */ |
28 | |
29 | #define ARM_COND_EQ 0x0 /* == */ |
30 | #define ARM_COND_NE 0x1 /* != */ |
31 | #define ARM_COND_CS 0x2 /* unsigned >= */ |
32 | #define ARM_COND_HS ARM_COND_CS |
33 | #define ARM_COND_CC 0x3 /* unsigned < */ |
34 | #define ARM_COND_LO ARM_COND_CC |
35 | #define ARM_COND_MI 0x4 /* < 0 */ |
36 | #define ARM_COND_PL 0x5 /* >= 0 */ |
37 | #define ARM_COND_VS 0x6 /* Signed Overflow */ |
38 | #define ARM_COND_VC 0x7 /* No Signed Overflow */ |
39 | #define ARM_COND_HI 0x8 /* unsigned > */ |
40 | #define ARM_COND_LS 0x9 /* unsigned <= */ |
41 | #define ARM_COND_GE 0xa /* Signed >= */ |
42 | #define ARM_COND_LT 0xb /* Signed < */ |
43 | #define ARM_COND_GT 0xc /* Signed > */ |
44 | #define ARM_COND_LE 0xd /* Signed <= */ |
45 | #define ARM_COND_AL 0xe /* None */ |
46 | |
47 | /* register shift types */ |
48 | #define SRTYPE_LSL 0 |
49 | #define SRTYPE_LSR 1 |
50 | #define SRTYPE_ASR 2 |
51 | #define SRTYPE_ROR 3 |
52 | #define SRTYPE_ASL (SRTYPE_LSL) |
53 | |
54 | #define ARM_INST_ADD_R 0x00800000 |
55 | #define ARM_INST_ADDS_R 0x00900000 |
56 | #define ARM_INST_ADC_R 0x00a00000 |
57 | #define ARM_INST_ADC_I 0x02a00000 |
58 | #define ARM_INST_ADD_I 0x02800000 |
59 | #define ARM_INST_ADDS_I 0x02900000 |
60 | |
61 | #define ARM_INST_AND_R 0x00000000 |
62 | #define ARM_INST_ANDS_R 0x00100000 |
63 | #define ARM_INST_AND_I 0x02000000 |
64 | |
65 | #define ARM_INST_BIC_R 0x01c00000 |
66 | #define ARM_INST_BIC_I 0x03c00000 |
67 | |
68 | #define ARM_INST_B 0x0a000000 |
69 | #define ARM_INST_BX 0x012FFF10 |
70 | #define ARM_INST_BLX_R 0x012fff30 |
71 | |
72 | #define ARM_INST_CMP_R 0x01500000 |
73 | #define ARM_INST_CMP_I 0x03500000 |
74 | |
75 | #define ARM_INST_EOR_R 0x00200000 |
76 | #define ARM_INST_EOR_I 0x02200000 |
77 | |
78 | #define ARM_INST_LDST__U 0x00800000 |
79 | #define ARM_INST_LDST__IMM12 0x00000fff |
80 | #define ARM_INST_LDRB_I 0x05500000 |
81 | #define ARM_INST_LDRB_R 0x07d00000 |
82 | #define ARM_INST_LDRSB_I 0x015000d0 |
83 | #define ARM_INST_LDRD_I 0x014000d0 |
84 | #define ARM_INST_LDRH_I 0x015000b0 |
85 | #define ARM_INST_LDRH_R 0x019000b0 |
86 | #define ARM_INST_LDRSH_I 0x015000f0 |
87 | #define ARM_INST_LDR_I 0x05100000 |
88 | #define ARM_INST_LDR_R 0x07900000 |
89 | |
90 | #define ARM_INST_LDM 0x08900000 |
91 | #define ARM_INST_LDM_IA 0x08b00000 |
92 | |
93 | #define ARM_INST_LSL_I 0x01a00000 |
94 | #define ARM_INST_LSL_R 0x01a00010 |
95 | |
96 | #define ARM_INST_LSR_I 0x01a00020 |
97 | #define ARM_INST_LSR_R 0x01a00030 |
98 | |
99 | #define ARM_INST_ASR_I 0x01a00040 |
100 | #define ARM_INST_ASR_R 0x01a00050 |
101 | |
102 | #define ARM_INST_MOV_R 0x01a00000 |
103 | #define ARM_INST_MOVS_R 0x01b00000 |
104 | #define ARM_INST_MOV_I 0x03a00000 |
105 | #define ARM_INST_MOVW 0x03000000 |
106 | #define ARM_INST_MOVT 0x03400000 |
107 | |
108 | #define ARM_INST_MUL 0x00000090 |
109 | |
110 | #define ARM_INST_POP 0x08bd0000 |
111 | #define ARM_INST_PUSH 0x092d0000 |
112 | |
113 | #define ARM_INST_ORR_R 0x01800000 |
114 | #define ARM_INST_ORRS_R 0x01900000 |
115 | #define ARM_INST_ORR_I 0x03800000 |
116 | |
117 | #define ARM_INST_REV 0x06bf0f30 |
118 | #define ARM_INST_REV16 0x06bf0fb0 |
119 | |
120 | #define ARM_INST_RSB_I 0x02600000 |
121 | #define ARM_INST_RSBS_I 0x02700000 |
122 | #define ARM_INST_RSC_I 0x02e00000 |
123 | |
124 | #define ARM_INST_SUB_R 0x00400000 |
125 | #define ARM_INST_SUBS_R 0x00500000 |
126 | #define ARM_INST_RSB_R 0x00600000 |
127 | #define ARM_INST_SUB_I 0x02400000 |
128 | #define ARM_INST_SUBS_I 0x02500000 |
129 | #define ARM_INST_SBC_I 0x02c00000 |
130 | #define ARM_INST_SBC_R 0x00c00000 |
131 | #define ARM_INST_SBCS_R 0x00d00000 |
132 | |
133 | #define ARM_INST_STR_I 0x05000000 |
134 | #define ARM_INST_STRB_I 0x05400000 |
135 | #define ARM_INST_STRD_I 0x014000f0 |
136 | #define ARM_INST_STRH_I 0x014000b0 |
137 | |
138 | #define ARM_INST_TST_R 0x01100000 |
139 | #define ARM_INST_TST_I 0x03100000 |
140 | |
141 | #define ARM_INST_UDIV 0x0730f010 |
142 | #define ARM_INST_SDIV 0x0710f010 |
143 | |
144 | #define ARM_INST_UMULL 0x00800090 |
145 | |
146 | #define ARM_INST_MLS 0x00600090 |
147 | |
148 | #define ARM_INST_UXTH 0x06ff0070 |
149 | |
150 | /* |
151 | * Use a suitable undefined instruction to use for ARM/Thumb2 faulting. |
152 | * We need to be careful not to conflict with those used by other modules |
153 | * (BUG, kprobes, etc) and the register_undef_hook() system. |
154 | * |
155 | * The ARM architecture reference manual guarantees that the following |
156 | * instruction space will produce an undefined instruction exception on |
157 | * all CPUs: |
158 | * |
159 | * ARM: xxxx 0111 1111 xxxx xxxx xxxx 1111 xxxx ARMv7-AR, section A5.4 |
160 | * Thumb: 1101 1110 xxxx xxxx ARMv7-M, section A5.2.6 |
161 | */ |
162 | #define ARM_INST_UDF 0xe7fddef1 |
163 | |
164 | /* register */ |
165 | #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) |
166 | /* immediate */ |
167 | #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) |
168 | /* register with register-shift */ |
169 | #define _AL3_SR(inst) (inst | (1 << 4)) |
170 | |
171 | #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) |
172 | #define ARM_ADDS_R(rd, rn, rm) _AL3_R(ARM_INST_ADDS, rd, rn, rm) |
173 | #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) |
174 | #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm) |
175 | #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) |
176 | #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) |
177 | |
178 | #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) |
179 | #define ARM_ANDS_R(rd, rn, rm) _AL3_R(ARM_INST_ANDS, rd, rn, rm) |
180 | #define ARM_AND_I(rd, rn, imm) _AL3_I(ARM_INST_AND, rd, rn, imm) |
181 | |
182 | #define ARM_BIC_R(rd, rn, rm) _AL3_R(ARM_INST_BIC, rd, rn, rm) |
183 | #define ARM_BIC_I(rd, rn, imm) _AL3_I(ARM_INST_BIC, rd, rn, imm) |
184 | |
185 | #define ARM_B(imm24) (ARM_INST_B | ((imm24) & 0xffffff)) |
186 | #define ARM_BX(rm) (ARM_INST_BX | (rm)) |
187 | #define ARM_BLX_R(rm) (ARM_INST_BLX_R | (rm)) |
188 | |
189 | #define ARM_CMP_R(rn, rm) _AL3_R(ARM_INST_CMP, 0, rn, rm) |
190 | #define ARM_CMP_I(rn, imm) _AL3_I(ARM_INST_CMP, 0, rn, imm) |
191 | |
192 | #define ARM_EOR_R(rd, rn, rm) _AL3_R(ARM_INST_EOR, rd, rn, rm) |
193 | #define ARM_EOR_I(rd, rn, imm) _AL3_I(ARM_INST_EOR, rd, rn, imm) |
194 | |
195 | #define ARM_LDR_R(rt, rn, rm) (ARM_INST_LDR_R | ARM_INST_LDST__U \ |
196 | | (rt) << 12 | (rn) << 16 \ |
197 | | (rm)) |
198 | #define ARM_LDR_R_SI(rt, rn, rm, type, imm) \ |
199 | (ARM_INST_LDR_R | ARM_INST_LDST__U \ |
200 | | (rt) << 12 | (rn) << 16 \ |
201 | | (imm) << 7 | (type) << 5 | (rm)) |
202 | #define ARM_LDRB_R(rt, rn, rm) (ARM_INST_LDRB_R | ARM_INST_LDST__U \ |
203 | | (rt) << 12 | (rn) << 16 \ |
204 | | (rm)) |
205 | #define ARM_LDRH_R(rt, rn, rm) (ARM_INST_LDRH_R | ARM_INST_LDST__U \ |
206 | | (rt) << 12 | (rn) << 16 \ |
207 | | (rm)) |
208 | |
209 | #define ARM_LDM(rn, regs) (ARM_INST_LDM | (rn) << 16 | (regs)) |
210 | #define ARM_LDM_IA(rn, regs) (ARM_INST_LDM_IA | (rn) << 16 | (regs)) |
211 | |
212 | #define ARM_LSL_R(rd, rn, rm) (_AL3_R(ARM_INST_LSL, rd, 0, rn) | (rm) << 8) |
213 | #define ARM_LSL_I(rd, rn, imm) (_AL3_I(ARM_INST_LSL, rd, 0, rn) | (imm) << 7) |
214 | |
215 | #define ARM_LSR_R(rd, rn, rm) (_AL3_R(ARM_INST_LSR, rd, 0, rn) | (rm) << 8) |
216 | #define ARM_LSR_I(rd, rn, imm) (_AL3_I(ARM_INST_LSR, rd, 0, rn) | (imm) << 7) |
217 | #define ARM_ASR_R(rd, rn, rm) (_AL3_R(ARM_INST_ASR, rd, 0, rn) | (rm) << 8) |
218 | #define ARM_ASR_I(rd, rn, imm) (_AL3_I(ARM_INST_ASR, rd, 0, rn) | (imm) << 7) |
219 | |
220 | #define ARM_MOV_R(rd, rm) _AL3_R(ARM_INST_MOV, rd, 0, rm) |
221 | #define ARM_MOVS_R(rd, rm) _AL3_R(ARM_INST_MOVS, rd, 0, rm) |
222 | #define ARM_MOV_I(rd, imm) _AL3_I(ARM_INST_MOV, rd, 0, imm) |
223 | #define ARM_MOV_SR(rd, rm, type, rs) \ |
224 | (_AL3_SR(ARM_MOV_R(rd, rm)) | (type) << 5 | (rs) << 8) |
225 | #define ARM_MOV_SI(rd, rm, type, imm6) \ |
226 | (ARM_MOV_R(rd, rm) | (type) << 5 | (imm6) << 7) |
227 | |
228 | #define ARM_MOVW(rd, imm) \ |
229 | (ARM_INST_MOVW | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff)) |
230 | |
231 | #define ARM_MOVT(rd, imm) \ |
232 | (ARM_INST_MOVT | ((imm) >> 12) << 16 | (rd) << 12 | ((imm) & 0x0fff)) |
233 | |
234 | #define ARM_MUL(rd, rm, rn) (ARM_INST_MUL | (rd) << 16 | (rm) << 8 | (rn)) |
235 | |
236 | #define ARM_POP(regs) (ARM_INST_POP | (regs)) |
237 | #define ARM_PUSH(regs) (ARM_INST_PUSH | (regs)) |
238 | |
239 | #define ARM_ORR_R(rd, rn, rm) _AL3_R(ARM_INST_ORR, rd, rn, rm) |
240 | #define ARM_ORR_I(rd, rn, imm) _AL3_I(ARM_INST_ORR, rd, rn, imm) |
241 | #define ARM_ORR_SR(rd, rn, rm, type, rs) \ |
242 | (_AL3_SR(ARM_ORR_R(rd, rn, rm)) | (type) << 5 | (rs) << 8) |
243 | #define ARM_ORRS_R(rd, rn, rm) _AL3_R(ARM_INST_ORRS, rd, rn, rm) |
244 | #define ARM_ORRS_SR(rd, rn, rm, type, rs) \ |
245 | (_AL3_SR(ARM_ORRS_R(rd, rn, rm)) | (type) << 5 | (rs) << 8) |
246 | #define ARM_ORR_SI(rd, rn, rm, type, imm6) \ |
247 | (ARM_ORR_R(rd, rn, rm) | (type) << 5 | (imm6) << 7) |
248 | #define ARM_ORRS_SI(rd, rn, rm, type, imm6) \ |
249 | (ARM_ORRS_R(rd, rn, rm) | (type) << 5 | (imm6) << 7) |
250 | |
251 | #define ARM_REV(rd, rm) (ARM_INST_REV | (rd) << 12 | (rm)) |
252 | #define ARM_REV16(rd, rm) (ARM_INST_REV16 | (rd) << 12 | (rm)) |
253 | |
254 | #define ARM_RSB_I(rd, rn, imm) _AL3_I(ARM_INST_RSB, rd, rn, imm) |
255 | #define ARM_RSBS_I(rd, rn, imm) _AL3_I(ARM_INST_RSBS, rd, rn, imm) |
256 | #define ARM_RSC_I(rd, rn, imm) _AL3_I(ARM_INST_RSC, rd, rn, imm) |
257 | |
258 | #define ARM_SUB_R(rd, rn, rm) _AL3_R(ARM_INST_SUB, rd, rn, rm) |
259 | #define ARM_SUBS_R(rd, rn, rm) _AL3_R(ARM_INST_SUBS, rd, rn, rm) |
260 | #define ARM_RSB_R(rd, rn, rm) _AL3_R(ARM_INST_RSB, rd, rn, rm) |
261 | #define ARM_SBC_R(rd, rn, rm) _AL3_R(ARM_INST_SBC, rd, rn, rm) |
262 | #define ARM_SBCS_R(rd, rn, rm) _AL3_R(ARM_INST_SBCS, rd, rn, rm) |
263 | #define ARM_SUB_I(rd, rn, imm) _AL3_I(ARM_INST_SUB, rd, rn, imm) |
264 | #define ARM_SUBS_I(rd, rn, imm) _AL3_I(ARM_INST_SUBS, rd, rn, imm) |
265 | #define ARM_SBC_I(rd, rn, imm) _AL3_I(ARM_INST_SBC, rd, rn, imm) |
266 | |
267 | #define ARM_TST_R(rn, rm) _AL3_R(ARM_INST_TST, 0, rn, rm) |
268 | #define ARM_TST_I(rn, imm) _AL3_I(ARM_INST_TST, 0, rn, imm) |
269 | |
270 | #define ARM_UDIV(rd, rn, rm) (ARM_INST_UDIV | (rd) << 16 | (rn) | (rm) << 8) |
271 | #define ARM_SDIV(rd, rn, rm) (ARM_INST_SDIV | (rd) << 16 | (rn) | (rm) << 8) |
272 | |
273 | #define ARM_UMULL(rd_lo, rd_hi, rn, rm) (ARM_INST_UMULL | (rd_hi) << 16 \ |
274 | | (rd_lo) << 12 | (rm) << 8 | rn) |
275 | |
276 | #define ARM_MLS(rd, rn, rm, ra) (ARM_INST_MLS | (rd) << 16 | (rn) | (rm) << 8 \ |
277 | | (ra) << 12) |
278 | #define ARM_UXTH(rd, rm) (ARM_INST_UXTH | (rd) << 12 | (rm)) |
279 | |
280 | #endif /* PFILTER_OPCODES_ARM_H */ |
281 | |