| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | NetWinder Floating Point Emulator |
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| 4 | (c) Rebel.com, 1998-1999 |
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| 5 | |
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| 6 | Direct questions, comments to Scott Bambrough <scottb@netwinder.org> |
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| 7 | |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef __FPSR_H__ |
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| 11 | #define __FPSR_H__ |
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| 12 | |
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| 13 | /* |
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| 14 | The FPSR is a 32 bit register consisting of 4 parts, each exactly |
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| 15 | one byte. |
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| 16 | |
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| 17 | SYSTEM ID |
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| 18 | EXCEPTION TRAP ENABLE BYTE |
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| 19 | SYSTEM CONTROL BYTE |
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| 20 | CUMULATIVE EXCEPTION FLAGS BYTE |
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| 21 | |
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| 22 | The FPCR is a 32 bit register consisting of bit flags. |
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| 23 | */ |
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| 24 | |
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| 25 | /* SYSTEM ID |
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| 26 | ------------ |
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| 27 | Note: the system id byte is read only */ |
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| 28 | |
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| 29 | typedef unsigned int FPSR; /* type for floating point status register */ |
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| 30 | typedef unsigned int FPCR; /* type for floating point control register */ |
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| 31 | |
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| 32 | #define MASK_SYSID 0xff000000 |
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| 33 | #define BIT_HARDWARE 0x80000000 |
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| 34 | #define FP_EMULATOR 0x01000000 /* System ID for emulator */ |
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| 35 | #define FP_ACCELERATOR 0x81000000 /* System ID for FPA11 */ |
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| 36 | |
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| 37 | /* EXCEPTION TRAP ENABLE BYTE |
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| 38 | ----------------------------- */ |
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| 39 | |
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| 40 | #define MASK_TRAP_ENABLE 0x00ff0000 |
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| 41 | #define MASK_TRAP_ENABLE_STRICT 0x001f0000 |
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| 42 | #define BIT_IXE 0x00100000 /* inexact exception enable */ |
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| 43 | #define BIT_UFE 0x00080000 /* underflow exception enable */ |
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| 44 | #define BIT_OFE 0x00040000 /* overflow exception enable */ |
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| 45 | #define BIT_DZE 0x00020000 /* divide by zero exception enable */ |
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| 46 | #define BIT_IOE 0x00010000 /* invalid operation exception enable */ |
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| 47 | |
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| 48 | /* SYSTEM CONTROL BYTE |
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| 49 | ---------------------- */ |
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| 50 | |
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| 51 | #define MASK_SYSTEM_CONTROL 0x0000ff00 |
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| 52 | #define MASK_TRAP_STRICT 0x00001f00 |
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| 53 | |
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| 54 | #define BIT_AC 0x00001000 /* use alternative C-flag definition |
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| 55 | for compares */ |
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| 56 | #define BIT_EP 0x00000800 /* use expanded packed decimal format */ |
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| 57 | #define BIT_SO 0x00000400 /* select synchronous operation of FPA */ |
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| 58 | #define BIT_NE 0x00000200 /* NaN exception bit */ |
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| 59 | #define BIT_ND 0x00000100 /* no denormalized numbers bit */ |
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| 60 | |
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| 61 | /* CUMULATIVE EXCEPTION FLAGS BYTE |
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| 62 | ---------------------------------- */ |
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| 63 | |
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| 64 | #define MASK_EXCEPTION_FLAGS 0x000000ff |
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| 65 | #define MASK_EXCEPTION_FLAGS_STRICT 0x0000001f |
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| 66 | |
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| 67 | #define BIT_IXC 0x00000010 /* inexact exception flag */ |
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| 68 | #define BIT_UFC 0x00000008 /* underflow exception flag */ |
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| 69 | #define BIT_OFC 0x00000004 /* overfloat exception flag */ |
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| 70 | #define BIT_DZC 0x00000002 /* divide by zero exception flag */ |
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| 71 | #define BIT_IOC 0x00000001 /* invalid operation exception flag */ |
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| 72 | |
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| 73 | /* Floating Point Control Register |
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| 74 | ----------------------------------*/ |
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| 75 | |
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| 76 | #define BIT_RU 0x80000000 /* rounded up bit */ |
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| 77 | #define BIT_IE 0x10000000 /* inexact bit */ |
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| 78 | #define BIT_MO 0x08000000 /* mantissa overflow bit */ |
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| 79 | #define BIT_EO 0x04000000 /* exponent overflow bit */ |
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| 80 | #define BIT_SB 0x00000800 /* store bounce */ |
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| 81 | #define BIT_AB 0x00000400 /* arithmetic bounce */ |
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| 82 | #define BIT_RE 0x00000200 /* rounding exception */ |
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| 83 | #define BIT_DA 0x00000100 /* disable FPA */ |
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| 84 | |
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| 85 | #define MASK_OP 0x00f08010 /* AU operation code */ |
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| 86 | #define MASK_PR 0x00080080 /* AU precision */ |
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| 87 | #define MASK_S1 0x00070000 /* AU source register 1 */ |
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| 88 | #define MASK_S2 0x00000007 /* AU source register 2 */ |
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| 89 | #define MASK_DS 0x00007000 /* AU destination register */ |
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| 90 | #define MASK_RM 0x00000060 /* AU rounding mode */ |
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| 91 | #define MASK_ALU 0x9cfff2ff /* only ALU can write these bits */ |
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| 92 | #define MASK_RESET 0x00000d00 /* bits set on reset, all others cleared */ |
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| 93 | #define MASK_WFC MASK_RESET |
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| 94 | #define MASK_RFC ~MASK_RESET |
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| 95 | |
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| 96 | #endif |
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| 97 | |
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