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| 1 | /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ |
|---|---|
| 2 | /* |
| 3 | * Copyright 2022 NXP |
| 4 | */ |
| 5 | |
| 6 | #ifndef __DTS_IMX93_PINFUNC_H |
| 7 | #define __DTS_IMX93_PINFUNC_H |
| 8 | |
| 9 | /* |
| 10 | * The pin function ID is a tuple of |
| 11 | * <mux_reg conf_reg input_reg mux_mode input_val> |
| 12 | */ |
| 13 | #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0 |
| 14 | #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0 |
| 15 | #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0 |
| 16 | #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0 |
| 17 | #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0 |
| 18 | #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0 |
| 19 | #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0 |
| 20 | #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0 |
| 21 | #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0 |
| 22 | #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0 |
| 23 | #define MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x01B8 0x03D4 0x0 0x0 |
| 24 | #define MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30 0x0008 0x01B8 0x0000 0x4 0x0 |
| 25 | #define MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30 0x0008 0x01B8 0x0000 0x5 0x0 |
| 26 | #define MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x01B8 0x042C 0x6 0x0 |
| 27 | #define MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x01BC 0x0000 0x0 0x0 |
| 28 | #define MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT 0x000C 0x01BC 0x0000 0x1 0x0 |
| 29 | #define MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x01BC 0x0364 0x3 0x0 |
| 30 | #define MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31 0x000C 0x01BC 0x0000 0x4 0x0 |
| 31 | #define MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31 0x000C 0x01BC 0x0000 0x5 0x0 |
| 32 | #define MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x01BC 0x0434 0x6 0x0 |
| 33 | #define MX93_PAD_GPIO_IO00__GPIO2_IO00 0x0010 0x01C0 0x0000 0x0 0x0 |
| 34 | #define MX93_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x01C0 0x03E4 0x11 0x0 |
| 35 | #define MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK 0x0010 0x01C0 0x0000 0x2 0x0 |
| 36 | #define MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x0010 0x01C0 0x0000 0x3 0x0 |
| 37 | #define MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x01C0 0x0000 0x4 0x0 |
| 38 | #define MX93_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x01C0 0x0434 0x5 0x1 |
| 39 | #define MX93_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x01C0 0x03EC 0x16 0x0 |
| 40 | #define MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00 0x0010 0x01C0 0x036C 0x7 0x0 |
| 41 | #define MX93_PAD_GPIO_IO01__GPIO2_IO01 0x0014 0x01C4 0x0000 0x0 0x0 |
| 42 | #define MX93_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x01C4 0x03E0 0x11 0x0 |
| 43 | #define MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00 0x0014 0x01C4 0x0000 0x2 0x0 |
| 44 | #define MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x0014 0x01C4 0x0000 0x3 0x0 |
| 45 | #define MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x01C4 0x0000 0x4 0x0 |
| 46 | #define MX93_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x01C4 0x0430 0x5 0x1 |
| 47 | #define MX93_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x01C4 0x03E8 0x16 0x0 |
| 48 | #define MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01 0x0014 0x01C4 0x0370 0x7 0x0 |
| 49 | #define MX93_PAD_GPIO_IO02__GPIO2_IO02 0x0018 0x01C8 0x0000 0x0 0x0 |
| 50 | #define MX93_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x01C8 0x0000 0x11 0x0 |
| 51 | #define MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC 0x0018 0x01C8 0x0000 0x2 0x0 |
| 52 | #define MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x0018 0x01C8 0x0000 0x3 0x0 |
| 53 | #define MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x01C8 0x0000 0x4 0x0 |
| 54 | #define MX93_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x01C8 0x042C 0x5 0x1 |
| 55 | #define MX93_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x01C8 0x03F4 0x16 0x0 |
| 56 | #define MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02 0x0018 0x01C8 0x0374 0x7 0x0 |
| 57 | #define MX93_PAD_GPIO_IO03__GPIO2_IO03 0x001C 0x01CC 0x0000 0x0 0x0 |
| 58 | #define MX93_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x01CC 0x0000 0x11 0x0 |
| 59 | #define MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC 0x001C 0x01CC 0x0000 0x2 0x0 |
| 60 | #define MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x001C 0x01CC 0x0000 0x3 0x0 |
| 61 | #define MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x01CC 0x0000 0x4 0x0 |
| 62 | #define MX93_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x01CC 0x0000 0x5 0x0 |
| 63 | #define MX93_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x01CC 0x03F0 0x16 0x0 |
| 64 | #define MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03 0x001C 0x01CC 0x0378 0x7 0x0 |
| 65 | #define MX93_PAD_GPIO_IO04__GPIO2_IO04 0x0020 0x01D0 0x0000 0x0 0x0 |
| 66 | #define MX93_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x01D0 0x0000 0x1 0x0 |
| 67 | #define MX93_PAD_GPIO_IO04__PDM_CLK 0x0020 0x01D0 0x0000 0x2 0x0 |
| 68 | #define MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x0020 0x01D0 0x0000 0x3 0x0 |
| 69 | #define MX93_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x01D0 0x0000 0x4 0x0 |
| 70 | #define MX93_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x01D0 0x0000 0x5 0x0 |
| 71 | #define MX93_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x01D0 0x03F4 0x16 0x1 |
| 72 | #define MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04 0x0020 0x01D0 0x037C 0x7 0x0 |
| 73 | #define MX93_PAD_GPIO_IO05__GPIO2_IO05 0x0024 0x01D4 0x0000 0x0 0x0 |
| 74 | #define MX93_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x01D4 0x0000 0x1 0x0 |
| 75 | #define MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00 0x0024 0x01D4 0x0438 0x2 0x0 |
| 76 | #define MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x0024 0x01D4 0x0000 0x3 0x0 |
| 77 | #define MX93_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x01D4 0x0000 0x4 0x0 |
| 78 | #define MX93_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x01D4 0x0000 0x5 0x0 |
| 79 | #define MX93_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x01D4 0x03F0 0x16 0x1 |
| 80 | #define MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05 0x0024 0x01D4 0x0380 0x7 0x0 |
| 81 | #define MX93_PAD_GPIO_IO06__GPIO2_IO06 0x0028 0x01D8 0x0000 0x0 0x0 |
| 82 | #define MX93_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x01D8 0x0000 0x1 0x0 |
| 83 | #define MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01 0x0028 0x01D8 0x043C 0x2 0x0 |
| 84 | #define MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x0028 0x01D8 0x0000 0x3 0x0 |
| 85 | #define MX93_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x01D8 0x0000 0x4 0x0 |
| 86 | #define MX93_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x01D8 0x0000 0x5 0x0 |
| 87 | #define MX93_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x01D8 0x03FC 0x16 0x0 |
| 88 | #define MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06 0x0028 0x01D8 0x0384 0x7 0x0 |
| 89 | #define MX93_PAD_GPIO_IO07__GPIO2_IO07 0x002C 0x01DC 0x0000 0x0 0x0 |
| 90 | #define MX93_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x01DC 0x0000 0x1 0x0 |
| 91 | #define MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01 0x002C 0x01DC 0x0000 0x2 0x0 |
| 92 | #define MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x002C 0x01DC 0x0000 0x3 0x0 |
| 93 | #define MX93_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x01DC 0x0000 0x4 0x0 |
| 94 | #define MX93_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x01DC 0x0000 0x5 0x0 |
| 95 | #define MX93_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x01DC 0x03F8 0x16 0x0 |
| 96 | #define MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07 0x002C 0x01DC 0x0388 0x7 0x0 |
| 97 | #define MX93_PAD_GPIO_IO08__GPIO2_IO08 0x0030 0x01E0 0x0000 0x0 0x0 |
| 98 | #define MX93_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x01E0 0x0000 0x1 0x0 |
| 99 | #define MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02 0x0030 0x01E0 0x0000 0x2 0x0 |
| 100 | #define MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x0030 0x01E0 0x0000 0x3 0x0 |
| 101 | #define MX93_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x01E0 0x0000 0x4 0x0 |
| 102 | #define MX93_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x01E0 0x0000 0x5 0x0 |
| 103 | #define MX93_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x01E0 0x03FC 0x16 0x1 |
| 104 | #define MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08 0x0030 0x01E0 0x038C 0x7 0x0 |
| 105 | #define MX93_PAD_GPIO_IO09__GPIO2_IO09 0x0034 0x01E4 0x0000 0x0 0x0 |
| 106 | #define MX93_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x01E4 0x0000 0x1 0x0 |
| 107 | #define MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03 0x0034 0x01E4 0x0000 0x2 0x0 |
| 108 | #define MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x0034 0x01E4 0x0000 0x3 0x0 |
| 109 | #define MX93_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x01E4 0x0000 0x4 0x0 |
| 110 | #define MX93_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x01E4 0x0000 0x5 0x0 |
| 111 | #define MX93_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x01E4 0x03F8 0x16 0x1 |
| 112 | #define MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09 0x0034 0x01E4 0x0390 0x7 0x0 |
| 113 | #define MX93_PAD_GPIO_IO10__GPIO2_IO10 0x0038 0x01E8 0x0000 0x0 0x0 |
| 114 | #define MX93_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x01E8 0x0000 0x1 0x0 |
| 115 | #define MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04 0x0038 0x01E8 0x0000 0x2 0x0 |
| 116 | #define MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x0038 0x01E8 0x0000 0x3 0x0 |
| 117 | #define MX93_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x01E8 0x0000 0x4 0x0 |
| 118 | #define MX93_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x01E8 0x0000 0x5 0x0 |
| 119 | #define MX93_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x01E8 0x0404 0x16 0x0 |
| 120 | #define MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10 0x0038 0x01E8 0x0394 0x7 0x0 |
| 121 | #define MX93_PAD_GPIO_IO11__GPIO2_IO11 0x003C 0x01EC 0x0000 0x0 0x0 |
| 122 | #define MX93_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x01EC 0x0000 0x1 0x0 |
| 123 | #define MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05 0x003C 0x01EC 0x0000 0x2 0x0 |
| 124 | #define MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x003C 0x01EC 0x0000 0x3 0x0 |
| 125 | #define MX93_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x01EC 0x0000 0x4 0x0 |
| 126 | #define MX93_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x01EC 0x0000 0x5 0x0 |
| 127 | #define MX93_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x01EC 0x0400 0x16 0x0 |
| 128 | #define MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11 0x003C 0x01EC 0x0398 0x7 0x0 |
| 129 | #define MX93_PAD_GPIO_IO12__GPIO2_IO12 0x0040 0x01F0 0x0000 0x0 0x0 |
| 130 | #define MX93_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x01F0 0x0000 0x1 0x0 |
| 131 | #define MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02 0x0040 0x01F0 0x0440 0x2 0x0 |
| 132 | #define MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x0040 0x01F0 0x0000 0x3 0x0 |
| 133 | #define MX93_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x01F0 0x0000 0x4 0x0 |
| 134 | #define MX93_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x01F0 0x0000 0x5 0x0 |
| 135 | #define MX93_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x01F0 0x0404 0x16 0x1 |
| 136 | #define MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x01F0 0x0450 0x7 0x0 |
| 137 | #define MX93_PAD_GPIO_IO13__GPIO2_IO13 0x0044 0x01F4 0x0000 0x0 0x0 |
| 138 | #define MX93_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x01F4 0x0000 0x1 0x0 |
| 139 | #define MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03 0x0044 0x01F4 0x0444 0x2 0x0 |
| 140 | #define MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x0044 0x01F4 0x0000 0x3 0x0 |
| 141 | #define MX93_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x01F4 0x0000 0x4 0x0 |
| 142 | #define MX93_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x01F4 0x0000 0x5 0x0 |
| 143 | #define MX93_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x01F4 0x0400 0x16 0x1 |
| 144 | #define MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13 0x0044 0x01F4 0x039C 0x7 0x0 |
| 145 | #define MX93_PAD_GPIO_IO14__GPIO2_IO14 0x0048 0x01F8 0x0000 0x0 0x0 |
| 146 | #define MX93_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x01F8 0x041C 0x1 0x0 |
| 147 | #define MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06 0x0048 0x01F8 0x0000 0x2 0x0 |
| 148 | #define MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x0048 0x01F8 0x0000 0x3 0x0 |
| 149 | #define MX93_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x01F8 0x0000 0x4 0x0 |
| 150 | #define MX93_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x01F8 0x0000 0x5 0x0 |
| 151 | #define MX93_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x01F8 0x0428 0x6 0x0 |
| 152 | #define MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14 0x0048 0x01F8 0x03A0 0x7 0x0 |
| 153 | #define MX93_PAD_GPIO_IO15__GPIO2_IO15 0x004C 0x01FC 0x0000 0x0 0x0 |
| 154 | #define MX93_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x01FC 0x0418 0x1 0x0 |
| 155 | #define MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07 0x004C 0x01FC 0x0000 0x2 0x0 |
| 156 | #define MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x004C 0x01FC 0x0000 0x3 0x0 |
| 157 | #define MX93_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x01FC 0x0000 0x4 0x0 |
| 158 | #define MX93_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x01FC 0x0000 0x5 0x0 |
| 159 | #define MX93_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x01FC 0x0424 0x6 0x0 |
| 160 | #define MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15 0x004C 0x01FC 0x03A4 0x7 0x0 |
| 161 | #define MX93_PAD_GPIO_IO16__GPIO2_IO16 0x0050 0x0200 0x0000 0x0 0x0 |
| 162 | #define MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0200 0x0000 0x1 0x0 |
| 163 | #define MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02 0x0050 0x0200 0x0440 0x2 0x1 |
| 164 | #define MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x0050 0x0200 0x0000 0x3 0x0 |
| 165 | #define MX93_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0200 0x0414 0x4 0x0 |
| 166 | #define MX93_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0200 0x0000 0x5 0x0 |
| 167 | #define MX93_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0200 0x0420 0x6 0x0 |
| 168 | #define MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16 0x0050 0x0200 0x03A8 0x7 0x0 |
| 169 | #define MX93_PAD_GPIO_IO17__GPIO2_IO17 0x0054 0x0204 0x0000 0x0 0x0 |
| 170 | #define MX93_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0204 0x0000 0x1 0x0 |
| 171 | #define MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08 0x0054 0x0204 0x0000 0x2 0x0 |
| 172 | #define MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x0054 0x0204 0x0000 0x3 0x0 |
| 173 | #define MX93_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0204 0x0000 0x4 0x0 |
| 174 | #define MX93_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0204 0x0000 0x5 0x0 |
| 175 | #define MX93_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0204 0x0000 0x6 0x0 |
| 176 | #define MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17 0x0054 0x0204 0x03AC 0x7 0x0 |
| 177 | #define MX93_PAD_GPIO_IO18__GPIO2_IO18 0x0058 0x0208 0x0000 0x0 0x0 |
| 178 | #define MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x0208 0x044C 0x1 0x0 |
| 179 | #define MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09 0x0058 0x0208 0x0000 0x2 0x0 |
| 180 | #define MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x0058 0x0208 0x0000 0x3 0x0 |
| 181 | #define MX93_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x0208 0x0000 0x4 0x0 |
| 182 | #define MX93_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x0208 0x0000 0x5 0x0 |
| 183 | #define MX93_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x0208 0x0000 0x6 0x0 |
| 184 | #define MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18 0x0058 0x0208 0x03B0 0x7 0x0 |
| 185 | #define MX93_PAD_GPIO_IO19__GPIO2_IO19 0x005C 0x020C 0x0000 0x0 0x0 |
| 186 | #define MX93_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x020C 0x0450 0x1 0x1 |
| 187 | #define MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03 0x005C 0x020C 0x0444 0x2 0x1 |
| 188 | #define MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x005C 0x020C 0x0000 0x3 0x0 |
| 189 | #define MX93_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x020C 0x0000 0x4 0x0 |
| 190 | #define MX93_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x020C 0x0000 0x5 0x0 |
| 191 | #define MX93_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x020C 0x0000 0x6 0x0 |
| 192 | #define MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x005C 0x020C 0x0000 0x7 0x0 |
| 193 | #define MX93_PAD_GPIO_IO20__GPIO2_IO20 0x0060 0x0210 0x0000 0x0 0x0 |
| 194 | #define MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x0060 0x0210 0x0000 0x1 0x0 |
| 195 | #define MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00 0x0060 0x0210 0x0438 0x2 0x1 |
| 196 | #define MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x0060 0x0210 0x0000 0x3 0x0 |
| 197 | #define MX93_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0210 0x0000 0x4 0x0 |
| 198 | #define MX93_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0210 0x0000 0x5 0x0 |
| 199 | #define MX93_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0210 0x0000 0x6 0x0 |
| 200 | #define MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20 0x0060 0x0210 0x03B4 0x7 0x0 |
| 201 | #define MX93_PAD_GPIO_IO21__GPIO2_IO21 0x0064 0x0214 0x0000 0x0 0x0 |
| 202 | #define MX93_PAD_GPIO_IO21__SAI3_TX_DATA00 0x0064 0x0214 0x0000 0x1 0x0 |
| 203 | #define MX93_PAD_GPIO_IO21__PDM_CLK 0x0064 0x0214 0x0000 0x2 0x0 |
| 204 | #define MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x0064 0x0214 0x0000 0x3 0x0 |
| 205 | #define MX93_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0214 0x0000 0x4 0x0 |
| 206 | #define MX93_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0214 0x0000 0x5 0x0 |
| 207 | #define MX93_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0214 0x0000 0x6 0x0 |
| 208 | #define MX93_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0214 0x044C 0x7 0x1 |
| 209 | #define MX93_PAD_GPIO_IO22__GPIO2_IO22 0x0068 0x0218 0x0000 0x0 0x0 |
| 210 | #define MX93_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x0218 0x0458 0x1 0x0 |
| 211 | #define MX93_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x0218 0x0454 0x2 0x0 |
| 212 | #define MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x0068 0x0218 0x0000 0x3 0x0 |
| 213 | #define MX93_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x0218 0x0000 0x4 0x0 |
| 214 | #define MX93_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x0218 0x0000 0x5 0x0 |
| 215 | #define MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x0218 0x03EC 0x16 0x1 |
| 216 | #define MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22 0x0068 0x0218 0x03B8 0x7 0x0 |
| 217 | #define MX93_PAD_GPIO_IO23__GPIO2_IO23 0x006C 0x021C 0x0000 0x0 0x0 |
| 218 | #define MX93_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x021C 0x045C 0x1 0x0 |
| 219 | #define MX93_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x021C 0x0000 0x2 0x0 |
| 220 | #define MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x006C 0x021C 0x0000 0x3 0x0 |
| 221 | #define MX93_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x021C 0x0000 0x4 0x0 |
| 222 | #define MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x021C 0x03E8 0x16 0x1 |
| 223 | #define MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23 0x006C 0x021C 0x03BC 0x7 0x0 |
| 224 | #define MX93_PAD_GPIO_IO24__GPIO2_IO24 0x0070 0x0220 0x0000 0x0 0x0 |
| 225 | #define MX93_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0220 0x0460 0x1 0x0 |
| 226 | #define MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x0070 0x0220 0x0000 0x3 0x0 |
| 227 | #define MX93_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0220 0x0000 0x4 0x0 |
| 228 | #define MX93_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0220 0x0000 0x5 0x0 |
| 229 | #define MX93_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0220 0x0000 0x6 0x0 |
| 230 | #define MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24 0x0070 0x0220 0x03C0 0x7 0x0 |
| 231 | #define MX93_PAD_GPIO_IO25__GPIO2_IO25 0x0074 0x0224 0x0000 0x0 0x0 |
| 232 | #define MX93_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0224 0x0464 0x1 0x0 |
| 233 | #define MX93_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0224 0x0000 0x2 0x0 |
| 234 | #define MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x0074 0x0224 0x0000 0x3 0x0 |
| 235 | #define MX93_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0224 0x0000 0x4 0x0 |
| 236 | #define MX93_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0224 0x03D4 0x5 0x1 |
| 237 | #define MX93_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0224 0x0000 0x6 0x0 |
| 238 | #define MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25 0x0074 0x0224 0x03C4 0x7 0x0 |
| 239 | #define MX93_PAD_GPIO_IO26__GPIO2_IO26 0x0078 0x0228 0x0000 0x0 0x0 |
| 240 | #define MX93_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x0228 0x0468 0x1 0x0 |
| 241 | #define MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01 0x0078 0x0228 0x043C 0x2 0x1 |
| 242 | #define MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x0078 0x0228 0x0000 0x3 0x0 |
| 243 | #define MX93_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x0228 0x0000 0x4 0x0 |
| 244 | #define MX93_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x0228 0x03D8 0x5 0x1 |
| 245 | #define MX93_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x0228 0x0000 0x6 0x0 |
| 246 | #define MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x0228 0x0000 0x7 0x0 |
| 247 | #define MX93_PAD_GPIO_IO27__GPIO2_IO27 0x007C 0x022C 0x0000 0x0 0x0 |
| 248 | #define MX93_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x022C 0x046C 0x1 0x0 |
| 249 | #define MX93_PAD_GPIO_IO27__CAN2_RX 0x007C 0x022C 0x0364 0x2 0x1 |
| 250 | #define MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x007C 0x022C 0x0000 0x3 0x0 |
| 251 | #define MX93_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x022C 0x0000 0x4 0x0 |
| 252 | #define MX93_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x022C 0x03DC 0x5 0x1 |
| 253 | #define MX93_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x022C 0x0000 0x6 0x0 |
| 254 | #define MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27 0x007C 0x022C 0x03C8 0x7 0x0 |
| 255 | #define MX93_PAD_GPIO_IO28__GPIO2_IO28 0x0080 0x0230 0x0000 0x0 0x0 |
| 256 | #define MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0230 0x03E4 0x11 0x1 |
| 257 | #define MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28 0x0080 0x0230 0x0000 0x7 0x0 |
| 258 | #define MX93_PAD_GPIO_IO29__GPIO2_IO29 0x0084 0x0234 0x0000 0x0 0x0 |
| 259 | #define MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0234 0x03E0 0x11 0x1 |
| 260 | #define MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29 0x0084 0x0234 0x0000 0x7 0x0 |
| 261 | #define MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1 0x0088 0x0238 0x0000 0x0 0x0 |
| 262 | #define MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26 0x0088 0x0238 0x0000 0x4 0x0 |
| 263 | #define MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x0088 0x0238 0x0000 0x5 0x0 |
| 264 | #define MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x008C 0x023C 0x0000 0x5 0x0 |
| 265 | #define MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2 0x008C 0x023C 0x0000 0x0 0x0 |
| 266 | #define MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27 0x008C 0x023C 0x03C8 0x4 0x1 |
| 267 | #define MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3 0x0090 0x0240 0x0000 0x0 0x0 |
| 268 | #define MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28 0x0090 0x0240 0x0000 0x4 0x0 |
| 269 | #define MX93_PAD_CCM_CLKO3__GPIO4_IO28 0x0090 0x0240 0x0000 0x5 0x0 |
| 270 | #define MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4 0x0094 0x0244 0x0000 0x0 0x0 |
| 271 | #define MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29 0x0094 0x0244 0x0000 0x4 0x0 |
| 272 | #define MX93_PAD_CCM_CLKO4__GPIO4_IO29 0x0094 0x0244 0x0000 0x5 0x0 |
| 273 | #define MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x0098 0x0248 0x0000 0x0 0x0 |
| 274 | #define MX93_PAD_ENET1_MDC__LPUART3_DCB_B 0x0098 0x0248 0x0000 0x1 0x0 |
| 275 | #define MX93_PAD_ENET1_MDC__I3C2_SCL 0x0098 0x0248 0x03CC 0x2 0x0 |
| 276 | #define MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1 0x0098 0x0248 0x0000 0x3 0x0 |
| 277 | #define MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00 0x0098 0x0248 0x0000 0x4 0x0 |
| 278 | #define MX93_PAD_ENET1_MDC__GPIO4_IO00 0x0098 0x0248 0x0000 0x5 0x0 |
| 279 | #define MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x009C 0x024C 0x0000 0x0 0x0 |
| 280 | #define MX93_PAD_ENET1_MDIO__LPUART3_RIN_B 0x009C 0x024C 0x0000 0x1 0x0 |
| 281 | #define MX93_PAD_ENET1_MDIO__I3C2_SDA 0x009C 0x024C 0x03D0 0x2 0x0 |
| 282 | #define MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1 0x009C 0x024C 0x0000 0x3 0x0 |
| 283 | #define MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01 0x009C 0x024C 0x0000 0x4 0x0 |
| 284 | #define MX93_PAD_ENET1_MDIO__GPIO4_IO01 0x009C 0x024C 0x0000 0x5 0x0 |
| 285 | #define MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x00A0 0x0250 0x0000 0x0 0x0 |
| 286 | #define MX93_PAD_ENET1_TD3__CAN2_TX 0x00A0 0x0250 0x0000 0x2 0x0 |
| 287 | #define MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2 0x00A0 0x0250 0x0000 0x3 0x0 |
| 288 | #define MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02 0x00A0 0x0250 0x0000 0x4 0x0 |
| 289 | #define MX93_PAD_ENET1_TD3__GPIO4_IO02 0x00A0 0x0250 0x0000 0x5 0x0 |
| 290 | #define MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x00A4 0x0254 0x0000 0x0 0x0 |
| 291 | #define MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x00A4 0x0254 0x0000 0x1 0x0 |
| 292 | #define MX93_PAD_ENET1_TD2__CAN2_RX 0x00A4 0x0254 0x0364 0x2 0x2 |
| 293 | #define MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2 0x00A4 0x0254 0x0000 0x3 0x0 |
| 294 | #define MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03 0x00A4 0x0254 0x0000 0x4 0x0 |
| 295 | #define MX93_PAD_ENET1_TD2__GPIO4_IO03 0x00A4 0x0254 0x0000 0x5 0x0 |
| 296 | #define MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x00A8 0x0258 0x0000 0x0 0x0 |
| 297 | #define MX93_PAD_ENET1_TD1__LPUART3_RTS_B 0x00A8 0x0258 0x0000 0x1 0x0 |
| 298 | #define MX93_PAD_ENET1_TD1__I3C2_PUR 0x00A8 0x0258 0x0000 0x2 0x0 |
| 299 | #define MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1 0x00A8 0x0258 0x0000 0x3 0x0 |
| 300 | #define MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04 0x00A8 0x0258 0x0000 0x4 0x0 |
| 301 | #define MX93_PAD_ENET1_TD1__GPIO4_IO04 0x00A8 0x0258 0x0000 0x5 0x0 |
| 302 | #define MX93_PAD_ENET1_TD1__I3C2_PUR_B 0x00A8 0x0258 0x0000 0x6 0x0 |
| 303 | #define MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x00AC 0x025C 0x0000 0x0 0x0 |
| 304 | #define MX93_PAD_ENET1_TD0__LPUART3_TX 0x00AC 0x025C 0x041C 0x1 0x1 |
| 305 | #define MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05 0x00AC 0x025C 0x0000 0x4 0x0 |
| 306 | #define MX93_PAD_ENET1_TD0__GPIO4_IO05 0x00AC 0x025C 0x0000 0x5 0x0 |
| 307 | #define MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x00B0 0x0260 0x0000 0x0 0x0 |
| 308 | #define MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00B0 0x0260 0x0000 0x1 0x0 |
| 309 | #define MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06 0x00B0 0x0260 0x0000 0x4 0x0 |
| 310 | #define MX93_PAD_ENET1_TX_CTL__GPIO4_IO06 0x00B0 0x0260 0x0000 0x5 0x0 |
| 311 | #define MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x00B4 0x0264 0x0000 0x0 0x0 |
| 312 | #define MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER 0x00B4 0x0264 0x0000 0x1 0x0 |
| 313 | #define MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07 0x00B4 0x0264 0x0000 0x4 0x0 |
| 314 | #define MX93_PAD_ENET1_TXC__GPIO4_IO07 0x00B4 0x0264 0x0000 0x5 0x0 |
| 315 | #define MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x00B8 0x0268 0x0000 0x0 0x0 |
| 316 | #define MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00B8 0x0268 0x0000 0x1 0x0 |
| 317 | #define MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2 0x00B8 0x0268 0x0000 0x3 0x0 |
| 318 | #define MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08 0x00B8 0x0268 0x0000 0x4 0x0 |
| 319 | #define MX93_PAD_ENET1_RX_CTL__GPIO4_IO08 0x00B8 0x0268 0x0000 0x5 0x0 |
| 320 | #define MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x00BC 0x026C 0x0000 0x0 0x0 |
| 321 | #define MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER 0x00BC 0x026C 0x0000 0x1 0x0 |
| 322 | #define MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09 0x00BC 0x026C 0x0000 0x4 0x0 |
| 323 | #define MX93_PAD_ENET1_RXC__GPIO4_IO09 0x00BC 0x026C 0x0000 0x5 0x0 |
| 324 | #define MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x00C0 0x0270 0x0000 0x0 0x0 |
| 325 | #define MX93_PAD_ENET1_RD0__LPUART3_RX 0x00C0 0x0270 0x0418 0x1 0x1 |
| 326 | #define MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10 0x00C0 0x0270 0x0000 0x4 0x0 |
| 327 | #define MX93_PAD_ENET1_RD0__GPIO4_IO10 0x00C0 0x0270 0x0000 0x5 0x0 |
| 328 | #define MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x00C4 0x0274 0x0000 0x0 0x0 |
| 329 | #define MX93_PAD_ENET1_RD1__LPUART3_CTS_B 0x00C4 0x0274 0x0414 0x1 0x1 |
| 330 | #define MX93_PAD_ENET1_RD1__LPTMR2_ALT1 0x00C4 0x0274 0x0408 0x3 0x0 |
| 331 | #define MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11 0x00C4 0x0274 0x0000 0x4 0x0 |
| 332 | #define MX93_PAD_ENET1_RD1__GPIO4_IO11 0x00C4 0x0274 0x0000 0x5 0x0 |
| 333 | #define MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x00C8 0x0278 0x0000 0x0 0x0 |
| 334 | #define MX93_PAD_ENET1_RD2__LPTMR2_ALT2 0x00C8 0x0278 0x040C 0x3 0x0 |
| 335 | #define MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12 0x00C8 0x0278 0x0000 0x4 0x0 |
| 336 | #define MX93_PAD_ENET1_RD2__GPIO4_IO12 0x00C8 0x0278 0x0000 0x5 0x0 |
| 337 | #define MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x00CC 0x027C 0x0000 0x0 0x0 |
| 338 | #define MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER 0x00CC 0x027C 0x0000 0x2 0x0 |
| 339 | #define MX93_PAD_ENET1_RD3__LPTMR2_ALT3 0x00CC 0x027C 0x0410 0x3 0x0 |
| 340 | #define MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13 0x00CC 0x027C 0x0000 0x4 0x0 |
| 341 | #define MX93_PAD_ENET1_RD3__GPIO4_IO13 0x00CC 0x027C 0x0000 0x5 0x0 |
| 342 | #define MX93_PAD_ENET2_MDC__ENET1_MDC 0x00D0 0x0280 0x0000 0x0 0x0 |
| 343 | #define MX93_PAD_ENET2_MDC__LPUART4_DCB_B 0x00D0 0x0280 0x0000 0x1 0x0 |
| 344 | #define MX93_PAD_ENET2_MDC__SAI2_RX_SYNC 0x00D0 0x0280 0x0000 0x2 0x0 |
| 345 | #define MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14 0x00D0 0x0280 0x0000 0x4 0x0 |
| 346 | #define MX93_PAD_ENET2_MDC__GPIO4_IO14 0x00D0 0x0280 0x0000 0x5 0x0 |
| 347 | #define MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x00D4 0x0284 0x0000 0x0 0x0 |
| 348 | #define MX93_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00D4 0x0284 0x0000 0x1 0x0 |
| 349 | #define MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK 0x00D4 0x0284 0x0000 0x2 0x0 |
| 350 | #define MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15 0x00D4 0x0284 0x0000 0x4 0x0 |
| 351 | #define MX93_PAD_ENET2_MDIO__GPIO4_IO15 0x00D4 0x0284 0x0000 0x5 0x0 |
| 352 | #define MX93_PAD_ENET2_TD3__SAI2_RX_DATA00 0x00D8 0x0288 0x0000 0x2 0x0 |
| 353 | #define MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16 0x00D8 0x0288 0x0000 0x4 0x0 |
| 354 | #define MX93_PAD_ENET2_TD3__GPIO4_IO16 0x00D8 0x0288 0x0000 0x5 0x0 |
| 355 | #define MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x00D8 0x0288 0x0000 0x0 0x0 |
| 356 | #define MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x00DC 0x028C 0x0000 0x0 0x0 |
| 357 | #define MX93_PAD_ENET2_TD2__ENET1_TX_CLK 0x00DC 0x028C 0x0000 0x1 0x0 |
| 358 | #define MX93_PAD_ENET2_TD2__SAI2_RX_DATA01 0x00DC 0x028C 0x0000 0x2 0x0 |
| 359 | #define MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17 0x00DC 0x028C 0x0000 0x4 0x0 |
| 360 | #define MX93_PAD_ENET2_TD2__GPIO4_IO17 0x00DC 0x028C 0x0000 0x5 0x0 |
| 361 | #define MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x00E0 0x0290 0x0000 0x0 0x0 |
| 362 | #define MX93_PAD_ENET2_TD1__LPUART4_RTS_B 0x00E0 0x0290 0x0000 0x1 0x0 |
| 363 | #define MX93_PAD_ENET2_TD1__SAI2_RX_DATA02 0x00E0 0x0290 0x0000 0x2 0x0 |
| 364 | #define MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18 0x00E0 0x0290 0x0000 0x4 0x0 |
| 365 | #define MX93_PAD_ENET2_TD1__GPIO4_IO18 0x00E0 0x0290 0x0000 0x5 0x0 |
| 366 | #define MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x00E4 0x0294 0x0000 0x0 0x0 |
| 367 | #define MX93_PAD_ENET2_TD0__LPUART4_TX 0x00E4 0x0294 0x0428 0x1 0x1 |
| 368 | #define MX93_PAD_ENET2_TD0__SAI2_RX_DATA03 0x00E4 0x0294 0x0000 0x2 0x0 |
| 369 | #define MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19 0x00E4 0x0294 0x0000 0x4 0x0 |
| 370 | #define MX93_PAD_ENET2_TD0__GPIO4_IO19 0x00E4 0x0294 0x0000 0x5 0x0 |
| 371 | #define MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x00E8 0x0298 0x0000 0x0 0x0 |
| 372 | #define MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x00E8 0x0298 0x0000 0x1 0x0 |
| 373 | #define MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC 0x00E8 0x0298 0x0000 0x2 0x0 |
| 374 | #define MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20 0x00E8 0x0298 0x0000 0x4 0x0 |
| 375 | #define MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x00E8 0x0298 0x0000 0x5 0x0 |
| 376 | #define MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x00EC 0x029C 0x0000 0x0 0x0 |
| 377 | #define MX93_PAD_ENET2_TXC__ENET1_TX_ER 0x00EC 0x029C 0x0000 0x1 0x0 |
| 378 | #define MX93_PAD_ENET2_TXC__SAI2_TX_BCLK 0x00EC 0x029C 0x0000 0x2 0x0 |
| 379 | #define MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21 0x00EC 0x029C 0x0000 0x4 0x0 |
| 380 | #define MX93_PAD_ENET2_TXC__GPIO4_IO21 0x00EC 0x029C 0x0000 0x5 0x0 |
| 381 | #define MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x00F0 0x02A0 0x0000 0x0 0x0 |
| 382 | #define MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x00F0 0x02A0 0x0000 0x1 0x0 |
| 383 | #define MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00 0x00F0 0x02A0 0x0000 0x2 0x0 |
| 384 | #define MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22 0x00F0 0x02A0 0x0000 0x4 0x0 |
| 385 | #define MX93_PAD_ENET2_RX_CTL__GPIO4_IO22 0x00F0 0x02A0 0x0000 0x5 0x0 |
| 386 | #define MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x00F4 0x02A4 0x0000 0x0 0x0 |
| 387 | #define MX93_PAD_ENET2_RXC__ENET1_RX_ER 0x00F4 0x02A4 0x0000 0x1 0x0 |
| 388 | #define MX93_PAD_ENET2_RXC__SAI2_TX_DATA01 0x00F4 0x02A4 0x0000 0x2 0x0 |
| 389 | #define MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23 0x00F4 0x02A4 0x0000 0x4 0x0 |
| 390 | #define MX93_PAD_ENET2_RXC__GPIO4_IO23 0x00F4 0x02A4 0x0000 0x5 0x0 |
| 391 | #define MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x00F8 0x02A8 0x0000 0x0 0x0 |
| 392 | #define MX93_PAD_ENET2_RD0__LPUART4_RX 0x00F8 0x02A8 0x0424 0x1 0x1 |
| 393 | #define MX93_PAD_ENET2_RD0__SAI2_TX_DATA02 0x00F8 0x02A8 0x0000 0x2 0x0 |
| 394 | #define MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24 0x00F8 0x02A8 0x0000 0x4 0x0 |
| 395 | #define MX93_PAD_ENET2_RD0__GPIO4_IO24 0x00F8 0x02A8 0x0000 0x5 0x0 |
| 396 | #define MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x00FC 0x02AC 0x0000 0x0 0x0 |
| 397 | #define MX93_PAD_ENET2_RD1__SPDIF_IN 0x00FC 0x02AC 0x0454 0x1 0x1 |
| 398 | #define MX93_PAD_ENET2_RD1__SAI2_TX_DATA03 0x00FC 0x02AC 0x0000 0x2 0x0 |
| 399 | #define MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25 0x00FC 0x02AC 0x0000 0x4 0x0 |
| 400 | #define MX93_PAD_ENET2_RD1__GPIO4_IO25 0x00FC 0x02AC 0x0000 0x5 0x0 |
| 401 | #define MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x0100 0x02B0 0x0000 0x0 0x0 |
| 402 | #define MX93_PAD_ENET2_RD2__LPUART4_CTS_B 0x0100 0x02B0 0x0420 0x1 0x1 |
| 403 | #define MX93_PAD_ENET2_RD2__SAI2_MCLK 0x0100 0x02B0 0x0000 0x2 0x0 |
| 404 | #define MX93_PAD_ENET2_RD2__MQS2_RIGHT 0x0100 0x02B0 0x0000 0x3 0x0 |
| 405 | #define MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26 0x0100 0x02B0 0x0000 0x4 0x0 |
| 406 | #define MX93_PAD_ENET2_RD2__GPIO4_IO26 0x0100 0x02B0 0x0000 0x5 0x0 |
| 407 | #define MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x0104 0x02B4 0x0000 0x0 0x0 |
| 408 | #define MX93_PAD_ENET2_RD3__SPDIF_OUT 0x0104 0x02B4 0x0000 0x1 0x0 |
| 409 | #define MX93_PAD_ENET2_RD3__SPDIF_IN 0x0104 0x02B4 0x0454 0x2 0x2 |
| 410 | #define MX93_PAD_ENET2_RD3__MQS2_LEFT 0x0104 0x02B4 0x0000 0x3 0x0 |
| 411 | #define MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27 0x0104 0x02B4 0x0000 0x4 0x0 |
| 412 | #define MX93_PAD_ENET2_RD3__GPIO4_IO27 0x0104 0x02B4 0x0000 0x5 0x0 |
| 413 | #define MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08 0x0108 0x02B8 0x038C 0x4 0x1 |
| 414 | #define MX93_PAD_SD1_CLK__GPIO3_IO08 0x0108 0x02B8 0x0000 0x5 0x0 |
| 415 | #define MX93_PAD_SD1_CLK__USDHC1_CLK 0x0108 0x02B8 0x0000 0x0 0x0 |
| 416 | #define MX93_PAD_SD1_CMD__USDHC1_CMD 0x010C 0x02BC 0x0000 0x0 0x0 |
| 417 | #define MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09 0x010C 0x02BC 0x0390 0x4 0x1 |
| 418 | #define MX93_PAD_SD1_CMD__GPIO3_IO09 0x010C 0x02BC 0x0000 0x5 0x0 |
| 419 | #define MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x0110 0x02C0 0x0000 0x0 0x0 |
| 420 | #define MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10 0x0110 0x02C0 0x0394 0x4 0x1 |
| 421 | #define MX93_PAD_SD1_DATA0__GPIO3_IO10 0x0110 0x02C0 0x0000 0x5 0x0 |
| 422 | #define MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x0114 0x02C4 0x0000 0x0 0x0 |
| 423 | #define MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11 0x0114 0x02C4 0x0398 0x4 0x1 |
| 424 | #define MX93_PAD_SD1_DATA1__GPIO3_IO11 0x0114 0x02C4 0x0000 0x5 0x0 |
| 425 | #define MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT 0x0114 0x02C4 0x0000 0x6 0x0 |
| 426 | #define MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x0118 0x02C8 0x0000 0x0 0x0 |
| 427 | #define MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12 0x0118 0x02C8 0x0000 0x4 0x0 |
| 428 | #define MX93_PAD_SD1_DATA2__GPIO3_IO12 0x0118 0x02C8 0x0000 0x5 0x0 |
| 429 | #define MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY 0x0118 0x02C8 0x0000 0x6 0x0 |
| 430 | #define MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x011C 0x02CC 0x0000 0x0 0x0 |
| 431 | #define MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x011C 0x02CC 0x0000 0x1 0x0 |
| 432 | #define MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13 0x011C 0x02CC 0x039C 0x4 0x1 |
| 433 | #define MX93_PAD_SD1_DATA3__GPIO3_IO13 0x011C 0x02CC 0x0000 0x5 0x0 |
| 434 | #define MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x0120 0x02D0 0x0000 0x0 0x0 |
| 435 | #define MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04 0x0120 0x02D0 0x0000 0x1 0x0 |
| 436 | #define MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14 0x0120 0x02D0 0x03A0 0x4 0x1 |
| 437 | #define MX93_PAD_SD1_DATA4__GPIO3_IO14 0x0120 0x02D0 0x0000 0x5 0x0 |
| 438 | #define MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x0124 0x02D4 0x0000 0x0 0x0 |
| 439 | #define MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05 0x0124 0x02D4 0x0000 0x1 0x0 |
| 440 | #define MX93_PAD_SD1_DATA5__USDHC1_RESET_B 0x0124 0x02D4 0x0000 0x2 0x0 |
| 441 | #define MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15 0x0124 0x02D4 0x03A4 0x4 0x1 |
| 442 | #define MX93_PAD_SD1_DATA5__GPIO3_IO15 0x0124 0x02D4 0x0000 0x5 0x0 |
| 443 | #define MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x0128 0x02D8 0x0000 0x0 0x0 |
| 444 | #define MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06 0x0128 0x02D8 0x0000 0x1 0x0 |
| 445 | #define MX93_PAD_SD1_DATA6__USDHC1_CD_B 0x0128 0x02D8 0x0000 0x2 0x0 |
| 446 | #define MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16 0x0128 0x02D8 0x03A8 0x4 0x1 |
| 447 | #define MX93_PAD_SD1_DATA6__GPIO3_IO16 0x0128 0x02D8 0x0000 0x5 0x0 |
| 448 | #define MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x012C 0x02DC 0x0000 0x0 0x0 |
| 449 | #define MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07 0x012C 0x02DC 0x0000 0x1 0x0 |
| 450 | #define MX93_PAD_SD1_DATA7__USDHC1_WP 0x012C 0x02DC 0x0000 0x2 0x0 |
| 451 | #define MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17 0x012C 0x02DC 0x03AC 0x4 0x1 |
| 452 | #define MX93_PAD_SD1_DATA7__GPIO3_IO17 0x012C 0x02DC 0x0000 0x5 0x0 |
| 453 | #define MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x0130 0x02E0 0x0000 0x0 0x0 |
| 454 | #define MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0130 0x02E0 0x0000 0x1 0x0 |
| 455 | #define MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18 0x0130 0x02E0 0x03B0 0x4 0x1 |
| 456 | #define MX93_PAD_SD1_STROBE__GPIO3_IO18 0x0130 0x02E0 0x0000 0x5 0x0 |
| 457 | #define MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0134 0x02E4 0x0000 0x0 0x0 |
| 458 | #define MX93_PAD_SD2_VSELECT__USDHC2_WP 0x0134 0x02E4 0x0000 0x1 0x0 |
| 459 | #define MX93_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0134 0x02E4 0x0410 0x2 0x1 |
| 460 | #define MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19 0x0134 0x02E4 0x0000 0x4 0x0 |
| 461 | #define MX93_PAD_SD2_VSELECT__GPIO3_IO19 0x0134 0x02E4 0x0000 0x5 0x0 |
| 462 | #define MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1 0x0134 0x02E4 0x0368 0x6 0x0 |
| 463 | #define MX93_PAD_SD3_CLK__USDHC3_CLK 0x0138 0x02E8 0x0458 0x0 0x1 |
| 464 | #define MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0138 0x02E8 0x0000 0x1 0x0 |
| 465 | #define MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20 0x0138 0x02E8 0x03B4 0x4 0x1 |
| 466 | #define MX93_PAD_SD3_CLK__GPIO3_IO20 0x0138 0x02E8 0x0000 0x5 0x0 |
| 467 | #define MX93_PAD_SD3_CMD__USDHC3_CMD 0x013C 0x02EC 0x045C 0x0 0x1 |
| 468 | #define MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x013C 0x02EC 0x0000 0x1 0x0 |
| 469 | #define MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21 0x013C 0x02EC 0x0000 0x4 0x0 |
| 470 | #define MX93_PAD_SD3_CMD__GPIO3_IO21 0x013C 0x02EC 0x0000 0x5 0x0 |
| 471 | #define MX93_PAD_SD3_DATA0__USDHC3_DATA0 0x0140 0x02F0 0x0460 0x0 0x1 |
| 472 | #define MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00 0x0140 0x02F0 0x0000 0x1 0x0 |
| 473 | #define MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22 0x0140 0x02F0 0x03B8 0x4 0x1 |
| 474 | #define MX93_PAD_SD3_DATA0__GPIO3_IO22 0x0140 0x02F0 0x0000 0x5 0x0 |
| 475 | #define MX93_PAD_SD3_DATA1__USDHC3_DATA1 0x0144 0x02F4 0x0464 0x0 0x1 |
| 476 | #define MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01 0x0144 0x02F4 0x0000 0x1 0x0 |
| 477 | #define MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23 0x0144 0x02F4 0x03BC 0x4 0x1 |
| 478 | #define MX93_PAD_SD3_DATA1__GPIO3_IO23 0x0144 0x02F4 0x0000 0x5 0x0 |
| 479 | #define MX93_PAD_SD3_DATA2__USDHC3_DATA2 0x0148 0x02F8 0x0468 0x0 0x1 |
| 480 | #define MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02 0x0148 0x02F8 0x0000 0x1 0x0 |
| 481 | #define MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24 0x0148 0x02F8 0x03C0 0x4 0x1 |
| 482 | #define MX93_PAD_SD3_DATA2__GPIO3_IO24 0x0148 0x02F8 0x0000 0x5 0x0 |
| 483 | #define MX93_PAD_SD3_DATA3__USDHC3_DATA3 0x014C 0x02FC 0x046C 0x0 0x1 |
| 484 | #define MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03 0x014C 0x02FC 0x0000 0x1 0x0 |
| 485 | #define MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25 0x014C 0x02FC 0x03C4 0x4 0x1 |
| 486 | #define MX93_PAD_SD3_DATA3__GPIO3_IO25 0x014C 0x02FC 0x0000 0x5 0x0 |
| 487 | #define MX93_PAD_SD2_CD_B__USDHC2_CD_B 0x0150 0x0300 0x0000 0x0 0x0 |
| 488 | #define MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN 0x0150 0x0300 0x0000 0x1 0x0 |
| 489 | #define MX93_PAD_SD2_CD_B__I3C2_SCL 0x0150 0x0300 0x03CC 0x2 0x1 |
| 490 | #define MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00 0x0150 0x0300 0x036C 0x4 0x1 |
| 491 | #define MX93_PAD_SD2_CD_B__GPIO3_IO00 0x0150 0x0300 0x0000 0x5 0x0 |
| 492 | #define MX93_PAD_SD2_CLK__USDHC2_CLK 0x0154 0x0304 0x0000 0x0 0x0 |
| 493 | #define MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT 0x0154 0x0304 0x0000 0x1 0x0 |
| 494 | #define MX93_PAD_SD2_CLK__I3C2_SDA 0x0154 0x0304 0x03D0 0x2 0x1 |
| 495 | #define MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01 0x0154 0x0304 0x0370 0x4 0x1 |
| 496 | #define MX93_PAD_SD2_CLK__GPIO3_IO01 0x0154 0x0304 0x0000 0x5 0x0 |
| 497 | #define MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0 0x0154 0x0304 0x0000 0x6 0x0 |
| 498 | #define MX93_PAD_SD2_CMD__USDHC2_CMD 0x0158 0x0308 0x0000 0x0 0x0 |
| 499 | #define MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN 0x0158 0x0308 0x0000 0x1 0x0 |
| 500 | #define MX93_PAD_SD2_CMD__I3C2_PUR 0x0158 0x0308 0x0000 0x2 0x0 |
| 501 | #define MX93_PAD_SD2_CMD__I3C2_PUR_B 0x0158 0x0308 0x0000 0x3 0x0 |
| 502 | #define MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02 0x0158 0x0308 0x0374 0x4 0x1 |
| 503 | #define MX93_PAD_SD2_CMD__GPIO3_IO02 0x0158 0x0308 0x0000 0x5 0x0 |
| 504 | #define MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1 0x0158 0x0308 0x0000 0x6 0x0 |
| 505 | #define MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x015C 0x030C 0x0000 0x0 0x0 |
| 506 | #define MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT 0x015C 0x030C 0x0000 0x1 0x0 |
| 507 | #define MX93_PAD_SD2_DATA0__CAN2_TX 0x015C 0x030C 0x0000 0x2 0x0 |
| 508 | #define MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03 0x015C 0x030C 0x0378 0x4 0x1 |
| 509 | #define MX93_PAD_SD2_DATA0__GPIO3_IO03 0x015C 0x030C 0x0000 0x5 0x0 |
| 510 | #define MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2 0x015C 0x030C 0x0000 0x6 0x0 |
| 511 | #define MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x0160 0x0310 0x0000 0x0 0x0 |
| 512 | #define MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN 0x0160 0x0310 0x0000 0x1 0x0 |
| 513 | #define MX93_PAD_SD2_DATA1__CAN2_RX 0x0160 0x0310 0x0364 0x2 0x3 |
| 514 | #define MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04 0x0160 0x0310 0x037C 0x4 0x1 |
| 515 | #define MX93_PAD_SD2_DATA1__GPIO3_IO04 0x0160 0x0310 0x0000 0x5 0x0 |
| 516 | #define MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT 0x0160 0x0310 0x0000 0x6 0x0 |
| 517 | #define MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x0164 0x0314 0x0000 0x0 0x0 |
| 518 | #define MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT 0x0164 0x0314 0x0000 0x1 0x0 |
| 519 | #define MX93_PAD_SD2_DATA2__MQS2_RIGHT 0x0164 0x0314 0x0000 0x2 0x0 |
| 520 | #define MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05 0x0164 0x0314 0x0380 0x4 0x1 |
| 521 | #define MX93_PAD_SD2_DATA2__GPIO3_IO05 0x0164 0x0314 0x0000 0x5 0x0 |
| 522 | #define MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP 0x0164 0x0314 0x0000 0x6 0x0 |
| 523 | #define MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x0168 0x0318 0x0000 0x0 0x0 |
| 524 | #define MX93_PAD_SD2_DATA3__LPTMR2_ALT1 0x0168 0x0318 0x0408 0x1 0x1 |
| 525 | #define MX93_PAD_SD2_DATA3__MQS2_LEFT 0x0168 0x0318 0x0000 0x2 0x0 |
| 526 | #define MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06 0x0168 0x0318 0x0384 0x4 0x1 |
| 527 | #define MX93_PAD_SD2_DATA3__GPIO3_IO06 0x0168 0x0318 0x0000 0x5 0x0 |
| 528 | #define MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET 0x0168 0x0318 0x0000 0x6 0x0 |
| 529 | #define MX93_PAD_SD2_RESET_B__USDHC2_RESET_B 0x016C 0x031C 0x0000 0x0 0x0 |
| 530 | #define MX93_PAD_SD2_RESET_B__LPTMR2_ALT2 0x016C 0x031C 0x040C 0x1 0x1 |
| 531 | #define MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07 0x016C 0x031C 0x0388 0x4 0x1 |
| 532 | #define MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x016C 0x031C 0x0000 0x5 0x0 |
| 533 | #define MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET 0x016C 0x031C 0x0000 0x6 0x0 |
| 534 | #define MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x0170 0x0320 0x0000 0x10 0x0 |
| 535 | #define MX93_PAD_I2C1_SCL__I3C1_SCL 0x0170 0x0320 0x0000 0x1 0x0 |
| 536 | #define MX93_PAD_I2C1_SCL__LPUART1_DCB_B 0x0170 0x0320 0x0000 0x2 0x0 |
| 537 | #define MX93_PAD_I2C1_SCL__TPM2_CH0 0x0170 0x0320 0x0000 0x3 0x0 |
| 538 | #define MX93_PAD_I2C1_SCL__GPIO1_IO00 0x0170 0x0320 0x0000 0x5 0x0 |
| 539 | #define MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x0174 0x0324 0x0000 0x10 0x0 |
| 540 | #define MX93_PAD_I2C1_SDA__I3C1_SDA 0x0174 0x0324 0x0000 0x1 0x0 |
| 541 | #define MX93_PAD_I2C1_SDA__LPUART1_RIN_B 0x0174 0x0324 0x0000 0x2 0x0 |
| 542 | #define MX93_PAD_I2C1_SDA__TPM2_CH1 0x0174 0x0324 0x0000 0x3 0x0 |
| 543 | #define MX93_PAD_I2C1_SDA__GPIO1_IO01 0x0174 0x0324 0x0000 0x5 0x0 |
| 544 | #define MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x0178 0x0328 0x0000 0x10 0x0 |
| 545 | #define MX93_PAD_I2C2_SCL__I3C1_PUR 0x0178 0x0328 0x0000 0x1 0x0 |
| 546 | #define MX93_PAD_I2C2_SCL__LPUART2_DCB_B 0x0178 0x0328 0x0000 0x2 0x0 |
| 547 | #define MX93_PAD_I2C2_SCL__TPM2_CH2 0x0178 0x0328 0x0000 0x3 0x0 |
| 548 | #define MX93_PAD_I2C2_SCL__SAI1_RX_SYNC 0x0178 0x0328 0x0000 0x4 0x0 |
| 549 | #define MX93_PAD_I2C2_SCL__GPIO1_IO02 0x0178 0x0328 0x0000 0x5 0x0 |
| 550 | #define MX93_PAD_I2C2_SCL__I3C1_PUR_B 0x0178 0x0328 0x0000 0x6 0x0 |
| 551 | #define MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x017C 0x032C 0x0000 0x10 0x0 |
| 552 | #define MX93_PAD_I2C2_SDA__LPUART2_RIN_B 0x017C 0x032C 0x0000 0x2 0x0 |
| 553 | #define MX93_PAD_I2C2_SDA__TPM2_CH3 0x017C 0x032C 0x0000 0x3 0x0 |
| 554 | #define MX93_PAD_I2C2_SDA__SAI1_RX_BCLK 0x017C 0x032C 0x0000 0x4 0x0 |
| 555 | #define MX93_PAD_I2C2_SDA__GPIO1_IO03 0x017C 0x032C 0x0000 0x5 0x0 |
| 556 | #define MX93_PAD_UART1_RXD__LPUART1_RX 0x0180 0x0330 0x0000 0x0 0x0 |
| 557 | #define MX93_PAD_UART1_RXD__S400_UART_RX 0x0180 0x0330 0x0000 0x1 0x0 |
| 558 | #define MX93_PAD_UART1_RXD__LPSPI2_SIN 0x0180 0x0330 0x0000 0x2 0x0 |
| 559 | #define MX93_PAD_UART1_RXD__TPM1_CH0 0x0180 0x0330 0x0000 0x3 0x0 |
| 560 | #define MX93_PAD_UART1_RXD__GPIO1_IO04 0x0180 0x0330 0x0000 0x5 0x0 |
| 561 | #define MX93_PAD_UART1_TXD__LPUART1_TX 0x0184 0x0334 0x0000 0x0 0x0 |
| 562 | #define MX93_PAD_UART1_TXD__S400_UART_TX 0x0184 0x0334 0x0000 0x1 0x0 |
| 563 | #define MX93_PAD_UART1_TXD__LPSPI2_PCS0 0x0184 0x0334 0x0000 0x2 0x0 |
| 564 | #define MX93_PAD_UART1_TXD__TPM1_CH1 0x0184 0x0334 0x0000 0x3 0x0 |
| 565 | #define MX93_PAD_UART1_TXD__GPIO1_IO05 0x0184 0x0334 0x0000 0x5 0x0 |
| 566 | #define MX93_PAD_UART2_RXD__LPUART2_RX 0x0188 0x0338 0x0000 0x0 0x0 |
| 567 | #define MX93_PAD_UART2_RXD__LPUART1_CTS_B 0x0188 0x0338 0x0000 0x1 0x0 |
| 568 | #define MX93_PAD_UART2_RXD__LPSPI2_SOUT 0x0188 0x0338 0x0000 0x2 0x0 |
| 569 | #define MX93_PAD_UART2_RXD__TPM1_CH2 0x0188 0x0338 0x0000 0x3 0x0 |
| 570 | #define MX93_PAD_UART2_RXD__SAI1_MCLK 0x0188 0x0338 0x0448 0x4 0x0 |
| 571 | #define MX93_PAD_UART2_RXD__GPIO1_IO06 0x0188 0x0338 0x0000 0x5 0x0 |
| 572 | #define MX93_PAD_UART2_TXD__LPUART2_TX 0x018C 0x033C 0x0000 0x0 0x0 |
| 573 | #define MX93_PAD_UART2_TXD__LPUART1_RTS_B 0x018C 0x033C 0x0000 0x1 0x0 |
| 574 | #define MX93_PAD_UART2_TXD__LPSPI2_SCK 0x018C 0x033C 0x0000 0x2 0x0 |
| 575 | #define MX93_PAD_UART2_TXD__TPM1_CH3 0x018C 0x033C 0x0000 0x3 0x0 |
| 576 | #define MX93_PAD_UART2_TXD__GPIO1_IO07 0x018C 0x033C 0x0000 0x5 0x0 |
| 577 | #define MX93_PAD_PDM_CLK__PDM_CLK 0x0190 0x0340 0x0000 0x0 0x0 |
| 578 | #define MX93_PAD_PDM_CLK__MQS1_LEFT 0x0190 0x0340 0x0000 0x1 0x0 |
| 579 | #define MX93_PAD_PDM_CLK__LPTMR1_ALT1 0x0190 0x0340 0x0000 0x4 0x0 |
| 580 | #define MX93_PAD_PDM_CLK__GPIO1_IO08 0x0190 0x0340 0x0000 0x5 0x0 |
| 581 | #define MX93_PAD_PDM_CLK__CAN1_TX 0x0190 0x0340 0x0000 0x6 0x0 |
| 582 | #define MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x0194 0x0344 0x0438 0x0 0x2 |
| 583 | #define MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT 0x0194 0x0344 0x0000 0x1 0x0 |
| 584 | #define MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1 0x0194 0x0344 0x0000 0x2 0x0 |
| 585 | #define MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK 0x0194 0x0344 0x0000 0x3 0x0 |
| 586 | #define MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2 0x0194 0x0344 0x0000 0x4 0x0 |
| 587 | #define MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09 0x0194 0x0344 0x0000 0x5 0x0 |
| 588 | #define MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x0194 0x0344 0x0360 0x6 0x0 |
| 589 | #define MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x0198 0x0348 0x043C 0x0 0x2 |
| 590 | #define MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x0198 0x0348 0x0000 0x1 0x0 |
| 591 | #define MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1 0x0198 0x0348 0x0000 0x2 0x0 |
| 592 | #define MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK 0x0198 0x0348 0x0000 0x3 0x0 |
| 593 | #define MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3 0x0198 0x0348 0x0000 0x4 0x0 |
| 594 | #define MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x0198 0x0348 0x0000 0x5 0x0 |
| 595 | #define MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1 0x0198 0x0348 0x0368 0x6 0x1 |
| 596 | #define MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x019C 0x034C 0x0000 0x0 0x0 |
| 597 | #define MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01 0x019C 0x034C 0x0000 0x1 0x0 |
| 598 | #define MX93_PAD_SAI1_TXFS__LPSPI1_PCS0 0x019C 0x034C 0x0000 0x2 0x0 |
| 599 | #define MX93_PAD_SAI1_TXFS__LPUART2_DTR_B 0x019C 0x034C 0x0000 0x3 0x0 |
| 600 | #define MX93_PAD_SAI1_TXFS__MQS1_LEFT 0x019C 0x034C 0x0000 0x4 0x0 |
| 601 | #define MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x019C 0x034C 0x0000 0x5 0x0 |
| 602 | #define MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x01A0 0x0350 0x0000 0x0 0x0 |
| 603 | #define MX93_PAD_SAI1_TXC__LPUART2_CTS_B 0x01A0 0x0350 0x0000 0x1 0x0 |
| 604 | #define MX93_PAD_SAI1_TXC__LPSPI1_SIN 0x01A0 0x0350 0x0000 0x2 0x0 |
| 605 | #define MX93_PAD_SAI1_TXC__LPUART1_DSR_B 0x01A0 0x0350 0x0000 0x3 0x0 |
| 606 | #define MX93_PAD_SAI1_TXC__CAN1_RX 0x01A0 0x0350 0x0360 0x4 0x1 |
| 607 | #define MX93_PAD_SAI1_TXC__GPIO1_IO12 0x01A0 0x0350 0x0000 0x5 0x0 |
| 608 | #define MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x01A4 0x0354 0x0000 0x0 0x0 |
| 609 | #define MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x01A4 0x0354 0x0000 0x1 0x0 |
| 610 | #define MX93_PAD_SAI1_TXD0__LPSPI1_SCK 0x01A4 0x0354 0x0000 0x2 0x0 |
| 611 | #define MX93_PAD_SAI1_TXD0__LPUART1_DTR_B 0x01A4 0x0354 0x0000 0x3 0x0 |
| 612 | #define MX93_PAD_SAI1_TXD0__CAN1_TX 0x01A4 0x0354 0x0000 0x4 0x0 |
| 613 | #define MX93_PAD_SAI1_TXD0__GPIO1_IO13 0x01A4 0x0354 0x0000 0x5 0x0 |
| 614 | #define MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x01A8 0x0358 0x0000 0x0 0x0 |
| 615 | #define MX93_PAD_SAI1_RXD0__SAI1_MCLK 0x01A8 0x0358 0x0448 0x1 0x1 |
| 616 | #define MX93_PAD_SAI1_RXD0__LPSPI1_SOUT 0x01A8 0x0358 0x0000 0x2 0x0 |
| 617 | #define MX93_PAD_SAI1_RXD0__LPUART2_DSR_B 0x01A8 0x0358 0x0000 0x3 0x0 |
| 618 | #define MX93_PAD_SAI1_RXD0__MQS1_RIGHT 0x01A8 0x0358 0x0000 0x4 0x0 |
| 619 | #define MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x01A8 0x0358 0x0000 0x5 0x0 |
| 620 | #define MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY 0x01AC 0x035C 0x0000 0x0 0x0 |
| 621 | #define MX93_PAD_WDOG_ANY__GPIO1_IO15 0x01AC 0x035C 0x0000 0x5 0x0 |
| 622 | |
| 623 | #endif /* __DTS_IMX93_PINFUNC_H */ |
| 624 |
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