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1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
---|---|
2 | /* |
3 | * Macros for accessing system registers with older binutils. |
4 | * |
5 | * Copyright (C) 2014 ARM Ltd. |
6 | * Author: Catalin Marinas <catalin.marinas@arm.com> |
7 | */ |
8 | |
9 | #ifndef __ASM_SYSREG_H |
10 | #define __ASM_SYSREG_H |
11 | |
12 | #include <linux/bits.h> |
13 | #include <linux/stringify.h> |
14 | #include <linux/kasan-tags.h> |
15 | #include <linux/kconfig.h> |
16 | |
17 | #include <asm/gpr-num.h> |
18 | |
19 | /* |
20 | * ARMv8 ARM reserves the following encoding for system registers: |
21 | * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", |
22 | * C5.2, version:ARM DDI 0487A.f) |
23 | * [20-19] : Op0 |
24 | * [18-16] : Op1 |
25 | * [15-12] : CRn |
26 | * [11-8] : CRm |
27 | * [7-5] : Op2 |
28 | */ |
29 | #define Op0_shift 19 |
30 | #define Op0_mask 0x3 |
31 | #define Op1_shift 16 |
32 | #define Op1_mask 0x7 |
33 | #define CRn_shift 12 |
34 | #define CRn_mask 0xf |
35 | #define CRm_shift 8 |
36 | #define CRm_mask 0xf |
37 | #define Op2_shift 5 |
38 | #define Op2_mask 0x7 |
39 | |
40 | #define sys_reg(op0, op1, crn, crm, op2) \ |
41 | (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ |
42 | ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ |
43 | ((op2) << Op2_shift)) |
44 | |
45 | #define sys_insn sys_reg |
46 | |
47 | #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) |
48 | #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) |
49 | #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) |
50 | #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) |
51 | #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) |
52 | |
53 | #ifndef CONFIG_BROKEN_GAS_INST |
54 | |
55 | #ifdef __ASSEMBLY__ |
56 | // The space separator is omitted so that __emit_inst(x) can be parsed as |
57 | // either an assembler directive or an assembler macro argument. |
58 | #define __emit_inst(x) .inst(x) |
59 | #else |
60 | #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" |
61 | #endif |
62 | |
63 | #else /* CONFIG_BROKEN_GAS_INST */ |
64 | |
65 | #ifndef CONFIG_CPU_BIG_ENDIAN |
66 | #define __INSTR_BSWAP(x) (x) |
67 | #else /* CONFIG_CPU_BIG_ENDIAN */ |
68 | #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \ |
69 | (((x) << 8) & 0x00ff0000) | \ |
70 | (((x) >> 8) & 0x0000ff00) | \ |
71 | (((x) >> 24) & 0x000000ff)) |
72 | #endif /* CONFIG_CPU_BIG_ENDIAN */ |
73 | |
74 | #ifdef __ASSEMBLY__ |
75 | #define __emit_inst(x) .long __INSTR_BSWAP(x) |
76 | #else /* __ASSEMBLY__ */ |
77 | #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t" |
78 | #endif /* __ASSEMBLY__ */ |
79 | |
80 | #endif /* CONFIG_BROKEN_GAS_INST */ |
81 | |
82 | /* |
83 | * Instructions for modifying PSTATE fields. |
84 | * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, |
85 | * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions |
86 | * for accessing PSTATE fields have the following encoding: |
87 | * Op0 = 0, CRn = 4 |
88 | * Op1, Op2 encodes the PSTATE field modified and defines the constraints. |
89 | * CRm = Imm4 for the instruction. |
90 | * Rt = 0x1f |
91 | */ |
92 | #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) |
93 | #define PSTATE_Imm_shift CRm_shift |
94 | #define SET_PSTATE(x, r) __emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift)) |
95 | |
96 | #define PSTATE_PAN pstate_field(0, 4) |
97 | #define PSTATE_UAO pstate_field(0, 3) |
98 | #define PSTATE_SSBS pstate_field(3, 1) |
99 | #define PSTATE_DIT pstate_field(3, 2) |
100 | #define PSTATE_TCO pstate_field(3, 4) |
101 | |
102 | #define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN) |
103 | #define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO) |
104 | #define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS) |
105 | #define SET_PSTATE_DIT(x) SET_PSTATE((x), DIT) |
106 | #define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO) |
107 | |
108 | #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) |
109 | #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) |
110 | #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) |
111 | #define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x)) |
112 | |
113 | /* Register-based PAN access, for save/restore purposes */ |
114 | #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3) |
115 | |
116 | #define __SYS_BARRIER_INSN(CRm, op2, Rt) \ |
117 | __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f)) |
118 | |
119 | #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31) |
120 | |
121 | /* Data cache zero operations */ |
122 | #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) |
123 | #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4) |
124 | #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6) |
125 | #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) |
126 | #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4) |
127 | #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6) |
128 | #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) |
129 | #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4) |
130 | #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6) |
131 | |
132 | #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0) |
133 | #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0) |
134 | #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1) |
135 | |
136 | #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1) |
137 | #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3) |
138 | #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5) |
139 | |
140 | #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1) |
141 | #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3) |
142 | #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5) |
143 | |
144 | #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1) |
145 | |
146 | #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1) |
147 | #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3) |
148 | #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5) |
149 | |
150 | #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1) |
151 | #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3) |
152 | #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5) |
153 | |
154 | #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1) |
155 | #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3) |
156 | #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5) |
157 | |
158 | #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1) |
159 | #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3) |
160 | #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4) |
161 | |
162 | #define SYS_DC_CIVAPS sys_insn(1, 0, 7, 15, 1) |
163 | #define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5) |
164 | |
165 | /* |
166 | * Automatically generated definitions for system registers, the |
167 | * manual encodings below are in the process of being converted to |
168 | * come from here. The header relies on the definition of sys_reg() |
169 | * earlier in this file. |
170 | */ |
171 | #include "asm/sysreg-defs.h" |
172 | |
173 | /* |
174 | * System registers, organised loosely by encoding but grouped together |
175 | * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. |
176 | */ |
177 | #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3) |
178 | #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3) |
179 | #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) |
180 | |
181 | #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) |
182 | #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) |
183 | #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) |
184 | #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) |
185 | #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) |
186 | |
187 | #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) |
188 | #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0)) |
189 | #define OSLSR_EL1_OSLM_NI 0 |
190 | #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3) |
191 | #define OSLSR_EL1_OSLK BIT(1) |
192 | |
193 | #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) |
194 | #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) |
195 | #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) |
196 | #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) |
197 | #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) |
198 | #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) |
199 | #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) |
200 | #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) |
201 | #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) |
202 | #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) |
203 | |
204 | #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0)) |
205 | #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0) |
206 | #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1)) |
207 | #define SYS_BRBSRCINJ_EL1 sys_reg(2, 1, 9, 1, 1) |
208 | #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2)) |
209 | #define SYS_BRBTGTINJ_EL1 sys_reg(2, 1, 9, 1, 2) |
210 | #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2) |
211 | |
212 | #define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0) |
213 | #define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1) |
214 | #define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0) |
215 | |
216 | #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3) |
217 | #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3))) |
218 | #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3))) |
219 | #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6) |
220 | #define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0) |
221 | #define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0) |
222 | #define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0) |
223 | #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2) |
224 | #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2) |
225 | #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0) |
226 | #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6) |
227 | #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6) |
228 | #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5) |
229 | #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5) |
230 | #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5) |
231 | #define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0) |
232 | #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6) |
233 | #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7) |
234 | #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0) |
235 | #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0) |
236 | #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4) |
237 | #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7) |
238 | #define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6) |
239 | #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6) |
240 | #define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6) |
241 | #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6) |
242 | #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7) |
243 | #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7) |
244 | #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7) |
245 | #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7) |
246 | #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7) |
247 | #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7) |
248 | #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7) |
249 | #define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6) |
250 | #define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6) |
251 | #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7) |
252 | #define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1) |
253 | #define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4) |
254 | #define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0) |
255 | #define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1) |
256 | #define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4))) |
257 | #define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0) |
258 | #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4) |
259 | #define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4) |
260 | #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4) |
261 | #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2) |
262 | #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2) |
263 | #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3) |
264 | #define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0) |
265 | #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0) |
266 | #define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0) |
267 | #define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1) |
268 | #define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0) |
269 | #define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2) |
270 | #define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2) |
271 | #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2) |
272 | #define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2) |
273 | #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2) |
274 | #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2) |
275 | #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1) |
276 | |
277 | /* ETM */ |
278 | #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4) |
279 | |
280 | #define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0) |
281 | |
282 | #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) |
283 | #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) |
284 | #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) |
285 | |
286 | #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) |
287 | #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) |
288 | #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) |
289 | |
290 | #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) |
291 | |
292 | #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) |
293 | #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) |
294 | #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) |
295 | #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) |
296 | |
297 | #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) |
298 | #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) |
299 | #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) |
300 | #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) |
301 | |
302 | #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) |
303 | #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) |
304 | |
305 | #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) |
306 | #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) |
307 | |
308 | #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) |
309 | |
310 | #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) |
311 | #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) |
312 | #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) |
313 | |
314 | #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) |
315 | #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) |
316 | #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) |
317 | #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) |
318 | #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) |
319 | #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) |
320 | #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4) |
321 | #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5) |
322 | #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6) |
323 | #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) |
324 | #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) |
325 | #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2) |
326 | #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3) |
327 | #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0) |
328 | #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1) |
329 | |
330 | #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) |
331 | |
332 | #define SYS_PAR_EL1_F BIT(0) |
333 | /* When PAR_EL1.F == 1 */ |
334 | #define SYS_PAR_EL1_FST GENMASK(6, 1) |
335 | #define SYS_PAR_EL1_PTW BIT(8) |
336 | #define SYS_PAR_EL1_S BIT(9) |
337 | #define SYS_PAR_EL1_AssuredOnly BIT(12) |
338 | #define SYS_PAR_EL1_TopLevel BIT(13) |
339 | #define SYS_PAR_EL1_Overlay BIT(14) |
340 | #define SYS_PAR_EL1_DirtyBit BIT(15) |
341 | #define SYS_PAR_EL1_F1_IMPDEF GENMASK_ULL(63, 48) |
342 | #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16)) |
343 | #define SYS_PAR_EL1_RES1 BIT(11) |
344 | /* When PAR_EL1.F == 0 */ |
345 | #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7) |
346 | #define SYS_PAR_EL1_NS BIT(9) |
347 | #define SYS_PAR_EL1_F0_IMPDEF BIT(10) |
348 | #define SYS_PAR_EL1_NSE BIT(11) |
349 | #define SYS_PAR_EL1_PA GENMASK_ULL(51, 12) |
350 | #define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56) |
351 | #define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52)) |
352 | |
353 | /*** Statistical Profiling Extension ***/ |
354 | #define PMSEVFR_EL1_RES0_IMP \ |
355 | (GENMASK_ULL(47, 32) | GENMASK_ULL(23, 16) | GENMASK_ULL(11, 8) |\ |
356 | BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) |
357 | #define PMSEVFR_EL1_RES0_V1P1 \ |
358 | (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) |
359 | #define PMSEVFR_EL1_RES0_V1P2 \ |
360 | (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) |
361 | |
362 | /* Buffer error reporting */ |
363 | #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT |
364 | #define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK |
365 | |
366 | #define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT |
367 | #define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK |
368 | |
369 | #define PMBSR_EL1_BUF_BSC_FULL 0x1UL |
370 | |
371 | /*** End of Statistical Profiling Extension ***/ |
372 | |
373 | #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) |
374 | #define TRBSR_EL1_BSC_SHIFT 0 |
375 | |
376 | #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) |
377 | #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) |
378 | |
379 | #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) |
380 | |
381 | #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) |
382 | #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) |
383 | |
384 | #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) |
385 | #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) |
386 | |
387 | #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) |
388 | #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) |
389 | #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) |
390 | #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) |
391 | #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) |
392 | #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) |
393 | #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) |
394 | #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) |
395 | #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) |
396 | #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) |
397 | #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) |
398 | #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) |
399 | #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) |
400 | #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) |
401 | #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) |
402 | #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) |
403 | #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) |
404 | #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) |
405 | #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) |
406 | #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) |
407 | #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) |
408 | #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) |
409 | #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) |
410 | #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) |
411 | #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) |
412 | #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) |
413 | #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) |
414 | |
415 | #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5) |
416 | |
417 | #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) |
418 | |
419 | #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) |
420 | |
421 | #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) |
422 | #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) |
423 | |
424 | #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) |
425 | #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) |
426 | #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) |
427 | #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) |
428 | #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) |
429 | #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) |
430 | #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) |
431 | #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) |
432 | #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) |
433 | #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) |
434 | #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) |
435 | #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) |
436 | |
437 | #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) |
438 | #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) |
439 | #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5) |
440 | |
441 | #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7) |
442 | |
443 | /* Definitions for system register interface to AMU for ARMv8.4 onwards */ |
444 | #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) |
445 | #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) |
446 | #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) |
447 | #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) |
448 | #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) |
449 | #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) |
450 | #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) |
451 | #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) |
452 | #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) |
453 | |
454 | /* |
455 | * Group 0 of activity monitors (architected): |
456 | * op0 op1 CRn CRm op2 |
457 | * Counter: 11 011 1101 010:n<3> n<2:0> |
458 | * Type: 11 011 1101 011:n<3> n<2:0> |
459 | * n: 0-15 |
460 | * |
461 | * Group 1 of activity monitors (auxiliary): |
462 | * op0 op1 CRn CRm op2 |
463 | * Counter: 11 011 1101 110:n<3> n<2:0> |
464 | * Type: 11 011 1101 111:n<3> n<2:0> |
465 | * n: 0-15 |
466 | */ |
467 | |
468 | #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) |
469 | #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) |
470 | #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) |
471 | #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) |
472 | |
473 | /* AMU v1: Fixed (architecturally defined) activity monitors */ |
474 | #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) |
475 | #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) |
476 | #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) |
477 | #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) |
478 | |
479 | #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) |
480 | |
481 | #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1) |
482 | #define SYS_CNTVCT_EL0 sys_reg(3, 3, 14, 0, 2) |
483 | #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5) |
484 | #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6) |
485 | |
486 | #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) |
487 | #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) |
488 | #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) |
489 | |
490 | #define SYS_CNTV_TVAL_EL0 sys_reg(3, 3, 14, 3, 0) |
491 | #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) |
492 | #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) |
493 | |
494 | #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) |
495 | #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) |
496 | #define SYS_AARCH32_CNTPCT sys_reg(0, 0, 0, 14, 0) |
497 | #define SYS_AARCH32_CNTVCT sys_reg(0, 1, 0, 14, 0) |
498 | #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) |
499 | #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0) |
500 | #define SYS_AARCH32_CNTVCTSS sys_reg(0, 9, 0, 14, 0) |
501 | |
502 | #define __PMEV_op2(n) ((n) & 0x7) |
503 | #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) |
504 | #define SYS_PMEVCNTSVRn_EL1(n) sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n)) |
505 | #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) |
506 | #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) |
507 | #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) |
508 | |
509 | #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) |
510 | |
511 | #define SYS_SPMCGCRn_EL1(n) sys_reg(2, 0, 9, 13, ((n) & 1)) |
512 | |
513 | #define __SPMEV_op2(n) ((n) & 0x7) |
514 | #define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1)) |
515 | #define SYS_SPMEVCNTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n)) |
516 | #define SYS_SPMEVFILT2Rn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n)) |
517 | #define SYS_SPMEVFILTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n)) |
518 | #define SYS_SPMEVTYPERn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n)) |
519 | |
520 | #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0) |
521 | #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5) |
522 | |
523 | #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0) |
524 | #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) |
525 | #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3) |
526 | #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0) |
527 | #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1) |
528 | #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2) |
529 | #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3) |
530 | #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7) |
531 | |
532 | #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0) |
533 | #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1) |
534 | #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2) |
535 | #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) |
536 | #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2) |
537 | |
538 | #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) |
539 | #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) |
540 | #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) |
541 | #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0) |
542 | #define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0) |
543 | #define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1) |
544 | #define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2) |
545 | #define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3) |
546 | #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) |
547 | #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0) |
548 | #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1) |
549 | #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) |
550 | #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) |
551 | #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) |
552 | #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0) |
553 | |
554 | #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) |
555 | #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4) |
556 | |
557 | #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0) |
558 | #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0) |
559 | |
560 | #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0) |
561 | #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1) |
562 | #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2) |
563 | #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) |
564 | #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) |
565 | #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) |
566 | #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) |
567 | #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) |
568 | #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) |
569 | |
570 | #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) |
571 | #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) |
572 | #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) |
573 | #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) |
574 | #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) |
575 | |
576 | #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) |
577 | #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) |
578 | #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) |
579 | #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) |
580 | #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7) |
581 | |
582 | #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) |
583 | #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) |
584 | #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) |
585 | #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) |
586 | #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) |
587 | #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) |
588 | #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) |
589 | #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) |
590 | #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) |
591 | |
592 | #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) |
593 | #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) |
594 | #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) |
595 | #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) |
596 | #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) |
597 | #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) |
598 | #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) |
599 | #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) |
600 | #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) |
601 | |
602 | #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1) |
603 | #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2) |
604 | #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7) |
605 | |
606 | #define __AMEV_op2(m) (m & 0x7) |
607 | #define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3)) |
608 | #define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m)) |
609 | #define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m) |
610 | #define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m)) |
611 | #define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m) |
612 | |
613 | #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) |
614 | #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) |
615 | #define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0) |
616 | #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1) |
617 | #define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2) |
618 | #define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0) |
619 | #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1) |
620 | #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2) |
621 | |
622 | /* VHE encodings for architectural EL0/1 system registers */ |
623 | #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0) |
624 | #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) |
625 | #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) |
626 | #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) |
627 | #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) |
628 | #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) |
629 | #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) |
630 | #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) |
631 | #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) |
632 | #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0) |
633 | #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) |
634 | #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) |
635 | #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) |
636 | #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7) |
637 | #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) |
638 | #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) |
639 | #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) |
640 | #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) |
641 | #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) |
642 | #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) |
643 | #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) |
644 | |
645 | #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0) |
646 | |
647 | /* AT instructions */ |
648 | #define AT_Op0 1 |
649 | #define AT_CRn 7 |
650 | |
651 | #define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0) |
652 | #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1) |
653 | #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2) |
654 | #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3) |
655 | #define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0) |
656 | #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1) |
657 | #define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2) |
658 | #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0) |
659 | #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1) |
660 | #define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4) |
661 | #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5) |
662 | #define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6) |
663 | #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7) |
664 | #define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2) |
665 | |
666 | /* TLBI instructions */ |
667 | #define TLBI_Op0 1 |
668 | |
669 | #define TLBI_Op1_EL1 0 /* Accessible from EL1 or higher */ |
670 | #define TLBI_Op1_EL2 4 /* Accessible from EL2 or higher */ |
671 | |
672 | #define TLBI_CRn_XS 8 /* Extra Slow (the common one) */ |
673 | #define TLBI_CRn_nXS 9 /* not Extra Slow (which nobody uses)*/ |
674 | |
675 | #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */ |
676 | #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */ |
677 | #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */ |
678 | #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */ |
679 | #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */ |
680 | #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */ |
681 | #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */ |
682 | #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */ |
683 | |
684 | #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0) |
685 | #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1) |
686 | #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2) |
687 | #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3) |
688 | #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5) |
689 | #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7) |
690 | #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1) |
691 | #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3) |
692 | #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5) |
693 | #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7) |
694 | #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0) |
695 | #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1) |
696 | #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2) |
697 | #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3) |
698 | #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5) |
699 | #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7) |
700 | #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1) |
701 | #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3) |
702 | #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5) |
703 | #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7) |
704 | #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1) |
705 | #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3) |
706 | #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5) |
707 | #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7) |
708 | #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0) |
709 | #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1) |
710 | #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2) |
711 | #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3) |
712 | #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5) |
713 | #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7) |
714 | #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0) |
715 | #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1) |
716 | #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2) |
717 | #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3) |
718 | #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5) |
719 | #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7) |
720 | #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1) |
721 | #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3) |
722 | #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5) |
723 | #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7) |
724 | #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0) |
725 | #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1) |
726 | #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2) |
727 | #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3) |
728 | #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5) |
729 | #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7) |
730 | #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1) |
731 | #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3) |
732 | #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5) |
733 | #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7) |
734 | #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1) |
735 | #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3) |
736 | #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5) |
737 | #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7) |
738 | #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0) |
739 | #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1) |
740 | #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2) |
741 | #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3) |
742 | #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5) |
743 | #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7) |
744 | #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1) |
745 | #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2) |
746 | #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5) |
747 | #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6) |
748 | #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0) |
749 | #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1) |
750 | #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4) |
751 | #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5) |
752 | #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6) |
753 | #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1) |
754 | #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5) |
755 | #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0) |
756 | #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1) |
757 | #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4) |
758 | #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5) |
759 | #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6) |
760 | #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0) |
761 | #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1) |
762 | #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2) |
763 | #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3) |
764 | #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4) |
765 | #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5) |
766 | #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6) |
767 | #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7) |
768 | #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1) |
769 | #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5) |
770 | #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1) |
771 | #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5) |
772 | #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0) |
773 | #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1) |
774 | #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4) |
775 | #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5) |
776 | #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6) |
777 | #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1) |
778 | #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2) |
779 | #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5) |
780 | #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6) |
781 | #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0) |
782 | #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1) |
783 | #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4) |
784 | #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5) |
785 | #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6) |
786 | #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1) |
787 | #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5) |
788 | #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0) |
789 | #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1) |
790 | #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4) |
791 | #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5) |
792 | #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6) |
793 | #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0) |
794 | #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1) |
795 | #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2) |
796 | #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3) |
797 | #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4) |
798 | #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5) |
799 | #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6) |
800 | #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7) |
801 | #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1) |
802 | #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5) |
803 | #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1) |
804 | #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5) |
805 | #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0) |
806 | #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1) |
807 | #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4) |
808 | #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5) |
809 | #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6) |
810 | |
811 | /* Misc instructions */ |
812 | #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4) |
813 | #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5) |
814 | #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6) |
815 | #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0) |
816 | |
817 | #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4) |
818 | #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5) |
819 | #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4) |
820 | #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5) |
821 | #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6) |
822 | #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7) |
823 | |
824 | /* Common SCTLR_ELx flags. */ |
825 | #define SCTLR_ELx_ENTP2 (BIT(60)) |
826 | #define SCTLR_ELx_DSSBS (BIT(44)) |
827 | #define SCTLR_ELx_ATA (BIT(43)) |
828 | |
829 | #define SCTLR_ELx_EE_SHIFT 25 |
830 | #define SCTLR_ELx_ENIA_SHIFT 31 |
831 | |
832 | #define SCTLR_ELx_ITFSB (BIT(37)) |
833 | #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT)) |
834 | #define SCTLR_ELx_ENIB (BIT(30)) |
835 | #define SCTLR_ELx_LSMAOE (BIT(29)) |
836 | #define SCTLR_ELx_nTLSMD (BIT(28)) |
837 | #define SCTLR_ELx_ENDA (BIT(27)) |
838 | #define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT)) |
839 | #define SCTLR_ELx_EIS (BIT(22)) |
840 | #define SCTLR_ELx_IESB (BIT(21)) |
841 | #define SCTLR_ELx_TSCXT (BIT(20)) |
842 | #define SCTLR_ELx_WXN (BIT(19)) |
843 | #define SCTLR_ELx_ENDB (BIT(13)) |
844 | #define SCTLR_ELx_I (BIT(12)) |
845 | #define SCTLR_ELx_EOS (BIT(11)) |
846 | #define SCTLR_ELx_SA (BIT(3)) |
847 | #define SCTLR_ELx_C (BIT(2)) |
848 | #define SCTLR_ELx_A (BIT(1)) |
849 | #define SCTLR_ELx_M (BIT(0)) |
850 | |
851 | /* SCTLR_EL2 specific flags. */ |
852 | #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \ |
853 | (BIT(18)) | (BIT(22)) | (BIT(23)) | (BIT(28)) | \ |
854 | (BIT(29))) |
855 | |
856 | #define SCTLR_EL2_BT (BIT(36)) |
857 | #ifdef CONFIG_CPU_BIG_ENDIAN |
858 | #define ENDIAN_SET_EL2 SCTLR_ELx_EE |
859 | #else |
860 | #define ENDIAN_SET_EL2 0 |
861 | #endif |
862 | |
863 | #define INIT_SCTLR_EL2_MMU_ON \ |
864 | (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \ |
865 | SCTLR_ELx_IESB | SCTLR_ELx_WXN | ENDIAN_SET_EL2 | \ |
866 | SCTLR_ELx_ITFSB | SCTLR_EL2_RES1) |
867 | |
868 | #define INIT_SCTLR_EL2_MMU_OFF \ |
869 | (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) |
870 | |
871 | /* SCTLR_EL1 specific flags. */ |
872 | #ifdef CONFIG_CPU_BIG_ENDIAN |
873 | #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) |
874 | #else |
875 | #define ENDIAN_SET_EL1 0 |
876 | #endif |
877 | |
878 | #define INIT_SCTLR_EL1_MMU_OFF \ |
879 | (ENDIAN_SET_EL1 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | \ |
880 | SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) |
881 | |
882 | #define INIT_SCTLR_EL1_MMU_ON \ |
883 | (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \ |
884 | SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \ |
885 | SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \ |
886 | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \ |
887 | ENDIAN_SET_EL1 | SCTLR_EL1_UCI | SCTLR_EL1_EPAN | \ |
888 | SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \ |
889 | SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) |
890 | |
891 | /* MAIR_ELx memory attributes (used by Linux) */ |
892 | #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) |
893 | #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) |
894 | #define MAIR_ATTR_NORMAL_NC UL(0x44) |
895 | #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0) |
896 | #define MAIR_ATTR_NORMAL UL(0xff) |
897 | #define MAIR_ATTR_MASK UL(0xff) |
898 | |
899 | /* Position the attr at the correct index */ |
900 | #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) |
901 | |
902 | /* id_aa64mmfr0 */ |
903 | #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0 |
904 | #define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT |
905 | #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7 |
906 | #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0 |
907 | #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7 |
908 | #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1 |
909 | #define ID_AA64MMFR0_EL1_TGRAN16_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT |
910 | #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf |
911 | |
912 | #define ARM64_MIN_PARANGE_BITS 32 |
913 | |
914 | #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0 |
915 | #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1 |
916 | #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2 |
917 | #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3 |
918 | #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 |
919 | |
920 | #ifdef CONFIG_ARM64_PA_BITS_52 |
921 | #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52 |
922 | #else |
923 | #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 |
924 | #endif |
925 | |
926 | #if defined(CONFIG_ARM64_4K_PAGES) |
927 | #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT |
928 | #define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT |
929 | #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN |
930 | #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX |
931 | #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT |
932 | #elif defined(CONFIG_ARM64_16K_PAGES) |
933 | #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT |
934 | #define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT |
935 | #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN |
936 | #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX |
937 | #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT |
938 | #elif defined(CONFIG_ARM64_64K_PAGES) |
939 | #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN64_SHIFT |
940 | #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN |
941 | #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX |
942 | #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT |
943 | #endif |
944 | |
945 | #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ |
946 | #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ |
947 | |
948 | #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */ |
949 | #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */ |
950 | |
951 | #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ |
952 | #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ |
953 | |
954 | /* GCR_EL1 Definitions */ |
955 | #define SYS_GCR_EL1_RRND (BIT(16)) |
956 | #define SYS_GCR_EL1_EXCL_MASK 0xffffUL |
957 | |
958 | #ifdef CONFIG_KASAN_HW_TAGS |
959 | /* |
960 | * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it |
961 | * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF. |
962 | */ |
963 | #define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf) |
964 | #define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf) |
965 | #define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN) |
966 | #define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL) |
967 | #else |
968 | #define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK |
969 | #endif |
970 | |
971 | #define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL) |
972 | |
973 | /* RGSR_EL1 Definitions */ |
974 | #define SYS_RGSR_EL1_TAG_MASK 0xfUL |
975 | #define SYS_RGSR_EL1_SEED_SHIFT 8 |
976 | #define SYS_RGSR_EL1_SEED_MASK 0xffffUL |
977 | |
978 | /* TFSR{,E0}_EL1 bit definitions */ |
979 | #define SYS_TFSR_EL1_TF0_SHIFT 0 |
980 | #define SYS_TFSR_EL1_TF1_SHIFT 1 |
981 | #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) |
982 | #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) |
983 | |
984 | /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ |
985 | #define SYS_MPIDR_SAFE_VAL (BIT(31)) |
986 | |
987 | /* GIC Hypervisor interface registers */ |
988 | /* ICH_LR*_EL2 bit definitions */ |
989 | #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) |
990 | |
991 | #define ICH_LR_EOI (1ULL << 41) |
992 | #define ICH_LR_GROUP (1ULL << 60) |
993 | #define ICH_LR_HW (1ULL << 61) |
994 | #define ICH_LR_STATE (3ULL << 62) |
995 | #define ICH_LR_PENDING_BIT (1ULL << 62) |
996 | #define ICH_LR_ACTIVE_BIT (1ULL << 63) |
997 | #define ICH_LR_PHYS_ID_SHIFT 32 |
998 | #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) |
999 | #define ICH_LR_PRIORITY_SHIFT 48 |
1000 | #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) |
1001 | |
1002 | /* ICH_VMCR_EL2 bit definitions */ |
1003 | #define ICH_VMCR_ACK_CTL_SHIFT 2 |
1004 | #define ICH_VMCR_ACK_CTL_MASK (1 << ICH_VMCR_ACK_CTL_SHIFT) |
1005 | #define ICH_VMCR_FIQ_EN_SHIFT 3 |
1006 | #define ICH_VMCR_FIQ_EN_MASK (1 << ICH_VMCR_FIQ_EN_SHIFT) |
1007 | #define ICH_VMCR_CBPR_SHIFT 4 |
1008 | #define ICH_VMCR_CBPR_MASK (1 << ICH_VMCR_CBPR_SHIFT) |
1009 | #define ICH_VMCR_EOIM_SHIFT 9 |
1010 | #define ICH_VMCR_EOIM_MASK (1 << ICH_VMCR_EOIM_SHIFT) |
1011 | #define ICH_VMCR_BPR1_SHIFT 18 |
1012 | #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT) |
1013 | #define ICH_VMCR_BPR0_SHIFT 21 |
1014 | #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT) |
1015 | #define ICH_VMCR_PMR_SHIFT 24 |
1016 | #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT) |
1017 | #define ICH_VMCR_ENG0_SHIFT 0 |
1018 | #define ICH_VMCR_ENG0_MASK (1 << ICH_VMCR_ENG0_SHIFT) |
1019 | #define ICH_VMCR_ENG1_SHIFT 1 |
1020 | #define ICH_VMCR_ENG1_MASK (1 << ICH_VMCR_ENG1_SHIFT) |
1021 | |
1022 | /* |
1023 | * Permission Indirection Extension (PIE) permission encodings. |
1024 | * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension). |
1025 | */ |
1026 | #define PIE_NONE_O UL(0x0) |
1027 | #define PIE_R_O UL(0x1) |
1028 | #define PIE_X_O UL(0x2) |
1029 | #define PIE_RX_O UL(0x3) |
1030 | #define PIE_RW_O UL(0x5) |
1031 | #define PIE_RWnX_O UL(0x6) |
1032 | #define PIE_RWX_O UL(0x7) |
1033 | #define PIE_R UL(0x8) |
1034 | #define PIE_GCS UL(0x9) |
1035 | #define PIE_RX UL(0xa) |
1036 | #define PIE_RW UL(0xc) |
1037 | #define PIE_RWX UL(0xe) |
1038 | #define PIE_MASK UL(0xf) |
1039 | |
1040 | #define PIRx_ELx_BITS_PER_IDX 4 |
1041 | #define PIRx_ELx_PERM_SHIFT(idx) ((idx) * PIRx_ELx_BITS_PER_IDX) |
1042 | #define PIRx_ELx_PERM_PREP(idx, perm) (((perm) & PIE_MASK) << PIRx_ELx_PERM_SHIFT(idx)) |
1043 | |
1044 | /* |
1045 | * Permission Overlay Extension (POE) permission encodings. |
1046 | */ |
1047 | #define POE_NONE UL(0x0) |
1048 | #define POE_R UL(0x1) |
1049 | #define POE_X UL(0x2) |
1050 | #define POE_RX UL(0x3) |
1051 | #define POE_W UL(0x4) |
1052 | #define POE_RW UL(0x5) |
1053 | #define POE_WX UL(0x6) |
1054 | #define POE_RWX UL(0x7) |
1055 | #define POE_MASK UL(0xf) |
1056 | |
1057 | #define POR_ELx_BITS_PER_IDX 4 |
1058 | #define POR_ELx_PERM_SHIFT(idx) ((idx) * POR_ELx_BITS_PER_IDX) |
1059 | #define POR_ELx_PERM_GET(idx, reg) (((reg) >> POR_ELx_PERM_SHIFT(idx)) & POE_MASK) |
1060 | #define POR_ELx_PERM_PREP(idx, perm) (((perm) & POE_MASK) << POR_ELx_PERM_SHIFT(idx)) |
1061 | |
1062 | /* |
1063 | * Definitions for Guarded Control Stack |
1064 | */ |
1065 | |
1066 | #define GCS_CAP_ADDR_MASK GENMASK(63, 12) |
1067 | #define GCS_CAP_ADDR_SHIFT 12 |
1068 | #define GCS_CAP_ADDR_WIDTH 52 |
1069 | #define GCS_CAP_ADDR(x) FIELD_GET(GCS_CAP_ADDR_MASK, x) |
1070 | |
1071 | #define GCS_CAP_TOKEN_MASK GENMASK(11, 0) |
1072 | #define GCS_CAP_TOKEN_SHIFT 0 |
1073 | #define GCS_CAP_TOKEN_WIDTH 12 |
1074 | #define GCS_CAP_TOKEN(x) FIELD_GET(GCS_CAP_TOKEN_MASK, x) |
1075 | |
1076 | #define GCS_CAP_VALID_TOKEN 0x1 |
1077 | #define GCS_CAP_IN_PROGRESS_TOKEN 0x5 |
1078 | |
1079 | #define GCS_CAP(x) ((((unsigned long)x) & GCS_CAP_ADDR_MASK) | \ |
1080 | GCS_CAP_VALID_TOKEN) |
1081 | |
1082 | #define ARM64_FEATURE_FIELD_BITS 4 |
1083 | |
1084 | /* Defined for compatibility only, do not add new users. */ |
1085 | #define ARM64_FEATURE_MASK(x) (x##_MASK) |
1086 | |
1087 | #ifdef __ASSEMBLY__ |
1088 | |
1089 | .macro mrs_s, rt, sreg |
1090 | __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt)) |
1091 | .endm |
1092 | |
1093 | .macro msr_s, sreg, rt |
1094 | __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt)) |
1095 | .endm |
1096 | |
1097 | .macro msr_hcr_el2, reg |
1098 | #if IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23) |
1099 | dsb nsh |
1100 | msr hcr_el2, \reg |
1101 | isb |
1102 | #else |
1103 | msr hcr_el2, \reg |
1104 | #endif |
1105 | .endm |
1106 | #else |
1107 | |
1108 | #include <linux/bitfield.h> |
1109 | #include <linux/build_bug.h> |
1110 | #include <linux/types.h> |
1111 | #include <asm/alternative.h> |
1112 | |
1113 | #define DEFINE_MRS_S \ |
1114 | __DEFINE_ASM_GPR_NUMS \ |
1115 | " .macro mrs_s, rt, sreg\n" \ |
1116 | __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \ |
1117 | " .endm\n" |
1118 | |
1119 | #define DEFINE_MSR_S \ |
1120 | __DEFINE_ASM_GPR_NUMS \ |
1121 | " .macro msr_s, sreg, rt\n" \ |
1122 | __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \ |
1123 | " .endm\n" |
1124 | |
1125 | #define UNDEFINE_MRS_S \ |
1126 | " .purgem mrs_s\n" |
1127 | |
1128 | #define UNDEFINE_MSR_S \ |
1129 | " .purgem msr_s\n" |
1130 | |
1131 | #define __mrs_s(v, r) \ |
1132 | DEFINE_MRS_S \ |
1133 | " mrs_s " v ", " __stringify(r) "\n" \ |
1134 | UNDEFINE_MRS_S |
1135 | |
1136 | #define __msr_s(r, v) \ |
1137 | DEFINE_MSR_S \ |
1138 | " msr_s " __stringify(r) ", " v "\n" \ |
1139 | UNDEFINE_MSR_S |
1140 | |
1141 | /* |
1142 | * Unlike read_cpuid, calls to read_sysreg are never expected to be |
1143 | * optimized away or replaced with synthetic values. |
1144 | */ |
1145 | #define read_sysreg(r) ({ \ |
1146 | u64 __val; \ |
1147 | asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ |
1148 | __val; \ |
1149 | }) |
1150 | |
1151 | /* |
1152 | * The "Z" constraint normally means a zero immediate, but when combined with |
1153 | * the "%x0" template means XZR. |
1154 | */ |
1155 | #define write_sysreg(v, r) do { \ |
1156 | u64 __val = (u64)(v); \ |
1157 | asm volatile("msr " __stringify(r) ", %x0" \ |
1158 | : : "rZ" (__val)); \ |
1159 | } while (0) |
1160 | |
1161 | /* |
1162 | * For registers without architectural names, or simply unsupported by |
1163 | * GAS. |
1164 | * |
1165 | * __check_r forces warnings to be generated by the compiler when |
1166 | * evaluating r which wouldn't normally happen due to being passed to |
1167 | * the assembler via __stringify(r). |
1168 | */ |
1169 | #define read_sysreg_s(r) ({ \ |
1170 | u64 __val; \ |
1171 | u32 __maybe_unused __check_r = (u32)(r); \ |
1172 | asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ |
1173 | __val; \ |
1174 | }) |
1175 | |
1176 | #define write_sysreg_s(v, r) do { \ |
1177 | u64 __val = (u64)(v); \ |
1178 | u32 __maybe_unused __check_r = (u32)(r); \ |
1179 | asm volatile(__msr_s(r, "%x0") : : "rZ" (__val)); \ |
1180 | } while (0) |
1181 | |
1182 | /* |
1183 | * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the |
1184 | * set mask are set. Other bits are left as-is. |
1185 | */ |
1186 | #define sysreg_clear_set(sysreg, clear, set) do { \ |
1187 | u64 __scs_val = read_sysreg(sysreg); \ |
1188 | u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ |
1189 | if (__scs_new != __scs_val) \ |
1190 | write_sysreg(__scs_new, sysreg); \ |
1191 | } while (0) |
1192 | |
1193 | #define sysreg_clear_set_hcr(clear, set) do { \ |
1194 | u64 __scs_val = read_sysreg(hcr_el2); \ |
1195 | u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ |
1196 | if (__scs_new != __scs_val) \ |
1197 | write_sysreg_hcr(__scs_new); \ |
1198 | } while (0) |
1199 | |
1200 | #define sysreg_clear_set_s(sysreg, clear, set) do { \ |
1201 | u64 __scs_val = read_sysreg_s(sysreg); \ |
1202 | u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ |
1203 | if (__scs_new != __scs_val) \ |
1204 | write_sysreg_s(__scs_new, sysreg); \ |
1205 | } while (0) |
1206 | |
1207 | #define write_sysreg_hcr(__val) do { \ |
1208 | if (IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23) && \ |
1209 | (!system_capabilities_finalized() || \ |
1210 | alternative_has_cap_unlikely(ARM64_WORKAROUND_AMPERE_AC04_CPU_23))) \ |
1211 | asm volatile("dsb nsh; msr hcr_el2, %x0; isb" \ |
1212 | : : "rZ" (__val)); \ |
1213 | else \ |
1214 | asm volatile("msr hcr_el2, %x0" \ |
1215 | : : "rZ" (__val)); \ |
1216 | } while (0) |
1217 | |
1218 | #define read_sysreg_par() ({ \ |
1219 | u64 par; \ |
1220 | asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ |
1221 | par = read_sysreg(par_el1); \ |
1222 | asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ |
1223 | par; \ |
1224 | }) |
1225 | |
1226 | #define SYS_FIELD_VALUE(reg, field, val) reg##_##field##_##val |
1227 | |
1228 | #define SYS_FIELD_GET(reg, field, val) \ |
1229 | FIELD_GET(reg##_##field##_MASK, val) |
1230 | |
1231 | #define SYS_FIELD_PREP(reg, field, val) \ |
1232 | FIELD_PREP(reg##_##field##_MASK, val) |
1233 | |
1234 | #define SYS_FIELD_PREP_ENUM(reg, field, val) \ |
1235 | FIELD_PREP(reg##_##field##_MASK, \ |
1236 | SYS_FIELD_VALUE(reg, field, val)) |
1237 | |
1238 | #endif |
1239 | |
1240 | #endif /* __ASM_SYSREG_H */ |
1241 |
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