| 1 | // SPDX-License-Identifier: GPL-2.0-only |
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| 2 | /* |
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| 3 | * First-level interrupt controller model for Hexagon. |
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| 4 | * |
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| 5 | * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved. |
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| 6 | */ |
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| 7 | |
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| 8 | #include <linux/interrupt.h> |
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| 9 | #include <asm/irq.h> |
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| 10 | #include <asm/hexagon_vm.h> |
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| 11 | |
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| 12 | static void mask_irq(struct irq_data *data) |
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| 13 | { |
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| 14 | __vmintop_locdis((long) data->irq); |
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| 15 | } |
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| 16 | |
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| 17 | static void mask_irq_num(unsigned int irq) |
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| 18 | { |
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| 19 | __vmintop_locdis((long) irq); |
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| 20 | } |
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| 21 | |
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| 22 | static void unmask_irq(struct irq_data *data) |
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| 23 | { |
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| 24 | __vmintop_locen((long) data->irq); |
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| 25 | } |
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| 26 | |
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| 27 | /* This is actually all we need for handle_fasteoi_irq */ |
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| 28 | static void eoi_irq(struct irq_data *data) |
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| 29 | { |
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| 30 | __vmintop_globen((long) data->irq); |
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| 31 | } |
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| 32 | |
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| 33 | /* Power mamangement wake call. We don't need this, however, |
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| 34 | * if this is absent, then an -ENXIO error is returned to the |
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| 35 | * msm_serial driver, and it fails to correctly initialize. |
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| 36 | * This is a bug in the msm_serial driver, but, for now, we |
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| 37 | * work around it here, by providing this bogus handler. |
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| 38 | * XXX FIXME!!! remove this when msm_serial is fixed. |
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| 39 | */ |
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| 40 | static int set_wake(struct irq_data *data, unsigned int on) |
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| 41 | { |
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| 42 | return 0; |
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| 43 | } |
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| 44 | |
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| 45 | static struct irq_chip hexagon_irq_chip = { |
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| 46 | .name = "HEXAGON" , |
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| 47 | .irq_mask = mask_irq, |
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| 48 | .irq_unmask = unmask_irq, |
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| 49 | .irq_set_wake = set_wake, |
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| 50 | .irq_eoi = eoi_irq |
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| 51 | }; |
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| 52 | |
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| 53 | /** |
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| 54 | * The hexagon core comes with a first-level interrupt controller |
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| 55 | * with 32 total possible interrupts. When the core is embedded |
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| 56 | * into different systems/platforms, it is typically wrapped by |
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| 57 | * macro cells that provide one or more second-level interrupt |
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| 58 | * controllers that are cascaded into one or more of the first-level |
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| 59 | * interrupts handled here. The precise wiring of these other |
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| 60 | * irqs varies from platform to platform, and are set up & configured |
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| 61 | * in the platform-specific files. |
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| 62 | * |
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| 63 | * The first-level interrupt controller is wrapped by the VM, which |
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| 64 | * virtualizes the interrupt controller for us. It provides a very |
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| 65 | * simple, fast & efficient API, and so the fasteoi handler is |
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| 66 | * appropriate for this case. |
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| 67 | */ |
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| 68 | void __init init_IRQ(void) |
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| 69 | { |
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| 70 | int irq; |
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| 71 | |
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| 72 | for (irq = 0; irq < HEXAGON_CPUINTS; irq++) { |
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| 73 | mask_irq_num(irq); |
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| 74 | irq_set_chip_and_handler(irq, &hexagon_irq_chip, |
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| 75 | handle_fasteoi_irq); |
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| 76 | } |
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| 77 | } |
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| 78 | |
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