| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Author: Lu Zeng <zenglu@loongson.cn> |
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| 4 | * Pei Huang <huangpei@loongson.cn> |
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| 5 | * Huacai Chen <chenhuacai@loongson.cn> |
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| 6 | * |
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| 7 | * Copyright (C) 2020-2022 Loongson Technology Corporation Limited |
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| 8 | */ |
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| 9 | #include <linux/export.h> |
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| 10 | #include <asm/asm.h> |
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| 11 | #include <asm/asmmacro.h> |
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| 12 | #include <asm/asm-extable.h> |
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| 13 | #include <asm/asm-offsets.h> |
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| 14 | #include <asm/errno.h> |
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| 15 | #include <asm/fpregdef.h> |
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| 16 | #include <asm/loongarch.h> |
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| 17 | #include <asm/regdef.h> |
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| 18 | #include <asm/unwind_hints.h> |
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| 19 | |
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| 20 | #define FPU_REG_WIDTH 8 |
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| 21 | #define LSX_REG_WIDTH 16 |
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| 22 | #define LASX_REG_WIDTH 32 |
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| 23 | |
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| 24 | .macro EX insn, reg, src, offs |
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| 25 | .ex\@: \insn \reg, \src, \offs |
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| 26 | _asm_extable .ex\@, .L_fpu_fault |
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| 27 | .endm |
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| 28 | |
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| 29 | .macro sc_save_fp base |
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| 30 | EX fst.d $f0, \base, (0 * FPU_REG_WIDTH) |
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| 31 | EX fst.d $f1, \base, (1 * FPU_REG_WIDTH) |
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| 32 | EX fst.d $f2, \base, (2 * FPU_REG_WIDTH) |
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| 33 | EX fst.d $f3, \base, (3 * FPU_REG_WIDTH) |
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| 34 | EX fst.d $f4, \base, (4 * FPU_REG_WIDTH) |
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| 35 | EX fst.d $f5, \base, (5 * FPU_REG_WIDTH) |
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| 36 | EX fst.d $f6, \base, (6 * FPU_REG_WIDTH) |
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| 37 | EX fst.d $f7, \base, (7 * FPU_REG_WIDTH) |
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| 38 | EX fst.d $f8, \base, (8 * FPU_REG_WIDTH) |
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| 39 | EX fst.d $f9, \base, (9 * FPU_REG_WIDTH) |
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| 40 | EX fst.d $f10, \base, (10 * FPU_REG_WIDTH) |
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| 41 | EX fst.d $f11, \base, (11 * FPU_REG_WIDTH) |
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| 42 | EX fst.d $f12, \base, (12 * FPU_REG_WIDTH) |
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| 43 | EX fst.d $f13, \base, (13 * FPU_REG_WIDTH) |
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| 44 | EX fst.d $f14, \base, (14 * FPU_REG_WIDTH) |
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| 45 | EX fst.d $f15, \base, (15 * FPU_REG_WIDTH) |
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| 46 | EX fst.d $f16, \base, (16 * FPU_REG_WIDTH) |
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| 47 | EX fst.d $f17, \base, (17 * FPU_REG_WIDTH) |
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| 48 | EX fst.d $f18, \base, (18 * FPU_REG_WIDTH) |
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| 49 | EX fst.d $f19, \base, (19 * FPU_REG_WIDTH) |
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| 50 | EX fst.d $f20, \base, (20 * FPU_REG_WIDTH) |
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| 51 | EX fst.d $f21, \base, (21 * FPU_REG_WIDTH) |
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| 52 | EX fst.d $f22, \base, (22 * FPU_REG_WIDTH) |
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| 53 | EX fst.d $f23, \base, (23 * FPU_REG_WIDTH) |
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| 54 | EX fst.d $f24, \base, (24 * FPU_REG_WIDTH) |
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| 55 | EX fst.d $f25, \base, (25 * FPU_REG_WIDTH) |
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| 56 | EX fst.d $f26, \base, (26 * FPU_REG_WIDTH) |
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| 57 | EX fst.d $f27, \base, (27 * FPU_REG_WIDTH) |
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| 58 | EX fst.d $f28, \base, (28 * FPU_REG_WIDTH) |
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| 59 | EX fst.d $f29, \base, (29 * FPU_REG_WIDTH) |
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| 60 | EX fst.d $f30, \base, (30 * FPU_REG_WIDTH) |
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| 61 | EX fst.d $f31, \base, (31 * FPU_REG_WIDTH) |
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| 62 | .endm |
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| 63 | |
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| 64 | .macro sc_restore_fp base |
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| 65 | EX fld.d $f0, \base, (0 * FPU_REG_WIDTH) |
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| 66 | EX fld.d $f1, \base, (1 * FPU_REG_WIDTH) |
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| 67 | EX fld.d $f2, \base, (2 * FPU_REG_WIDTH) |
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| 68 | EX fld.d $f3, \base, (3 * FPU_REG_WIDTH) |
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| 69 | EX fld.d $f4, \base, (4 * FPU_REG_WIDTH) |
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| 70 | EX fld.d $f5, \base, (5 * FPU_REG_WIDTH) |
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| 71 | EX fld.d $f6, \base, (6 * FPU_REG_WIDTH) |
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| 72 | EX fld.d $f7, \base, (7 * FPU_REG_WIDTH) |
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| 73 | EX fld.d $f8, \base, (8 * FPU_REG_WIDTH) |
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| 74 | EX fld.d $f9, \base, (9 * FPU_REG_WIDTH) |
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| 75 | EX fld.d $f10, \base, (10 * FPU_REG_WIDTH) |
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| 76 | EX fld.d $f11, \base, (11 * FPU_REG_WIDTH) |
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| 77 | EX fld.d $f12, \base, (12 * FPU_REG_WIDTH) |
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| 78 | EX fld.d $f13, \base, (13 * FPU_REG_WIDTH) |
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| 79 | EX fld.d $f14, \base, (14 * FPU_REG_WIDTH) |
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| 80 | EX fld.d $f15, \base, (15 * FPU_REG_WIDTH) |
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| 81 | EX fld.d $f16, \base, (16 * FPU_REG_WIDTH) |
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| 82 | EX fld.d $f17, \base, (17 * FPU_REG_WIDTH) |
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| 83 | EX fld.d $f18, \base, (18 * FPU_REG_WIDTH) |
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| 84 | EX fld.d $f19, \base, (19 * FPU_REG_WIDTH) |
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| 85 | EX fld.d $f20, \base, (20 * FPU_REG_WIDTH) |
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| 86 | EX fld.d $f21, \base, (21 * FPU_REG_WIDTH) |
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| 87 | EX fld.d $f22, \base, (22 * FPU_REG_WIDTH) |
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| 88 | EX fld.d $f23, \base, (23 * FPU_REG_WIDTH) |
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| 89 | EX fld.d $f24, \base, (24 * FPU_REG_WIDTH) |
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| 90 | EX fld.d $f25, \base, (25 * FPU_REG_WIDTH) |
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| 91 | EX fld.d $f26, \base, (26 * FPU_REG_WIDTH) |
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| 92 | EX fld.d $f27, \base, (27 * FPU_REG_WIDTH) |
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| 93 | EX fld.d $f28, \base, (28 * FPU_REG_WIDTH) |
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| 94 | EX fld.d $f29, \base, (29 * FPU_REG_WIDTH) |
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| 95 | EX fld.d $f30, \base, (30 * FPU_REG_WIDTH) |
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| 96 | EX fld.d $f31, \base, (31 * FPU_REG_WIDTH) |
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| 97 | .endm |
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| 98 | |
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| 99 | .macro sc_save_fcc base, tmp0, tmp1 |
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| 100 | movcf2gr \tmp0, $fcc0 |
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| 101 | move \tmp1, \tmp0 |
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| 102 | movcf2gr \tmp0, $fcc1 |
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| 103 | bstrins.d \tmp1, \tmp0, 15, 8 |
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| 104 | movcf2gr \tmp0, $fcc2 |
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| 105 | bstrins.d \tmp1, \tmp0, 23, 16 |
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| 106 | movcf2gr \tmp0, $fcc3 |
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| 107 | bstrins.d \tmp1, \tmp0, 31, 24 |
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| 108 | movcf2gr \tmp0, $fcc4 |
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| 109 | bstrins.d \tmp1, \tmp0, 39, 32 |
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| 110 | movcf2gr \tmp0, $fcc5 |
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| 111 | bstrins.d \tmp1, \tmp0, 47, 40 |
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| 112 | movcf2gr \tmp0, $fcc6 |
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| 113 | bstrins.d \tmp1, \tmp0, 55, 48 |
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| 114 | movcf2gr \tmp0, $fcc7 |
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| 115 | bstrins.d \tmp1, \tmp0, 63, 56 |
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| 116 | EX st.d \tmp1, \base, 0 |
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| 117 | .endm |
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| 118 | |
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| 119 | .macro sc_restore_fcc base, tmp0, tmp1 |
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| 120 | EX ld.d \tmp0, \base, 0 |
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| 121 | bstrpick.d \tmp1, \tmp0, 7, 0 |
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| 122 | movgr2cf $fcc0, \tmp1 |
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| 123 | bstrpick.d \tmp1, \tmp0, 15, 8 |
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| 124 | movgr2cf $fcc1, \tmp1 |
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| 125 | bstrpick.d \tmp1, \tmp0, 23, 16 |
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| 126 | movgr2cf $fcc2, \tmp1 |
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| 127 | bstrpick.d \tmp1, \tmp0, 31, 24 |
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| 128 | movgr2cf $fcc3, \tmp1 |
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| 129 | bstrpick.d \tmp1, \tmp0, 39, 32 |
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| 130 | movgr2cf $fcc4, \tmp1 |
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| 131 | bstrpick.d \tmp1, \tmp0, 47, 40 |
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| 132 | movgr2cf $fcc5, \tmp1 |
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| 133 | bstrpick.d \tmp1, \tmp0, 55, 48 |
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| 134 | movgr2cf $fcc6, \tmp1 |
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| 135 | bstrpick.d \tmp1, \tmp0, 63, 56 |
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| 136 | movgr2cf $fcc7, \tmp1 |
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| 137 | .endm |
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| 138 | |
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| 139 | .macro sc_save_fcsr base, tmp0 |
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| 140 | movfcsr2gr \tmp0, fcsr0 |
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| 141 | EX st.w \tmp0, \base, 0 |
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| 142 | #if defined(CONFIG_CPU_HAS_LBT) |
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| 143 | /* TM bit is always 0 if LBT not supported */ |
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| 144 | andi \tmp0, \tmp0, FPU_CSR_TM |
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| 145 | beqz \tmp0, 1f |
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| 146 | x86clrtm |
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| 147 | 1: |
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| 148 | #endif |
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| 149 | .endm |
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| 150 | |
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| 151 | .macro sc_restore_fcsr base, tmp0 |
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| 152 | EX ld.w \tmp0, \base, 0 |
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| 153 | movgr2fcsr fcsr0, \tmp0 |
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| 154 | .endm |
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| 155 | |
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| 156 | .macro sc_save_lsx base |
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| 157 | #ifdef CONFIG_CPU_HAS_LSX |
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| 158 | EX vst $vr0, \base, (0 * LSX_REG_WIDTH) |
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| 159 | EX vst $vr1, \base, (1 * LSX_REG_WIDTH) |
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| 160 | EX vst $vr2, \base, (2 * LSX_REG_WIDTH) |
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| 161 | EX vst $vr3, \base, (3 * LSX_REG_WIDTH) |
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| 162 | EX vst $vr4, \base, (4 * LSX_REG_WIDTH) |
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| 163 | EX vst $vr5, \base, (5 * LSX_REG_WIDTH) |
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| 164 | EX vst $vr6, \base, (6 * LSX_REG_WIDTH) |
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| 165 | EX vst $vr7, \base, (7 * LSX_REG_WIDTH) |
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| 166 | EX vst $vr8, \base, (8 * LSX_REG_WIDTH) |
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| 167 | EX vst $vr9, \base, (9 * LSX_REG_WIDTH) |
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| 168 | EX vst $vr10, \base, (10 * LSX_REG_WIDTH) |
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| 169 | EX vst $vr11, \base, (11 * LSX_REG_WIDTH) |
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| 170 | EX vst $vr12, \base, (12 * LSX_REG_WIDTH) |
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| 171 | EX vst $vr13, \base, (13 * LSX_REG_WIDTH) |
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| 172 | EX vst $vr14, \base, (14 * LSX_REG_WIDTH) |
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| 173 | EX vst $vr15, \base, (15 * LSX_REG_WIDTH) |
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| 174 | EX vst $vr16, \base, (16 * LSX_REG_WIDTH) |
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| 175 | EX vst $vr17, \base, (17 * LSX_REG_WIDTH) |
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| 176 | EX vst $vr18, \base, (18 * LSX_REG_WIDTH) |
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| 177 | EX vst $vr19, \base, (19 * LSX_REG_WIDTH) |
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| 178 | EX vst $vr20, \base, (20 * LSX_REG_WIDTH) |
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| 179 | EX vst $vr21, \base, (21 * LSX_REG_WIDTH) |
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| 180 | EX vst $vr22, \base, (22 * LSX_REG_WIDTH) |
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| 181 | EX vst $vr23, \base, (23 * LSX_REG_WIDTH) |
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| 182 | EX vst $vr24, \base, (24 * LSX_REG_WIDTH) |
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| 183 | EX vst $vr25, \base, (25 * LSX_REG_WIDTH) |
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| 184 | EX vst $vr26, \base, (26 * LSX_REG_WIDTH) |
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| 185 | EX vst $vr27, \base, (27 * LSX_REG_WIDTH) |
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| 186 | EX vst $vr28, \base, (28 * LSX_REG_WIDTH) |
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| 187 | EX vst $vr29, \base, (29 * LSX_REG_WIDTH) |
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| 188 | EX vst $vr30, \base, (30 * LSX_REG_WIDTH) |
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| 189 | EX vst $vr31, \base, (31 * LSX_REG_WIDTH) |
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| 190 | #endif |
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| 191 | .endm |
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| 192 | |
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| 193 | .macro sc_restore_lsx base |
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| 194 | #ifdef CONFIG_CPU_HAS_LSX |
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| 195 | EX vld $vr0, \base, (0 * LSX_REG_WIDTH) |
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| 196 | EX vld $vr1, \base, (1 * LSX_REG_WIDTH) |
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| 197 | EX vld $vr2, \base, (2 * LSX_REG_WIDTH) |
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| 198 | EX vld $vr3, \base, (3 * LSX_REG_WIDTH) |
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| 199 | EX vld $vr4, \base, (4 * LSX_REG_WIDTH) |
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| 200 | EX vld $vr5, \base, (5 * LSX_REG_WIDTH) |
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| 201 | EX vld $vr6, \base, (6 * LSX_REG_WIDTH) |
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| 202 | EX vld $vr7, \base, (7 * LSX_REG_WIDTH) |
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| 203 | EX vld $vr8, \base, (8 * LSX_REG_WIDTH) |
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| 204 | EX vld $vr9, \base, (9 * LSX_REG_WIDTH) |
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| 205 | EX vld $vr10, \base, (10 * LSX_REG_WIDTH) |
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| 206 | EX vld $vr11, \base, (11 * LSX_REG_WIDTH) |
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| 207 | EX vld $vr12, \base, (12 * LSX_REG_WIDTH) |
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| 208 | EX vld $vr13, \base, (13 * LSX_REG_WIDTH) |
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| 209 | EX vld $vr14, \base, (14 * LSX_REG_WIDTH) |
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| 210 | EX vld $vr15, \base, (15 * LSX_REG_WIDTH) |
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| 211 | EX vld $vr16, \base, (16 * LSX_REG_WIDTH) |
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| 212 | EX vld $vr17, \base, (17 * LSX_REG_WIDTH) |
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| 213 | EX vld $vr18, \base, (18 * LSX_REG_WIDTH) |
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| 214 | EX vld $vr19, \base, (19 * LSX_REG_WIDTH) |
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| 215 | EX vld $vr20, \base, (20 * LSX_REG_WIDTH) |
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| 216 | EX vld $vr21, \base, (21 * LSX_REG_WIDTH) |
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| 217 | EX vld $vr22, \base, (22 * LSX_REG_WIDTH) |
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| 218 | EX vld $vr23, \base, (23 * LSX_REG_WIDTH) |
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| 219 | EX vld $vr24, \base, (24 * LSX_REG_WIDTH) |
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| 220 | EX vld $vr25, \base, (25 * LSX_REG_WIDTH) |
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| 221 | EX vld $vr26, \base, (26 * LSX_REG_WIDTH) |
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| 222 | EX vld $vr27, \base, (27 * LSX_REG_WIDTH) |
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| 223 | EX vld $vr28, \base, (28 * LSX_REG_WIDTH) |
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| 224 | EX vld $vr29, \base, (29 * LSX_REG_WIDTH) |
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| 225 | EX vld $vr30, \base, (30 * LSX_REG_WIDTH) |
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| 226 | EX vld $vr31, \base, (31 * LSX_REG_WIDTH) |
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| 227 | #endif |
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| 228 | .endm |
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| 229 | |
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| 230 | .macro sc_save_lasx base |
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| 231 | #ifdef CONFIG_CPU_HAS_LASX |
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| 232 | EX xvst $xr0, \base, (0 * LASX_REG_WIDTH) |
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| 233 | EX xvst $xr1, \base, (1 * LASX_REG_WIDTH) |
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| 234 | EX xvst $xr2, \base, (2 * LASX_REG_WIDTH) |
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| 235 | EX xvst $xr3, \base, (3 * LASX_REG_WIDTH) |
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| 236 | EX xvst $xr4, \base, (4 * LASX_REG_WIDTH) |
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| 237 | EX xvst $xr5, \base, (5 * LASX_REG_WIDTH) |
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| 238 | EX xvst $xr6, \base, (6 * LASX_REG_WIDTH) |
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| 239 | EX xvst $xr7, \base, (7 * LASX_REG_WIDTH) |
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| 240 | EX xvst $xr8, \base, (8 * LASX_REG_WIDTH) |
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| 241 | EX xvst $xr9, \base, (9 * LASX_REG_WIDTH) |
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| 242 | EX xvst $xr10, \base, (10 * LASX_REG_WIDTH) |
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| 243 | EX xvst $xr11, \base, (11 * LASX_REG_WIDTH) |
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| 244 | EX xvst $xr12, \base, (12 * LASX_REG_WIDTH) |
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| 245 | EX xvst $xr13, \base, (13 * LASX_REG_WIDTH) |
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| 246 | EX xvst $xr14, \base, (14 * LASX_REG_WIDTH) |
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| 247 | EX xvst $xr15, \base, (15 * LASX_REG_WIDTH) |
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| 248 | EX xvst $xr16, \base, (16 * LASX_REG_WIDTH) |
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| 249 | EX xvst $xr17, \base, (17 * LASX_REG_WIDTH) |
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| 250 | EX xvst $xr18, \base, (18 * LASX_REG_WIDTH) |
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| 251 | EX xvst $xr19, \base, (19 * LASX_REG_WIDTH) |
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| 252 | EX xvst $xr20, \base, (20 * LASX_REG_WIDTH) |
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| 253 | EX xvst $xr21, \base, (21 * LASX_REG_WIDTH) |
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| 254 | EX xvst $xr22, \base, (22 * LASX_REG_WIDTH) |
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| 255 | EX xvst $xr23, \base, (23 * LASX_REG_WIDTH) |
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| 256 | EX xvst $xr24, \base, (24 * LASX_REG_WIDTH) |
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| 257 | EX xvst $xr25, \base, (25 * LASX_REG_WIDTH) |
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| 258 | EX xvst $xr26, \base, (26 * LASX_REG_WIDTH) |
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| 259 | EX xvst $xr27, \base, (27 * LASX_REG_WIDTH) |
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| 260 | EX xvst $xr28, \base, (28 * LASX_REG_WIDTH) |
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| 261 | EX xvst $xr29, \base, (29 * LASX_REG_WIDTH) |
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| 262 | EX xvst $xr30, \base, (30 * LASX_REG_WIDTH) |
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| 263 | EX xvst $xr31, \base, (31 * LASX_REG_WIDTH) |
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| 264 | #endif |
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| 265 | .endm |
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| 266 | |
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| 267 | .macro sc_restore_lasx base |
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| 268 | #ifdef CONFIG_CPU_HAS_LASX |
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| 269 | EX xvld $xr0, \base, (0 * LASX_REG_WIDTH) |
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| 270 | EX xvld $xr1, \base, (1 * LASX_REG_WIDTH) |
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| 271 | EX xvld $xr2, \base, (2 * LASX_REG_WIDTH) |
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| 272 | EX xvld $xr3, \base, (3 * LASX_REG_WIDTH) |
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| 273 | EX xvld $xr4, \base, (4 * LASX_REG_WIDTH) |
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| 274 | EX xvld $xr5, \base, (5 * LASX_REG_WIDTH) |
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| 275 | EX xvld $xr6, \base, (6 * LASX_REG_WIDTH) |
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| 276 | EX xvld $xr7, \base, (7 * LASX_REG_WIDTH) |
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| 277 | EX xvld $xr8, \base, (8 * LASX_REG_WIDTH) |
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| 278 | EX xvld $xr9, \base, (9 * LASX_REG_WIDTH) |
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| 279 | EX xvld $xr10, \base, (10 * LASX_REG_WIDTH) |
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| 280 | EX xvld $xr11, \base, (11 * LASX_REG_WIDTH) |
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| 281 | EX xvld $xr12, \base, (12 * LASX_REG_WIDTH) |
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| 282 | EX xvld $xr13, \base, (13 * LASX_REG_WIDTH) |
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| 283 | EX xvld $xr14, \base, (14 * LASX_REG_WIDTH) |
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| 284 | EX xvld $xr15, \base, (15 * LASX_REG_WIDTH) |
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| 285 | EX xvld $xr16, \base, (16 * LASX_REG_WIDTH) |
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| 286 | EX xvld $xr17, \base, (17 * LASX_REG_WIDTH) |
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| 287 | EX xvld $xr18, \base, (18 * LASX_REG_WIDTH) |
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| 288 | EX xvld $xr19, \base, (19 * LASX_REG_WIDTH) |
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| 289 | EX xvld $xr20, \base, (20 * LASX_REG_WIDTH) |
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| 290 | EX xvld $xr21, \base, (21 * LASX_REG_WIDTH) |
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| 291 | EX xvld $xr22, \base, (22 * LASX_REG_WIDTH) |
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| 292 | EX xvld $xr23, \base, (23 * LASX_REG_WIDTH) |
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| 293 | EX xvld $xr24, \base, (24 * LASX_REG_WIDTH) |
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| 294 | EX xvld $xr25, \base, (25 * LASX_REG_WIDTH) |
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| 295 | EX xvld $xr26, \base, (26 * LASX_REG_WIDTH) |
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| 296 | EX xvld $xr27, \base, (27 * LASX_REG_WIDTH) |
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| 297 | EX xvld $xr28, \base, (28 * LASX_REG_WIDTH) |
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| 298 | EX xvld $xr29, \base, (29 * LASX_REG_WIDTH) |
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| 299 | EX xvld $xr30, \base, (30 * LASX_REG_WIDTH) |
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| 300 | EX xvld $xr31, \base, (31 * LASX_REG_WIDTH) |
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| 301 | #endif |
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| 302 | .endm |
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| 303 | |
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| 304 | /* |
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| 305 | * Save a thread's fp context. |
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| 306 | */ |
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| 307 | SYM_FUNC_START(_save_fp) |
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| 308 | fpu_save_csr a0 t1 |
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| 309 | fpu_save_double a0 t1 # clobbers t1 |
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| 310 | fpu_save_cc a0 t1 t2 # clobbers t1, t2 |
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| 311 | jr ra |
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| 312 | SYM_FUNC_END(_save_fp) |
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| 313 | EXPORT_SYMBOL(_save_fp) |
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| 314 | |
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| 315 | /* |
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| 316 | * Restore a thread's fp context. |
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| 317 | */ |
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| 318 | SYM_FUNC_START(_restore_fp) |
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| 319 | fpu_restore_double a0 t1 # clobbers t1 |
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| 320 | fpu_restore_csr a0 t1 t2 |
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| 321 | fpu_restore_cc a0 t1 t2 # clobbers t1, t2 |
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| 322 | jr ra |
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| 323 | SYM_FUNC_END(_restore_fp) |
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| 324 | |
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| 325 | #ifdef CONFIG_CPU_HAS_LSX |
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| 326 | |
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| 327 | /* |
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| 328 | * Save a thread's LSX vector context. |
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| 329 | */ |
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| 330 | SYM_FUNC_START(_save_lsx) |
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| 331 | lsx_save_all a0 t1 t2 |
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| 332 | jr ra |
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| 333 | SYM_FUNC_END(_save_lsx) |
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| 334 | EXPORT_SYMBOL(_save_lsx) |
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| 335 | |
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| 336 | /* |
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| 337 | * Restore a thread's LSX vector context. |
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| 338 | */ |
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| 339 | SYM_FUNC_START(_restore_lsx) |
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| 340 | lsx_restore_all a0 t1 t2 |
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| 341 | jr ra |
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| 342 | SYM_FUNC_END(_restore_lsx) |
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| 343 | |
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| 344 | SYM_FUNC_START(_save_lsx_upper) |
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| 345 | lsx_save_all_upper a0 t0 t1 |
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| 346 | jr ra |
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| 347 | SYM_FUNC_END(_save_lsx_upper) |
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| 348 | |
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| 349 | SYM_FUNC_START(_restore_lsx_upper) |
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| 350 | lsx_restore_all_upper a0 t0 t1 |
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| 351 | jr ra |
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| 352 | SYM_FUNC_END(_restore_lsx_upper) |
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| 353 | EXPORT_SYMBOL(_restore_lsx_upper) |
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| 354 | |
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| 355 | SYM_FUNC_START(_init_lsx_upper) |
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| 356 | lsx_init_all_upper t1 |
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| 357 | jr ra |
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| 358 | SYM_FUNC_END(_init_lsx_upper) |
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| 359 | #endif |
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| 360 | |
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| 361 | #ifdef CONFIG_CPU_HAS_LASX |
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| 362 | |
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| 363 | /* |
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| 364 | * Save a thread's LASX vector context. |
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| 365 | */ |
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| 366 | SYM_FUNC_START(_save_lasx) |
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| 367 | lasx_save_all a0 t1 t2 |
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| 368 | jr ra |
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| 369 | SYM_FUNC_END(_save_lasx) |
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| 370 | EXPORT_SYMBOL(_save_lasx) |
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| 371 | |
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| 372 | /* |
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| 373 | * Restore a thread's LASX vector context. |
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| 374 | */ |
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| 375 | SYM_FUNC_START(_restore_lasx) |
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| 376 | lasx_restore_all a0 t1 t2 |
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| 377 | jr ra |
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| 378 | SYM_FUNC_END(_restore_lasx) |
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| 379 | |
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| 380 | SYM_FUNC_START(_save_lasx_upper) |
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| 381 | lasx_save_all_upper a0 t0 t1 |
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| 382 | jr ra |
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| 383 | SYM_FUNC_END(_save_lasx_upper) |
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| 384 | |
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| 385 | SYM_FUNC_START(_restore_lasx_upper) |
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| 386 | lasx_restore_all_upper a0 t0 t1 |
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| 387 | jr ra |
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| 388 | SYM_FUNC_END(_restore_lasx_upper) |
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| 389 | EXPORT_SYMBOL(_restore_lasx_upper) |
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| 390 | |
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| 391 | SYM_FUNC_START(_init_lasx_upper) |
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| 392 | lasx_init_all_upper t1 |
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| 393 | jr ra |
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| 394 | SYM_FUNC_END(_init_lasx_upper) |
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| 395 | #endif |
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| 396 | |
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| 397 | /* |
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| 398 | * Load the FPU with signalling NANS. This bit pattern we're using has |
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| 399 | * the property that no matter whether considered as single or as double |
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| 400 | * precision represents signaling NANS. |
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| 401 | * |
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| 402 | * The value to initialize fcsr0 to comes in $a0. |
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| 403 | */ |
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| 404 | |
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| 405 | SYM_FUNC_START(_init_fpu) |
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| 406 | li.w t1, CSR_EUEN_FPEN |
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| 407 | csrxchg t1, t1, LOONGARCH_CSR_EUEN |
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| 408 | |
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| 409 | movgr2fcsr fcsr0, a0 |
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| 410 | |
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| 411 | li.w t1, -1 # SNaN |
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| 412 | |
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| 413 | movgr2fr.d $f0, t1 |
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| 414 | movgr2fr.d $f1, t1 |
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| 415 | movgr2fr.d $f2, t1 |
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| 416 | movgr2fr.d $f3, t1 |
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| 417 | movgr2fr.d $f4, t1 |
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| 418 | movgr2fr.d $f5, t1 |
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| 419 | movgr2fr.d $f6, t1 |
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| 420 | movgr2fr.d $f7, t1 |
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| 421 | movgr2fr.d $f8, t1 |
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| 422 | movgr2fr.d $f9, t1 |
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| 423 | movgr2fr.d $f10, t1 |
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| 424 | movgr2fr.d $f11, t1 |
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| 425 | movgr2fr.d $f12, t1 |
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| 426 | movgr2fr.d $f13, t1 |
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| 427 | movgr2fr.d $f14, t1 |
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| 428 | movgr2fr.d $f15, t1 |
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| 429 | movgr2fr.d $f16, t1 |
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| 430 | movgr2fr.d $f17, t1 |
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| 431 | movgr2fr.d $f18, t1 |
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| 432 | movgr2fr.d $f19, t1 |
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| 433 | movgr2fr.d $f20, t1 |
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| 434 | movgr2fr.d $f21, t1 |
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| 435 | movgr2fr.d $f22, t1 |
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| 436 | movgr2fr.d $f23, t1 |
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| 437 | movgr2fr.d $f24, t1 |
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| 438 | movgr2fr.d $f25, t1 |
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| 439 | movgr2fr.d $f26, t1 |
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| 440 | movgr2fr.d $f27, t1 |
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| 441 | movgr2fr.d $f28, t1 |
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| 442 | movgr2fr.d $f29, t1 |
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| 443 | movgr2fr.d $f30, t1 |
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| 444 | movgr2fr.d $f31, t1 |
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| 445 | |
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| 446 | jr ra |
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| 447 | SYM_FUNC_END(_init_fpu) |
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| 448 | |
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| 449 | /* |
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| 450 | * a0: fpregs |
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| 451 | * a1: fcc |
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| 452 | * a2: fcsr |
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| 453 | */ |
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| 454 | SYM_FUNC_START(_save_fp_context) |
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| 455 | sc_save_fcc a1 t1 t2 |
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| 456 | sc_save_fcsr a2 t1 |
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| 457 | sc_save_fp a0 |
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| 458 | li.w a0, 0 # success |
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| 459 | jr ra |
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| 460 | SYM_FUNC_END(_save_fp_context) |
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| 461 | |
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| 462 | /* |
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| 463 | * a0: fpregs |
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| 464 | * a1: fcc |
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| 465 | * a2: fcsr |
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| 466 | */ |
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| 467 | SYM_FUNC_START(_restore_fp_context) |
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| 468 | sc_restore_fp a0 |
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| 469 | sc_restore_fcc a1 t1 t2 |
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| 470 | sc_restore_fcsr a2 t1 |
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| 471 | li.w a0, 0 # success |
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| 472 | jr ra |
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| 473 | SYM_FUNC_END(_restore_fp_context) |
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| 474 | |
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| 475 | /* |
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| 476 | * a0: fpregs |
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| 477 | * a1: fcc |
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| 478 | * a2: fcsr |
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| 479 | */ |
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| 480 | SYM_FUNC_START(_save_lsx_context) |
|---|
| 481 | sc_save_fcc a1, t0, t1 |
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| 482 | sc_save_fcsr a2, t0 |
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| 483 | sc_save_lsx a0 |
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| 484 | li.w a0, 0 # success |
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| 485 | jr ra |
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| 486 | SYM_FUNC_END(_save_lsx_context) |
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| 487 | |
|---|
| 488 | /* |
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| 489 | * a0: fpregs |
|---|
| 490 | * a1: fcc |
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| 491 | * a2: fcsr |
|---|
| 492 | */ |
|---|
| 493 | SYM_FUNC_START(_restore_lsx_context) |
|---|
| 494 | sc_restore_lsx a0 |
|---|
| 495 | sc_restore_fcc a1, t1, t2 |
|---|
| 496 | sc_restore_fcsr a2, t1 |
|---|
| 497 | li.w a0, 0 # success |
|---|
| 498 | jr ra |
|---|
| 499 | SYM_FUNC_END(_restore_lsx_context) |
|---|
| 500 | |
|---|
| 501 | /* |
|---|
| 502 | * a0: fpregs |
|---|
| 503 | * a1: fcc |
|---|
| 504 | * a2: fcsr |
|---|
| 505 | */ |
|---|
| 506 | SYM_FUNC_START(_save_lasx_context) |
|---|
| 507 | sc_save_fcc a1, t0, t1 |
|---|
| 508 | sc_save_fcsr a2, t0 |
|---|
| 509 | sc_save_lasx a0 |
|---|
| 510 | li.w a0, 0 # success |
|---|
| 511 | jr ra |
|---|
| 512 | SYM_FUNC_END(_save_lasx_context) |
|---|
| 513 | |
|---|
| 514 | /* |
|---|
| 515 | * a0: fpregs |
|---|
| 516 | * a1: fcc |
|---|
| 517 | * a2: fcsr |
|---|
| 518 | */ |
|---|
| 519 | SYM_FUNC_START(_restore_lasx_context) |
|---|
| 520 | sc_restore_lasx a0 |
|---|
| 521 | sc_restore_fcc a1, t1, t2 |
|---|
| 522 | sc_restore_fcsr a2, t1 |
|---|
| 523 | li.w a0, 0 # success |
|---|
| 524 | jr ra |
|---|
| 525 | SYM_FUNC_END(_restore_lasx_context) |
|---|
| 526 | |
|---|
| 527 | .L_fpu_fault: |
|---|
| 528 | li.w a0, -EFAULT # failure |
|---|
| 529 | jr ra |
|---|
| 530 | |
|---|
| 531 | #ifdef CONFIG_CPU_HAS_LBT |
|---|
| 532 | STACK_FRAME_NON_STANDARD _restore_fp |
|---|
| 533 | STACK_FRAME_NON_STANDARD _restore_lsx |
|---|
| 534 | STACK_FRAME_NON_STANDARD _restore_lasx |
|---|
| 535 | #endif |
|---|
| 536 | |
|---|
