| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * This file contains low level CPU setup functions. |
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| 4 | * Valentine Barshak <vbarshak@ru.mvista.com> |
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| 5 | * MontaVista Software, Inc (c) 2007 |
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| 6 | * |
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| 7 | * Based on cpu_setup_6xx code by |
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| 8 | * Benjamin Herrenschmidt <benh@kernel.crashing.org> |
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| 9 | */ |
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| 10 | |
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| 11 | #include <asm/processor.h> |
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| 12 | #include <asm/cputable.h> |
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| 13 | #include <asm/ppc_asm.h> |
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| 14 | |
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| 15 | _GLOBAL(__setup_cpu_440ep) |
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| 16 | b __init_fpu_44x |
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| 17 | _GLOBAL(__setup_cpu_440epx) |
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| 18 | mflr r4 |
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| 19 | bl __init_fpu_44x |
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| 20 | bl __plb_disable_wrp |
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| 21 | bl __fixup_440A_mcheck |
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| 22 | mtlr r4 |
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| 23 | blr |
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| 24 | _GLOBAL(__setup_cpu_440grx) |
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| 25 | mflr r4 |
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| 26 | bl __plb_disable_wrp |
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| 27 | bl __fixup_440A_mcheck |
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| 28 | mtlr r4 |
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| 29 | blr |
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| 30 | _GLOBAL(__setup_cpu_460ex) |
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| 31 | _GLOBAL(__setup_cpu_460gt) |
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| 32 | _GLOBAL(__setup_cpu_460sx) |
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| 33 | _GLOBAL(__setup_cpu_apm821xx) |
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| 34 | mflr r4 |
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| 35 | bl __init_fpu_44x |
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| 36 | bl __fixup_440A_mcheck |
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| 37 | mtlr r4 |
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| 38 | blr |
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| 39 | |
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| 40 | _GLOBAL(__setup_cpu_440x5) |
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| 41 | _GLOBAL(__setup_cpu_440gx) |
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| 42 | _GLOBAL(__setup_cpu_440spe) |
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| 43 | b __fixup_440A_mcheck |
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| 44 | |
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| 45 | /* enable APU between CPU and FPU */ |
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| 46 | _GLOBAL(__init_fpu_44x) |
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| 47 | mfspr r3,SPRN_CCR0 |
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| 48 | /* Clear DAPUIB flag in CCR0 */ |
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| 49 | rlwinm r3,r3,0,12,10 |
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| 50 | mtspr SPRN_CCR0,r3 |
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| 51 | isync |
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| 52 | blr |
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| 53 | |
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| 54 | /* |
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| 55 | * Workaround for the incorrect write to DDR SDRAM errata. |
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| 56 | * The write address can be corrupted during writes to |
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| 57 | * DDR SDRAM when write pipelining is enabled on PLB0. |
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| 58 | * Disable write pipelining here. |
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| 59 | */ |
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| 60 | #define DCRN_PLB4A0_ACR 0x81 |
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| 61 | |
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| 62 | _GLOBAL(__plb_disable_wrp) |
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| 63 | mfdcr r3,DCRN_PLB4A0_ACR |
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| 64 | /* clear WRP bit in PLB4A0_ACR */ |
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| 65 | rlwinm r3,r3,0,8,6 |
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| 66 | mtdcr DCRN_PLB4A0_ACR,r3 |
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| 67 | isync |
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| 68 | blr |
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| 69 | |
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| 70 | |
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