| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved. |
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| 4 | * Dave Liu <daveliu@freescale.com> |
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| 5 | * copy from idle_6xx.S and modify for e500 based processor, |
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| 6 | * implement the power_save function in idle. |
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| 7 | */ |
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| 8 | |
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| 9 | #include <linux/threads.h> |
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| 10 | #include <asm/reg.h> |
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| 11 | #include <asm/page.h> |
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| 12 | #include <asm/cputable.h> |
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| 13 | #include <asm/thread_info.h> |
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| 14 | #include <asm/ppc_asm.h> |
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| 15 | #include <asm/asm-offsets.h> |
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| 16 | #include <asm/feature-fixups.h> |
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| 17 | |
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| 18 | .text |
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| 19 | |
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| 20 | _GLOBAL(e500_idle) |
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| 21 | lwz r4,TI_LOCAL_FLAGS(r2) /* set napping bit */ |
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| 22 | ori r4,r4,_TLF_NAPPING /* so when we take an exception */ |
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| 23 | stw r4,TI_LOCAL_FLAGS(r2) /* it will return to our caller */ |
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| 24 | |
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| 25 | #ifdef CONFIG_PPC_E500MC |
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| 26 | wrteei 1 |
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| 27 | 1: wait |
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| 28 | |
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| 29 | /* |
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| 30 | * Guard against spurious wakeups (e.g. from a hypervisor) -- |
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| 31 | * any real interrupt will cause us to return to LR due to |
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| 32 | * _TLF_NAPPING. |
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| 33 | */ |
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| 34 | b 1b |
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| 35 | #else |
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| 36 | /* Check if we can nap or doze, put HID0 mask in r3 */ |
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| 37 | lis r3,0 |
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| 38 | BEGIN_FTR_SECTION |
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| 39 | lis r3,HID0_DOZE@h |
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| 40 | END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE) |
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| 41 | |
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| 42 | BEGIN_FTR_SECTION |
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| 43 | /* Now check if user enabled NAP mode */ |
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| 44 | lis r4,powersave_nap@ha |
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| 45 | lwz r4,powersave_nap@l(r4) |
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| 46 | cmpwi 0,r4,0 |
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| 47 | beq 1f |
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| 48 | stwu r1,-16(r1) |
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| 49 | mflr r0 |
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| 50 | stw r0,20(r1) |
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| 51 | bl flush_dcache_L1 |
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| 52 | lwz r0,20(r1) |
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| 53 | addi r1,r1,16 |
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| 54 | mtlr r0 |
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| 55 | lis r3,HID0_NAP@h |
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| 56 | END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP) |
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| 57 | 1: |
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| 58 | /* Go to NAP or DOZE now */ |
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| 59 | mfspr r4,SPRN_HID0 |
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| 60 | rlwinm r4,r4,0,~(HID0_DOZE|HID0_NAP|HID0_SLEEP) |
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| 61 | or r4,r4,r3 |
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| 62 | isync |
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| 63 | mtspr SPRN_HID0,r4 |
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| 64 | isync |
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| 65 | |
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| 66 | mfmsr r7 |
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| 67 | oris r7,r7,MSR_WE@h |
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| 68 | ori r7,r7,MSR_EE |
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| 69 | msync |
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| 70 | mtmsr r7 |
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| 71 | isync |
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| 72 | 2: b 2b |
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| 73 | #endif /* !E500MC */ |
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| 74 | |
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| 75 | /* |
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| 76 | * Return from NAP/DOZE mode, restore some CPU specific registers, |
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| 77 | * r2 containing address of current. |
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| 78 | * r11 points to the exception frame. |
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| 79 | * We have to preserve r10. |
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| 80 | */ |
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| 81 | _GLOBAL(power_save_ppc32_restore) |
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| 82 | lwz r9,_LINK(r11) /* interrupted in e500_idle */ |
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| 83 | stw r9,_NIP(r11) /* make it do a blr */ |
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| 84 | blr |
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| 85 | _ASM_NOKPROBE_SYMBOL(power_save_ppc32_restore) |
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| 86 | |
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