| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | #include <linux/threads.h> |
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| 3 | #include <linux/linkage.h> |
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| 4 | |
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| 5 | #include <asm/processor.h> |
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| 6 | #include <asm/page.h> |
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| 7 | #include <asm/cputable.h> |
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| 8 | #include <asm/thread_info.h> |
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| 9 | #include <asm/ppc_asm.h> |
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| 10 | #include <asm/asm-offsets.h> |
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| 11 | #include <asm/mmu.h> |
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| 12 | #include <asm/feature-fixups.h> |
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| 13 | |
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| 14 | /* |
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| 15 | * Structure for storing CPU registers on the save area. |
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| 16 | */ |
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| 17 | #define SL_SP 0 |
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| 18 | #define SL_PC 4 |
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| 19 | #define SL_MSR 8 |
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| 20 | #define SL_SDR1 0xc |
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| 21 | #define SL_SPRG0 0x10 /* 4 sprg's */ |
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| 22 | #define SL_DBAT0 0x20 |
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| 23 | #define SL_IBAT0 0x28 |
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| 24 | #define SL_DBAT1 0x30 |
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| 25 | #define SL_IBAT1 0x38 |
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| 26 | #define SL_DBAT2 0x40 |
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| 27 | #define SL_IBAT2 0x48 |
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| 28 | #define SL_DBAT3 0x50 |
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| 29 | #define SL_IBAT3 0x58 |
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| 30 | #define SL_DBAT4 0x60 |
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| 31 | #define SL_IBAT4 0x68 |
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| 32 | #define SL_DBAT5 0x70 |
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| 33 | #define SL_IBAT5 0x78 |
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| 34 | #define SL_DBAT6 0x80 |
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| 35 | #define SL_IBAT6 0x88 |
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| 36 | #define SL_DBAT7 0x90 |
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| 37 | #define SL_IBAT7 0x98 |
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| 38 | #define SL_TB 0xa0 |
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| 39 | #define SL_R2 0xa8 |
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| 40 | #define SL_CR 0xac |
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| 41 | #define SL_LR 0xb0 |
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| 42 | #define SL_R12 0xb4 /* r12 to r31 */ |
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| 43 | #define SL_SIZE (SL_R12 + 80) |
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| 44 | |
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| 45 | .section .data |
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| 46 | .align 5 |
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| 47 | |
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| 48 | _GLOBAL(swsusp_save_area) |
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| 49 | .space SL_SIZE |
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| 50 | |
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| 51 | |
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| 52 | .section .text |
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| 53 | .align 5 |
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| 54 | |
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| 55 | _GLOBAL(swsusp_arch_suspend) |
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| 56 | |
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| 57 | lis r11,swsusp_save_area@h |
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| 58 | ori r11,r11,swsusp_save_area@l |
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| 59 | |
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| 60 | mflr r0 |
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| 61 | stw r0,SL_LR(r11) |
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| 62 | mfcr r0 |
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| 63 | stw r0,SL_CR(r11) |
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| 64 | stw r1,SL_SP(r11) |
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| 65 | stw r2,SL_R2(r11) |
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| 66 | stmw r12,SL_R12(r11) |
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| 67 | |
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| 68 | /* Save MSR & SDR1 */ |
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| 69 | mfmsr r4 |
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| 70 | stw r4,SL_MSR(r11) |
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| 71 | mfsdr1 r4 |
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| 72 | stw r4,SL_SDR1(r11) |
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| 73 | |
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| 74 | /* Get a stable timebase and save it */ |
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| 75 | 1: mftbu r4 |
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| 76 | stw r4,SL_TB(r11) |
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| 77 | mftb r5 |
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| 78 | stw r5,SL_TB+4(r11) |
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| 79 | mftbu r3 |
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| 80 | cmpw r3,r4 |
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| 81 | bne 1b |
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| 82 | |
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| 83 | /* Save SPRGs */ |
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| 84 | mfsprg r4,0 |
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| 85 | stw r4,SL_SPRG0(r11) |
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| 86 | mfsprg r4,1 |
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| 87 | stw r4,SL_SPRG0+4(r11) |
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| 88 | mfsprg r4,2 |
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| 89 | stw r4,SL_SPRG0+8(r11) |
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| 90 | mfsprg r4,3 |
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| 91 | stw r4,SL_SPRG0+12(r11) |
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| 92 | |
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| 93 | /* Save BATs */ |
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| 94 | mfdbatu r4,0 |
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| 95 | stw r4,SL_DBAT0(r11) |
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| 96 | mfdbatl r4,0 |
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| 97 | stw r4,SL_DBAT0+4(r11) |
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| 98 | mfdbatu r4,1 |
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| 99 | stw r4,SL_DBAT1(r11) |
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| 100 | mfdbatl r4,1 |
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| 101 | stw r4,SL_DBAT1+4(r11) |
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| 102 | mfdbatu r4,2 |
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| 103 | stw r4,SL_DBAT2(r11) |
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| 104 | mfdbatl r4,2 |
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| 105 | stw r4,SL_DBAT2+4(r11) |
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| 106 | mfdbatu r4,3 |
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| 107 | stw r4,SL_DBAT3(r11) |
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| 108 | mfdbatl r4,3 |
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| 109 | stw r4,SL_DBAT3+4(r11) |
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| 110 | mfibatu r4,0 |
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| 111 | stw r4,SL_IBAT0(r11) |
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| 112 | mfibatl r4,0 |
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| 113 | stw r4,SL_IBAT0+4(r11) |
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| 114 | mfibatu r4,1 |
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| 115 | stw r4,SL_IBAT1(r11) |
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| 116 | mfibatl r4,1 |
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| 117 | stw r4,SL_IBAT1+4(r11) |
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| 118 | mfibatu r4,2 |
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| 119 | stw r4,SL_IBAT2(r11) |
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| 120 | mfibatl r4,2 |
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| 121 | stw r4,SL_IBAT2+4(r11) |
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| 122 | mfibatu r4,3 |
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| 123 | stw r4,SL_IBAT3(r11) |
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| 124 | mfibatl r4,3 |
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| 125 | stw r4,SL_IBAT3+4(r11) |
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| 126 | |
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| 127 | BEGIN_MMU_FTR_SECTION |
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| 128 | mfspr r4,SPRN_DBAT4U |
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| 129 | stw r4,SL_DBAT4(r11) |
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| 130 | mfspr r4,SPRN_DBAT4L |
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| 131 | stw r4,SL_DBAT4+4(r11) |
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| 132 | mfspr r4,SPRN_DBAT5U |
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| 133 | stw r4,SL_DBAT5(r11) |
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| 134 | mfspr r4,SPRN_DBAT5L |
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| 135 | stw r4,SL_DBAT5+4(r11) |
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| 136 | mfspr r4,SPRN_DBAT6U |
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| 137 | stw r4,SL_DBAT6(r11) |
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| 138 | mfspr r4,SPRN_DBAT6L |
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| 139 | stw r4,SL_DBAT6+4(r11) |
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| 140 | mfspr r4,SPRN_DBAT7U |
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| 141 | stw r4,SL_DBAT7(r11) |
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| 142 | mfspr r4,SPRN_DBAT7L |
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| 143 | stw r4,SL_DBAT7+4(r11) |
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| 144 | mfspr r4,SPRN_IBAT4U |
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| 145 | stw r4,SL_IBAT4(r11) |
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| 146 | mfspr r4,SPRN_IBAT4L |
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| 147 | stw r4,SL_IBAT4+4(r11) |
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| 148 | mfspr r4,SPRN_IBAT5U |
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| 149 | stw r4,SL_IBAT5(r11) |
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| 150 | mfspr r4,SPRN_IBAT5L |
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| 151 | stw r4,SL_IBAT5+4(r11) |
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| 152 | mfspr r4,SPRN_IBAT6U |
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| 153 | stw r4,SL_IBAT6(r11) |
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| 154 | mfspr r4,SPRN_IBAT6L |
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| 155 | stw r4,SL_IBAT6+4(r11) |
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| 156 | mfspr r4,SPRN_IBAT7U |
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| 157 | stw r4,SL_IBAT7(r11) |
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| 158 | mfspr r4,SPRN_IBAT7L |
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| 159 | stw r4,SL_IBAT7+4(r11) |
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| 160 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
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| 161 | |
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| 162 | #if 0 |
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| 163 | /* Backup various CPU config stuffs */ |
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| 164 | bl __save_cpu_setup |
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| 165 | #endif |
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| 166 | /* Call the low level suspend stuff (we should probably have made |
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| 167 | * a stackframe... |
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| 168 | */ |
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| 169 | bl swsusp_save |
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| 170 | |
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| 171 | /* Restore LR from the save area */ |
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| 172 | lis r11,swsusp_save_area@h |
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| 173 | ori r11,r11,swsusp_save_area@l |
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| 174 | lwz r0,SL_LR(r11) |
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| 175 | mtlr r0 |
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| 176 | |
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| 177 | blr |
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| 178 | |
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| 179 | |
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| 180 | /* Resume code */ |
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| 181 | _GLOBAL(swsusp_arch_resume) |
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| 182 | |
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| 183 | #ifdef CONFIG_ALTIVEC |
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| 184 | /* Stop pending alitvec streams and memory accesses */ |
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| 185 | BEGIN_FTR_SECTION |
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| 186 | PPC_DSSALL |
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| 187 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) |
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| 188 | #endif |
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| 189 | sync |
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| 190 | |
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| 191 | /* Disable MSR:DR to make sure we don't take a TLB or |
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| 192 | * hash miss during the copy, as our hash table will |
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| 193 | * for a while be unusable. For .text, we assume we are |
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| 194 | * covered by a BAT. This works only for non-G5 at this |
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| 195 | * point. G5 will need a better approach, possibly using |
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| 196 | * a small temporary hash table filled with large mappings, |
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| 197 | * disabling the MMU completely isn't a good option for |
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| 198 | * performance reasons. |
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| 199 | * (Note that 750's may have the same performance issue as |
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| 200 | * the G5 in this case, we should investigate using moving |
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| 201 | * BATs for these CPUs) |
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| 202 | */ |
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| 203 | mfmsr r0 |
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| 204 | sync |
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| 205 | rlwinm r0,r0,0,28,26 /* clear MSR_DR */ |
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| 206 | mtmsr r0 |
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| 207 | sync |
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| 208 | isync |
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| 209 | |
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| 210 | /* Load ptr the list of pages to copy in r3 */ |
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| 211 | lis r11,(restore_pblist - KERNELBASE)@h |
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| 212 | ori r11,r11,restore_pblist@l |
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| 213 | lwz r10,0(r11) |
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| 214 | |
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| 215 | /* Copy the pages. This is a very basic implementation, to |
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| 216 | * be replaced by something more cache efficient */ |
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| 217 | 1: |
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| 218 | tophys(r3,r10) |
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| 219 | li r0,256 |
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| 220 | mtctr r0 |
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| 221 | lwz r11,pbe_address(r3) /* source */ |
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| 222 | tophys(r5,r11) |
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| 223 | lwz r10,pbe_orig_address(r3) /* destination */ |
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| 224 | tophys(r6,r10) |
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| 225 | 2: |
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| 226 | lwz r8,0(r5) |
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| 227 | lwz r9,4(r5) |
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| 228 | lwz r10,8(r5) |
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| 229 | lwz r11,12(r5) |
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| 230 | addi r5,r5,16 |
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| 231 | stw r8,0(r6) |
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| 232 | stw r9,4(r6) |
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| 233 | stw r10,8(r6) |
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| 234 | stw r11,12(r6) |
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| 235 | addi r6,r6,16 |
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| 236 | bdnz 2b |
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| 237 | lwz r10,pbe_next(r3) |
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| 238 | cmpwi 0,r10,0 |
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| 239 | bne 1b |
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| 240 | |
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| 241 | /* Do a very simple cache flush/inval of the L1 to ensure |
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| 242 | * coherency of the icache |
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| 243 | */ |
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| 244 | lis r3,0x0002 |
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| 245 | mtctr r3 |
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| 246 | li r3, 0 |
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| 247 | 1: |
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| 248 | lwz r0,0(r3) |
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| 249 | addi r3,r3,0x0020 |
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| 250 | bdnz 1b |
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| 251 | isync |
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| 252 | sync |
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| 253 | |
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| 254 | /* Now flush those cache lines */ |
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| 255 | lis r3,0x0002 |
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| 256 | mtctr r3 |
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| 257 | li r3, 0 |
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| 258 | 1: |
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| 259 | dcbf 0,r3 |
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| 260 | addi r3,r3,0x0020 |
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| 261 | bdnz 1b |
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| 262 | sync |
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| 263 | |
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| 264 | /* Ok, we are now running with the kernel data of the old |
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| 265 | * kernel fully restored. We can get to the save area |
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| 266 | * easily now. As for the rest of the code, it assumes the |
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| 267 | * loader kernel and the booted one are exactly identical |
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| 268 | */ |
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| 269 | lis r11,swsusp_save_area@h |
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| 270 | ori r11,r11,swsusp_save_area@l |
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| 271 | tophys(r11,r11) |
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| 272 | |
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| 273 | #if 0 |
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| 274 | /* Restore various CPU config stuffs */ |
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| 275 | bl __restore_cpu_setup |
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| 276 | #endif |
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| 277 | /* Restore the BATs, and SDR1. Then we can turn on the MMU. |
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| 278 | * This is a bit hairy as we are running out of those BATs, |
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| 279 | * but first, our code is probably in the icache, and we are |
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| 280 | * writing the same value to the BAT, so that should be fine, |
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| 281 | * though a better solution will have to be found long-term |
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| 282 | */ |
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| 283 | lwz r4,SL_SDR1(r11) |
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| 284 | mtsdr1 r4 |
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| 285 | lwz r4,SL_SPRG0(r11) |
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| 286 | mtsprg 0,r4 |
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| 287 | lwz r4,SL_SPRG0+4(r11) |
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| 288 | mtsprg 1,r4 |
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| 289 | lwz r4,SL_SPRG0+8(r11) |
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| 290 | mtsprg 2,r4 |
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| 291 | lwz r4,SL_SPRG0+12(r11) |
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| 292 | mtsprg 3,r4 |
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| 293 | |
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| 294 | #if 0 |
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| 295 | lwz r4,SL_DBAT0(r11) |
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| 296 | mtdbatu 0,r4 |
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| 297 | lwz r4,SL_DBAT0+4(r11) |
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| 298 | mtdbatl 0,r4 |
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| 299 | lwz r4,SL_DBAT1(r11) |
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| 300 | mtdbatu 1,r4 |
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| 301 | lwz r4,SL_DBAT1+4(r11) |
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| 302 | mtdbatl 1,r4 |
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| 303 | lwz r4,SL_DBAT2(r11) |
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| 304 | mtdbatu 2,r4 |
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| 305 | lwz r4,SL_DBAT2+4(r11) |
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| 306 | mtdbatl 2,r4 |
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| 307 | lwz r4,SL_DBAT3(r11) |
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| 308 | mtdbatu 3,r4 |
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| 309 | lwz r4,SL_DBAT3+4(r11) |
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| 310 | mtdbatl 3,r4 |
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| 311 | lwz r4,SL_IBAT0(r11) |
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| 312 | mtibatu 0,r4 |
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| 313 | lwz r4,SL_IBAT0+4(r11) |
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| 314 | mtibatl 0,r4 |
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| 315 | lwz r4,SL_IBAT1(r11) |
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| 316 | mtibatu 1,r4 |
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| 317 | lwz r4,SL_IBAT1+4(r11) |
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| 318 | mtibatl 1,r4 |
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| 319 | lwz r4,SL_IBAT2(r11) |
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| 320 | mtibatu 2,r4 |
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| 321 | lwz r4,SL_IBAT2+4(r11) |
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| 322 | mtibatl 2,r4 |
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| 323 | lwz r4,SL_IBAT3(r11) |
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| 324 | mtibatu 3,r4 |
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| 325 | lwz r4,SL_IBAT3+4(r11) |
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| 326 | mtibatl 3,r4 |
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| 327 | BEGIN_MMU_FTR_SECTION |
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| 328 | lwz r4,SL_DBAT4(r11) |
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| 329 | mtspr SPRN_DBAT4U,r4 |
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| 330 | lwz r4,SL_DBAT4+4(r11) |
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| 331 | mtspr SPRN_DBAT4L,r4 |
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| 332 | lwz r4,SL_DBAT5(r11) |
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| 333 | mtspr SPRN_DBAT5U,r4 |
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| 334 | lwz r4,SL_DBAT5+4(r11) |
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| 335 | mtspr SPRN_DBAT5L,r4 |
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| 336 | lwz r4,SL_DBAT6(r11) |
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| 337 | mtspr SPRN_DBAT6U,r4 |
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| 338 | lwz r4,SL_DBAT6+4(r11) |
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| 339 | mtspr SPRN_DBAT6L,r4 |
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| 340 | lwz r4,SL_DBAT7(r11) |
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| 341 | mtspr SPRN_DBAT7U,r4 |
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| 342 | lwz r4,SL_DBAT7+4(r11) |
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| 343 | mtspr SPRN_DBAT7L,r4 |
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| 344 | lwz r4,SL_IBAT4(r11) |
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| 345 | mtspr SPRN_IBAT4U,r4 |
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| 346 | lwz r4,SL_IBAT4+4(r11) |
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| 347 | mtspr SPRN_IBAT4L,r4 |
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| 348 | lwz r4,SL_IBAT5(r11) |
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| 349 | mtspr SPRN_IBAT5U,r4 |
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| 350 | lwz r4,SL_IBAT5+4(r11) |
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| 351 | mtspr SPRN_IBAT5L,r4 |
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| 352 | lwz r4,SL_IBAT6(r11) |
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| 353 | mtspr SPRN_IBAT6U,r4 |
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| 354 | lwz r4,SL_IBAT6+4(r11) |
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| 355 | mtspr SPRN_IBAT6L,r4 |
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| 356 | lwz r4,SL_IBAT7(r11) |
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| 357 | mtspr SPRN_IBAT7U,r4 |
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| 358 | lwz r4,SL_IBAT7+4(r11) |
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| 359 | mtspr SPRN_IBAT7L,r4 |
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| 360 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
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| 361 | #endif |
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| 362 | |
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| 363 | /* Flush all TLBs */ |
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| 364 | lis r4,0x1000 |
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| 365 | 1: addic. r4,r4,-0x1000 |
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| 366 | tlbie r4 |
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| 367 | bgt 1b |
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| 368 | sync |
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| 369 | |
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| 370 | /* restore the MSR and turn on the MMU */ |
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| 371 | lwz r3,SL_MSR(r11) |
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| 372 | bl turn_on_mmu |
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| 373 | tovirt(r11,r11) |
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| 374 | |
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| 375 | /* Restore TB */ |
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| 376 | li r3,0 |
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| 377 | mttbl r3 |
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| 378 | lwz r3,SL_TB(r11) |
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| 379 | lwz r4,SL_TB+4(r11) |
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| 380 | mttbu r3 |
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| 381 | mttbl r4 |
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| 382 | |
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| 383 | /* Kick decrementer */ |
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| 384 | li r0,1 |
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| 385 | mtdec r0 |
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| 386 | |
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| 387 | /* Restore the callee-saved registers and return */ |
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| 388 | lwz r0,SL_CR(r11) |
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| 389 | mtcr r0 |
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| 390 | lwz r2,SL_R2(r11) |
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| 391 | lmw r12,SL_R12(r11) |
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| 392 | lwz r1,SL_SP(r11) |
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| 393 | lwz r0,SL_LR(r11) |
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| 394 | mtlr r0 |
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| 395 | |
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| 396 | // XXX Note: we don't really need to call swsusp_resume |
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| 397 | |
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| 398 | li r3,0 |
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| 399 | blr |
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| 400 | _ASM_NOKPROBE_SYMBOL(swsusp_arch_resume) |
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| 401 | |
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| 402 | /* FIXME:This construct is actually not useful since we don't shut |
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| 403 | * down the instruction MMU, we could just flip back MSR-DR on. |
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| 404 | */ |
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| 405 | SYM_FUNC_START_LOCAL(turn_on_mmu) |
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| 406 | mflr r4 |
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| 407 | mtsrr0 r4 |
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| 408 | mtsrr1 r3 |
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| 409 | sync |
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| 410 | isync |
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| 411 | rfi |
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| 412 | _ASM_NOKPROBE_SYMBOL(turn_on_mmu) |
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| 413 | SYM_FUNC_END(turn_on_mmu) |
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| 414 | |
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| 415 | |
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