| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Signal trampoline for 64 bits processes in a ppc64 kernel for |
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| 4 | * use in the vDSO |
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| 5 | * |
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| 6 | * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp. |
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| 7 | * Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp. |
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| 8 | */ |
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| 9 | #include <asm/cache.h> /* IFETCH_ALIGN_BYTES */ |
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| 10 | #include <asm/processor.h> |
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| 11 | #include <asm/ppc_asm.h> |
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| 12 | #include <asm/unistd.h> |
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| 13 | #include <asm/vdso.h> |
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| 14 | #include <asm/ptrace.h> /* XXX for __SIGNAL_FRAMESIZE */ |
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| 15 | |
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| 16 | .text |
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| 17 | |
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| 18 | /* |
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| 19 | * __kernel_start_sigtramp_rt64 and __kernel_sigtramp_rt64 together |
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| 20 | * are one function split in two parts. The kernel jumps to the former |
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| 21 | * and the signal handler indirectly (by blr) returns to the latter. |
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| 22 | * __kernel_sigtramp_rt64 needs to point to the return address so |
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| 23 | * glibc can correctly identify the trampoline stack frame. |
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| 24 | */ |
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| 25 | .balign 8 |
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| 26 | .balign IFETCH_ALIGN_BYTES |
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| 27 | V_FUNCTION_BEGIN(__kernel_start_sigtramp_rt64) |
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| 28 | .Lsigrt_start: |
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| 29 | bctrl /* call the handler */ |
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| 30 | V_FUNCTION_END(__kernel_start_sigtramp_rt64) |
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| 31 | V_FUNCTION_BEGIN(__kernel_sigtramp_rt64) |
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| 32 | addi r1, r1, __SIGNAL_FRAMESIZE |
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| 33 | li r0,__NR_rt_sigreturn |
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| 34 | sc |
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| 35 | .Lsigrt_end: |
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| 36 | V_FUNCTION_END(__kernel_sigtramp_rt64) |
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| 37 | /* The .balign 8 above and the following zeros mimic the old stack |
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| 38 | trampoline layout. The last magic value is the ucontext pointer, |
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| 39 | chosen in such a way that older libgcc unwind code returns a zero |
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| 40 | for a sigcontext pointer. */ |
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| 41 | .long 0,0,0 |
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| 42 | .quad 0,-21*8 |
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| 43 | |
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| 44 | /* Register r1 can be found at offset 8 of a pt_regs structure. |
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| 45 | A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */ |
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| 46 | #define cfa_save \ |
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| 47 | .byte 0x0f; /* DW_CFA_def_cfa_expression */ \ |
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| 48 | .uleb128 9f - 1f; /* length */ \ |
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| 49 | 1: \ |
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| 50 | .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \ |
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| 51 | .byte 0x06; /* DW_OP_deref */ \ |
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| 52 | .byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \ |
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| 53 | .byte 0x06; /* DW_OP_deref */ \ |
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| 54 | 9: |
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| 55 | |
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| 56 | /* Register REGNO can be found at offset OFS of a pt_regs structure. |
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| 57 | A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */ |
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| 58 | #define rsave(regno, ofs) \ |
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| 59 | .byte 0x10; /* DW_CFA_expression */ \ |
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| 60 | .uleb128 regno; /* regno */ \ |
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| 61 | .uleb128 9f - 1f; /* length */ \ |
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| 62 | 1: \ |
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| 63 | .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \ |
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| 64 | .byte 0x06; /* DW_OP_deref */ \ |
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| 65 | .ifne ofs; \ |
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| 66 | .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \ |
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| 67 | .endif; \ |
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| 68 | 9: |
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| 69 | |
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| 70 | /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16 |
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| 71 | of the VMX reg struct. A pointer to the VMX reg struct is at VREGS in |
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| 72 | the pt_regs struct. This macro is for REGNO == 0, and contains |
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| 73 | 'subroutines' that the other macros jump to. */ |
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| 74 | #define vsave_msr0(regno) \ |
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| 75 | .byte 0x10; /* DW_CFA_expression */ \ |
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| 76 | .uleb128 regno + 77; /* regno */ \ |
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| 77 | .uleb128 9f - 1f; /* length */ \ |
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| 78 | 1: \ |
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| 79 | .byte 0x30 + regno; /* DW_OP_lit0 */ \ |
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| 80 | 2: \ |
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| 81 | .byte 0x40; /* DW_OP_lit16 */ \ |
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| 82 | .byte 0x1e; /* DW_OP_mul */ \ |
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| 83 | 3: \ |
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| 84 | .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \ |
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| 85 | .byte 0x06; /* DW_OP_deref */ \ |
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| 86 | .byte 0x12; /* DW_OP_dup */ \ |
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| 87 | .byte 0x23; /* DW_OP_plus_uconst */ \ |
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| 88 | .uleb128 33*RSIZE; /* msr offset */ \ |
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| 89 | .byte 0x06; /* DW_OP_deref */ \ |
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| 90 | .byte 0x0c; .long 1 << 25; /* DW_OP_const4u */ \ |
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| 91 | .byte 0x1a; /* DW_OP_and */ \ |
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| 92 | .byte 0x12; /* DW_OP_dup, ret 0 if bra taken */ \ |
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| 93 | .byte 0x30; /* DW_OP_lit0 */ \ |
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| 94 | .byte 0x29; /* DW_OP_eq */ \ |
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| 95 | .byte 0x28; .short 0x7fff; /* DW_OP_bra to end */ \ |
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| 96 | .byte 0x13; /* DW_OP_drop, pop the 0 */ \ |
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| 97 | .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \ |
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| 98 | .byte 0x06; /* DW_OP_deref */ \ |
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| 99 | .byte 0x22; /* DW_OP_plus */ \ |
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| 100 | .byte 0x2f; .short 0x7fff; /* DW_OP_skip to end */ \ |
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| 101 | 9: |
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| 102 | |
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| 103 | /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16 |
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| 104 | of the VMX reg struct. REGNO is 1 thru 31. */ |
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| 105 | #define vsave_msr1(regno) \ |
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| 106 | .byte 0x10; /* DW_CFA_expression */ \ |
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| 107 | .uleb128 regno + 77; /* regno */ \ |
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| 108 | .uleb128 9f - 1f; /* length */ \ |
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| 109 | 1: \ |
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| 110 | .byte 0x30 + regno; /* DW_OP_lit n */ \ |
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| 111 | .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \ |
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| 112 | 9: |
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| 113 | |
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| 114 | /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of |
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| 115 | the VMX save block. */ |
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| 116 | #define vsave_msr2(regno, ofs) \ |
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| 117 | .byte 0x10; /* DW_CFA_expression */ \ |
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| 118 | .uleb128 regno + 77; /* regno */ \ |
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| 119 | .uleb128 9f - 1f; /* length */ \ |
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| 120 | 1: \ |
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| 121 | .byte 0x0a; .short ofs; /* DW_OP_const2u */ \ |
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| 122 | .byte 0x2f; .short 3b - 9f; /* DW_OP_skip */ \ |
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| 123 | 9: |
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| 124 | |
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| 125 | /* VMX register REGNO is at offset OFS of the VMX save area. */ |
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| 126 | #define vsave(regno, ofs) \ |
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| 127 | .byte 0x10; /* DW_CFA_expression */ \ |
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| 128 | .uleb128 regno + 77; /* regno */ \ |
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| 129 | .uleb128 9f - 1f; /* length */ \ |
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| 130 | 1: \ |
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| 131 | .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \ |
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| 132 | .byte 0x06; /* DW_OP_deref */ \ |
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| 133 | .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \ |
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| 134 | .byte 0x06; /* DW_OP_deref */ \ |
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| 135 | .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \ |
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| 136 | 9: |
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| 137 | |
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| 138 | /* This is where the pt_regs pointer can be found on the stack. */ |
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| 139 | #define PTREGS 128+168+56 |
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| 140 | |
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| 141 | /* Size of regs. */ |
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| 142 | #define RSIZE 8 |
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| 143 | |
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| 144 | /* Size of CR reg in DWARF unwind info. */ |
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| 145 | #define CRSIZE 4 |
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| 146 | |
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| 147 | /* Offset of CR reg within a full word. */ |
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| 148 | #ifdef __LITTLE_ENDIAN__ |
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| 149 | #define CROFF 0 |
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| 150 | #else |
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| 151 | #define CROFF (RSIZE - CRSIZE) |
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| 152 | #endif |
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| 153 | |
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| 154 | /* This is the offset of the VMX reg pointer. */ |
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| 155 | #define VREGS 48*RSIZE+33*8 |
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| 156 | |
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| 157 | /* Describe where general purpose regs are saved. */ |
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| 158 | #define EH_FRAME_GEN \ |
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| 159 | cfa_save; \ |
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| 160 | rsave ( 0, 0*RSIZE); \ |
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| 161 | rsave ( 2, 2*RSIZE); \ |
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| 162 | rsave ( 3, 3*RSIZE); \ |
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| 163 | rsave ( 4, 4*RSIZE); \ |
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| 164 | rsave ( 5, 5*RSIZE); \ |
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| 165 | rsave ( 6, 6*RSIZE); \ |
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| 166 | rsave ( 7, 7*RSIZE); \ |
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| 167 | rsave ( 8, 8*RSIZE); \ |
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| 168 | rsave ( 9, 9*RSIZE); \ |
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| 169 | rsave (10, 10*RSIZE); \ |
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| 170 | rsave (11, 11*RSIZE); \ |
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| 171 | rsave (12, 12*RSIZE); \ |
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| 172 | rsave (13, 13*RSIZE); \ |
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| 173 | rsave (14, 14*RSIZE); \ |
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| 174 | rsave (15, 15*RSIZE); \ |
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| 175 | rsave (16, 16*RSIZE); \ |
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| 176 | rsave (17, 17*RSIZE); \ |
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| 177 | rsave (18, 18*RSIZE); \ |
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| 178 | rsave (19, 19*RSIZE); \ |
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| 179 | rsave (20, 20*RSIZE); \ |
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| 180 | rsave (21, 21*RSIZE); \ |
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| 181 | rsave (22, 22*RSIZE); \ |
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| 182 | rsave (23, 23*RSIZE); \ |
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| 183 | rsave (24, 24*RSIZE); \ |
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| 184 | rsave (25, 25*RSIZE); \ |
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| 185 | rsave (26, 26*RSIZE); \ |
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| 186 | rsave (27, 27*RSIZE); \ |
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| 187 | rsave (28, 28*RSIZE); \ |
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| 188 | rsave (29, 29*RSIZE); \ |
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| 189 | rsave (30, 30*RSIZE); \ |
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| 190 | rsave (31, 31*RSIZE); \ |
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| 191 | rsave (67, 32*RSIZE); /* ap, used as temp for nip */ \ |
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| 192 | rsave (65, 36*RSIZE); /* lr */ \ |
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| 193 | rsave (68, 38*RSIZE + CROFF); /* cr fields */ \ |
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| 194 | rsave (69, 38*RSIZE + CROFF); \ |
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| 195 | rsave (70, 38*RSIZE + CROFF); \ |
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| 196 | rsave (71, 38*RSIZE + CROFF); \ |
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| 197 | rsave (72, 38*RSIZE + CROFF); \ |
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| 198 | rsave (73, 38*RSIZE + CROFF); \ |
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| 199 | rsave (74, 38*RSIZE + CROFF); \ |
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| 200 | rsave (75, 38*RSIZE + CROFF) |
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| 201 | |
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| 202 | /* Describe where the FP regs are saved. */ |
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| 203 | #define EH_FRAME_FP \ |
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| 204 | rsave (32, 48*RSIZE + 0*8); \ |
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| 205 | rsave (33, 48*RSIZE + 1*8); \ |
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| 206 | rsave (34, 48*RSIZE + 2*8); \ |
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| 207 | rsave (35, 48*RSIZE + 3*8); \ |
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| 208 | rsave (36, 48*RSIZE + 4*8); \ |
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| 209 | rsave (37, 48*RSIZE + 5*8); \ |
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| 210 | rsave (38, 48*RSIZE + 6*8); \ |
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| 211 | rsave (39, 48*RSIZE + 7*8); \ |
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| 212 | rsave (40, 48*RSIZE + 8*8); \ |
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| 213 | rsave (41, 48*RSIZE + 9*8); \ |
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| 214 | rsave (42, 48*RSIZE + 10*8); \ |
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| 215 | rsave (43, 48*RSIZE + 11*8); \ |
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| 216 | rsave (44, 48*RSIZE + 12*8); \ |
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| 217 | rsave (45, 48*RSIZE + 13*8); \ |
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| 218 | rsave (46, 48*RSIZE + 14*8); \ |
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| 219 | rsave (47, 48*RSIZE + 15*8); \ |
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| 220 | rsave (48, 48*RSIZE + 16*8); \ |
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| 221 | rsave (49, 48*RSIZE + 17*8); \ |
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| 222 | rsave (50, 48*RSIZE + 18*8); \ |
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| 223 | rsave (51, 48*RSIZE + 19*8); \ |
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| 224 | rsave (52, 48*RSIZE + 20*8); \ |
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| 225 | rsave (53, 48*RSIZE + 21*8); \ |
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| 226 | rsave (54, 48*RSIZE + 22*8); \ |
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| 227 | rsave (55, 48*RSIZE + 23*8); \ |
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| 228 | rsave (56, 48*RSIZE + 24*8); \ |
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| 229 | rsave (57, 48*RSIZE + 25*8); \ |
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| 230 | rsave (58, 48*RSIZE + 26*8); \ |
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| 231 | rsave (59, 48*RSIZE + 27*8); \ |
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| 232 | rsave (60, 48*RSIZE + 28*8); \ |
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| 233 | rsave (61, 48*RSIZE + 29*8); \ |
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| 234 | rsave (62, 48*RSIZE + 30*8); \ |
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| 235 | rsave (63, 48*RSIZE + 31*8) |
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| 236 | |
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| 237 | /* Describe where the VMX regs are saved. */ |
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| 238 | #ifdef CONFIG_ALTIVEC |
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| 239 | #define EH_FRAME_VMX \ |
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| 240 | vsave_msr0 ( 0); \ |
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| 241 | vsave_msr1 ( 1); \ |
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| 242 | vsave_msr1 ( 2); \ |
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| 243 | vsave_msr1 ( 3); \ |
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| 244 | vsave_msr1 ( 4); \ |
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| 245 | vsave_msr1 ( 5); \ |
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| 246 | vsave_msr1 ( 6); \ |
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| 247 | vsave_msr1 ( 7); \ |
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| 248 | vsave_msr1 ( 8); \ |
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| 249 | vsave_msr1 ( 9); \ |
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| 250 | vsave_msr1 (10); \ |
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| 251 | vsave_msr1 (11); \ |
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| 252 | vsave_msr1 (12); \ |
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| 253 | vsave_msr1 (13); \ |
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| 254 | vsave_msr1 (14); \ |
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| 255 | vsave_msr1 (15); \ |
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| 256 | vsave_msr1 (16); \ |
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| 257 | vsave_msr1 (17); \ |
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| 258 | vsave_msr1 (18); \ |
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| 259 | vsave_msr1 (19); \ |
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| 260 | vsave_msr1 (20); \ |
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| 261 | vsave_msr1 (21); \ |
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| 262 | vsave_msr1 (22); \ |
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| 263 | vsave_msr1 (23); \ |
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| 264 | vsave_msr1 (24); \ |
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| 265 | vsave_msr1 (25); \ |
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| 266 | vsave_msr1 (26); \ |
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| 267 | vsave_msr1 (27); \ |
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| 268 | vsave_msr1 (28); \ |
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| 269 | vsave_msr1 (29); \ |
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| 270 | vsave_msr1 (30); \ |
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| 271 | vsave_msr1 (31); \ |
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| 272 | vsave_msr2 (33, 32*16+12); \ |
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| 273 | vsave (32, 33*16) |
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| 274 | #else |
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| 275 | #define EH_FRAME_VMX |
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| 276 | #endif |
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| 277 | |
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| 278 | .section .eh_frame,"a" ,@progbits |
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| 279 | .Lcie: |
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| 280 | .long .Lcie_end - .Lcie_start |
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| 281 | .Lcie_start: |
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| 282 | .long 0 /* CIE ID */ |
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| 283 | .byte 1 /* Version number */ |
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| 284 | .string "zRS" /* NUL-terminated augmentation string */ |
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| 285 | .uleb128 4 /* Code alignment factor */ |
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| 286 | .sleb128 -8 /* Data alignment factor */ |
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| 287 | .byte 67 /* Return address register column, ap */ |
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| 288 | .uleb128 1 /* Augmentation value length */ |
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| 289 | .byte 0x14 /* DW_EH_PE_pcrel | DW_EH_PE_udata8. */ |
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| 290 | .byte 0x0c,1,0 /* DW_CFA_def_cfa: r1 ofs 0 */ |
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| 291 | .balign 8 |
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| 292 | .Lcie_end: |
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| 293 | |
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| 294 | .long .Lfde0_end - .Lfde0_start |
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| 295 | .Lfde0_start: |
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| 296 | .long .Lfde0_start - .Lcie /* CIE pointer. */ |
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| 297 | .quad .Lsigrt_start - . /* PC start, length */ |
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| 298 | .quad .Lsigrt_end - .Lsigrt_start |
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| 299 | .uleb128 0 /* Augmentation */ |
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| 300 | EH_FRAME_GEN |
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| 301 | EH_FRAME_FP |
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| 302 | EH_FRAME_VMX |
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| 303 | # Do we really need to describe the frame at this point? ie. will |
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| 304 | # we ever have some call chain that returns somewhere past the addi? |
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| 305 | # I don't think so, since gcc doesn't support async signals. |
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| 306 | # .byte 0x41 /* DW_CFA_advance_loc 1*4 */ |
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| 307 | #undef PTREGS |
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| 308 | #define PTREGS 168+56 |
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| 309 | # EH_FRAME_GEN |
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| 310 | # EH_FRAME_FP |
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| 311 | # EH_FRAME_VMX |
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| 312 | .balign 8 |
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| 313 | .Lfde0_end: |
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| 314 | |
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