| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Performance counter support for POWER10 processors. |
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| 4 | * |
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| 5 | * Copyright 2020 Madhavan Srinivasan, IBM Corporation. |
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| 6 | * Copyright 2020 Athira Rajeev, IBM Corporation. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Power10 event codes. |
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| 11 | */ |
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| 12 | EVENT(PM_CYC, 0x600f4); |
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| 13 | EVENT(PM_DISP_STALL_CYC, 0x100f8); |
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| 14 | EVENT(PM_EXEC_STALL, 0x30008); |
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| 15 | EVENT(PM_INST_CMPL, 0x500fa); |
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| 16 | EVENT(PM_BR_CMPL, 0x4d05e); |
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| 17 | EVENT(PM_BR_MPRED_CMPL, 0x400f6); |
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| 18 | EVENT(PM_BR_FIN, 0x2f04a); |
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| 19 | EVENT(PM_MPRED_BR_FIN, 0x3e098); |
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| 20 | EVENT(PM_LD_DEMAND_MISS_L1_FIN, 0x400f0); |
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| 21 | |
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| 22 | /* All L1 D cache load references counted at finish, gated by reject */ |
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| 23 | EVENT(PM_LD_REF_L1, 0x100fc); |
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| 24 | /* Load Missed L1 */ |
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| 25 | EVENT(PM_LD_MISS_L1, 0x3e054); |
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| 26 | /* Store Missed L1 */ |
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| 27 | EVENT(PM_ST_MISS_L1, 0x300f0); |
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| 28 | /* L1 cache data prefetches */ |
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| 29 | EVENT(PM_LD_PREFETCH_CACHE_LINE_MISS, 0x1002c); |
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| 30 | /* Demand iCache Miss */ |
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| 31 | EVENT(PM_L1_ICACHE_MISS, 0x200fc); |
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| 32 | /* Instruction fetches from L1 */ |
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| 33 | EVENT(PM_INST_FROM_L1, 0x04080); |
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| 34 | /* Instruction Demand sectors wriittent into IL1 */ |
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| 35 | EVENT(PM_INST_FROM_L1MISS, 0x03f00000001c040); |
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| 36 | /* Instruction prefetch written into IL1 */ |
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| 37 | EVENT(PM_IC_PREF_REQ, 0x040a0); |
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| 38 | /* The data cache was reloaded from local core's L3 due to a demand load */ |
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| 39 | EVENT(PM_DATA_FROM_L3, 0x01340000001c040); |
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| 40 | /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ |
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| 41 | EVENT(PM_DATA_FROM_L3MISS, 0x300fe); |
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| 42 | /* All successful D-side store dispatches for this thread */ |
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| 43 | EVENT(PM_L2_ST, 0x010000046080); |
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| 44 | /* All successful D-side store dispatches for this thread that were L2 Miss */ |
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| 45 | EVENT(PM_L2_ST_MISS, 0x26880); |
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| 46 | /* Total HW L3 prefetches(Load+store) */ |
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| 47 | EVENT(PM_L3_PF_MISS_L3, 0x100000016080); |
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| 48 | /* Data PTEG reload */ |
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| 49 | EVENT(PM_DTLB_MISS, 0x300fc); |
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| 50 | /* ITLB Reloaded */ |
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| 51 | EVENT(PM_ITLB_MISS, 0x400fc); |
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| 52 | |
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| 53 | EVENT(PM_CYC_ALT, 0x0001e); |
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| 54 | EVENT(PM_INST_CMPL_ALT, 0x00002); |
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| 55 | |
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| 56 | /* |
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| 57 | * Memory Access Events |
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| 58 | * |
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| 59 | * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0) |
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| 60 | * To enable capturing of memory profiling, these MMCRA bits |
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| 61 | * needs to be programmed and corresponding raw event format |
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| 62 | * encoding. |
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| 63 | * |
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| 64 | * MMCRA bits encoding needed are |
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| 65 | * SM (Sampling Mode) |
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| 66 | * EM (Eligibility for Random Sampling) |
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| 67 | * TECE (Threshold Event Counter Event) |
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| 68 | * TS (Threshold Start Event) |
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| 69 | * TE (Threshold End Event) |
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| 70 | * |
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| 71 | * Corresponding Raw Encoding bits: |
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| 72 | * sample [EM,SM] |
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| 73 | * thresh_sel (TECE) |
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| 74 | * thresh start (TS) |
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| 75 | * thresh end (TE) |
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| 76 | */ |
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| 77 | |
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| 78 | EVENT(MEM_LOADS, 0x35340401e0); |
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| 79 | EVENT(MEM_STORES, 0x353c0401e0); |
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| 80 | |
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