| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Performance counter support for POWER9 processors. |
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| 4 | * |
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| 5 | * Copyright 2016 Madhavan Srinivasan, IBM Corporation. |
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| 6 | */ |
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| 7 | |
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| 8 | /* |
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| 9 | * Power9 event codes. |
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| 10 | */ |
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| 11 | EVENT(PM_CYC, 0x0001e) |
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| 12 | EVENT(PM_ICT_NOSLOT_CYC, 0x100f8) |
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| 13 | EVENT(PM_CMPLU_STALL, 0x1e054) |
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| 14 | EVENT(PM_INST_CMPL, 0x00002) |
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| 15 | EVENT(PM_BR_CMPL, 0x4d05e) |
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| 16 | EVENT(PM_BR_MPRED_CMPL, 0x400f6) |
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| 17 | |
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| 18 | /* All L1 D cache load references counted at finish, gated by reject */ |
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| 19 | EVENT(PM_LD_REF_L1, 0x100fc) |
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| 20 | /* Load Missed L1 */ |
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| 21 | EVENT(PM_LD_MISS_L1_FIN, 0x2c04e) |
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| 22 | EVENT(PM_LD_MISS_L1, 0x3e054) |
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| 23 | /* Alternate event code for PM_LD_MISS_L1 */ |
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| 24 | EVENT(PM_LD_MISS_L1_ALT, 0x400f0) |
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| 25 | /* Store Missed L1 */ |
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| 26 | EVENT(PM_ST_MISS_L1, 0x300f0) |
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| 27 | /* L1 cache data prefetches */ |
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| 28 | EVENT(PM_L1_PREF, 0x20054) |
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| 29 | /* Instruction fetches from L1 */ |
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| 30 | EVENT(PM_INST_FROM_L1, 0x04080) |
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| 31 | /* Demand iCache Miss */ |
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| 32 | EVENT(PM_L1_ICACHE_MISS, 0x200fd) |
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| 33 | /* Instruction Demand sectors wriittent into IL1 */ |
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| 34 | EVENT(PM_L1_DEMAND_WRITE, 0x0408c) |
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| 35 | /* Instruction prefetch written into IL1 */ |
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| 36 | EVENT(PM_IC_PREF_WRITE, 0x0488c) |
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| 37 | /* The data cache was reloaded from local core's L3 due to a demand load */ |
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| 38 | EVENT(PM_DATA_FROM_L3, 0x4c042) |
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| 39 | /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ |
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| 40 | EVENT(PM_DATA_FROM_L3MISS, 0x300fe) |
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| 41 | /* All successful D-side store dispatches for this thread */ |
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| 42 | EVENT(PM_L2_ST, 0x16880) |
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| 43 | /* All successful D-side store dispatches for this thread that were L2 Miss */ |
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| 44 | EVENT(PM_L2_ST_MISS, 0x26880) |
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| 45 | /* Total HW L3 prefetches(Load+store) */ |
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| 46 | EVENT(PM_L3_PREF_ALL, 0x4e052) |
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| 47 | /* Data PTEG reload */ |
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| 48 | EVENT(PM_DTLB_MISS, 0x300fc) |
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| 49 | /* ITLB Reloaded */ |
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| 50 | EVENT(PM_ITLB_MISS, 0x400fc) |
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| 51 | /* Run_Instructions */ |
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| 52 | EVENT(PM_RUN_INST_CMPL, 0x500fa) |
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| 53 | /* Alternate event code for PM_RUN_INST_CMPL */ |
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| 54 | EVENT(PM_RUN_INST_CMPL_ALT, 0x400fa) |
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| 55 | /* Run_cycles */ |
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| 56 | EVENT(PM_RUN_CYC, 0x600f4) |
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| 57 | /* Alternate event code for Run_cycles */ |
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| 58 | EVENT(PM_RUN_CYC_ALT, 0x200f4) |
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| 59 | /* Instruction Dispatched */ |
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| 60 | EVENT(PM_INST_DISP, 0x200f2) |
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| 61 | EVENT(PM_INST_DISP_ALT, 0x300f2) |
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| 62 | /* Branch event that are not strongly biased */ |
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| 63 | EVENT(PM_BR_2PATH, 0x20036) |
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| 64 | /* ALternate branch event that are not strongly biased */ |
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| 65 | EVENT(PM_BR_2PATH_ALT, 0x40036) |
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| 66 | |
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| 67 | /* Blacklisted events */ |
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| 68 | EVENT(PM_MRK_ST_DONE_L2, 0x10134) |
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| 69 | EVENT(PM_RADIX_PWC_L1_HIT, 0x1f056) |
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| 70 | EVENT(PM_FLOP_CMPL, 0x100f4) |
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| 71 | EVENT(PM_MRK_NTF_FIN, 0x20112) |
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| 72 | EVENT(PM_RADIX_PWC_L2_HIT, 0x2d024) |
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| 73 | EVENT(PM_IFETCH_THROTTLE, 0x3405e) |
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| 74 | EVENT(PM_MRK_L2_TM_ST_ABORT_SISTER, 0x3e15c) |
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| 75 | EVENT(PM_RADIX_PWC_L3_HIT, 0x3f056) |
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| 76 | EVENT(PM_RUN_CYC_SMT2_MODE, 0x3006c) |
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| 77 | EVENT(PM_TM_TX_PASS_RUN_INST, 0x4e014) |
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| 78 | EVENT(PM_DISP_HELD_SYNC_HOLD, 0x4003c) |
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| 79 | EVENT(PM_DTLB_MISS_16G, 0x1c058) |
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| 80 | EVENT(PM_DERAT_MISS_2M, 0x1c05a) |
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| 81 | EVENT(PM_DTLB_MISS_2M, 0x1c05c) |
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| 82 | EVENT(PM_MRK_DTLB_MISS_1G, 0x1d15c) |
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| 83 | EVENT(PM_DTLB_MISS_4K, 0x2c056) |
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| 84 | EVENT(PM_DERAT_MISS_1G, 0x2c05a) |
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| 85 | EVENT(PM_MRK_DERAT_MISS_2M, 0x2d152) |
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| 86 | EVENT(PM_MRK_DTLB_MISS_4K, 0x2d156) |
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| 87 | EVENT(PM_MRK_DTLB_MISS_16G, 0x2d15e) |
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| 88 | EVENT(PM_DTLB_MISS_64K, 0x3c056) |
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| 89 | EVENT(PM_MRK_DERAT_MISS_1G, 0x3d152) |
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| 90 | EVENT(PM_MRK_DTLB_MISS_64K, 0x3d156) |
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| 91 | EVENT(PM_DTLB_MISS_16M, 0x4c056) |
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| 92 | EVENT(PM_DTLB_MISS_1G, 0x4c05a) |
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| 93 | EVENT(PM_MRK_DTLB_MISS_16M, 0x4c15e) |
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| 94 | |
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| 95 | /* |
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| 96 | * Memory Access Events |
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| 97 | * |
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| 98 | * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0) |
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| 99 | * To enable capturing of memory profiling, these MMCRA bits |
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| 100 | * needs to be programmed and corresponding raw event format |
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| 101 | * encoding. |
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| 102 | * |
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| 103 | * MMCRA bits encoding needed are |
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| 104 | * SM (Sampling Mode) |
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| 105 | * EM (Eligibility for Random Sampling) |
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| 106 | * TECE (Threshold Event Counter Event) |
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| 107 | * TS (Threshold Start Event) |
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| 108 | * TE (Threshold End Event) |
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| 109 | * |
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| 110 | * Corresponding Raw Encoding bits: |
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| 111 | * sample [EM,SM] |
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| 112 | * thresh_sel (TECE) |
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| 113 | * thresh start (TS) |
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| 114 | * thresh end (TE) |
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| 115 | */ |
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| 116 | EVENT(MEM_LOADS, 0x34340401e0) |
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| 117 | EVENT(MEM_STORES, 0x343c0401e0) |
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| 118 | |
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